Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
17 #include "clk-regmap.h"
18 #include "clk-pll.h"
19 #include "clk-mpll.h"
21 #include "meson-eeclk.h"
26 .data = &(struct meson_clk_pll_data){
29 .shift = 30,
34 .shift = 0,
39 .shift = 9,
44 .shift = 0,
49 .shift = 31,
54 .shift = 29,
69 .data = &(struct clk_regmap_div_data){
71 .shift = 16,
90 .data = &(struct meson_clk_pll_data){
93 .shift = 30,
98 .shift = 0,
103 .shift = 9,
108 .shift = 31,
113 .shift = 29,
128 .data = &(struct clk_regmap_div_data){
130 .shift = 16,
187 .data = &(struct meson_clk_pll_data){
190 .shift = 30,
195 .shift = 0,
200 .shift = 9,
205 .shift = 0,
210 .shift = 31,
215 .shift = 29,
233 .data = &(struct clk_regmap_div_data){
235 .shift = 16,
259 .data = &(struct meson_clk_pll_data){
262 .shift = 30,
267 .shift = 0,
272 .shift = 9,
277 .shift = 0,
282 .shift = 31,
287 .shift = 29,
306 .data = &(struct clk_regmap_div_data){
308 .shift = 16,
335 .data = &(struct clk_regmap_gate_data){
362 .data = &(struct clk_regmap_gate_data){
381 * b) CCF has a clock hand-off mechanism to make the sure the
400 .data = &(struct clk_regmap_gate_data){
426 .data = &(struct clk_regmap_gate_data){
454 .data = &(struct clk_regmap_gate_data){
469 .data = &(struct clk_regmap_div_data){
471 .shift = 12,
485 .data = &(struct meson_clk_mpll_data){
488 .shift = 0,
493 .shift = 15,
498 .shift = 16,
503 .shift = 0,
520 .data = &(struct clk_regmap_gate_data){
536 .data = &(struct meson_clk_mpll_data){
539 .shift = 0,
544 .shift = 15,
549 .shift = 16,
554 .shift = 1,
571 .data = &(struct clk_regmap_gate_data){
587 .data = &(struct meson_clk_mpll_data){
590 .shift = 0,
595 .shift = 15,
600 .shift = 16,
605 .shift = 25,
610 .shift = 2,
627 .data = &(struct clk_regmap_gate_data){
643 .data = &(struct meson_clk_mpll_data){
646 .shift = 12,
651 .shift = 11,
656 .shift = 2,
661 .shift = 3,
678 .data = &(struct clk_regmap_gate_data){
712 .data = &(struct meson_clk_pll_data){
715 .shift = 30,
720 .shift = 0,
725 .shift = 9,
730 .shift = 0,
735 .shift = 31,
740 .shift = 29,
758 .data = &(struct clk_regmap_div_data){
760 .shift = 16,
776 .data = &(struct clk_regmap_div_data){
778 .shift = 6,
794 .data = &(struct clk_regmap_mux_data){
797 .shift = 2,
811 .data = &(struct clk_regmap_mux_data){
814 .shift = 1,
828 .data = &(struct clk_regmap_gate_data){
843 .data = &(struct clk_regmap_gate_data){
868 .data = &(struct clk_regmap_mux_data){
871 .shift = 12,
883 .data = &(struct clk_regmap_div_data){
885 .shift = 0,
900 .data = &(struct clk_regmap_gate_data){
931 .data = &(struct clk_regmap_mux_data){
934 .shift = 25,
946 .data = &(struct clk_regmap_div_data){
948 .shift = 16,
964 .data = &(struct clk_regmap_gate_data){
981 .data = &(struct clk_regmap_mux_data){
984 .shift = 9,
996 .data = &(struct clk_regmap_div_data){
998 .shift = 0,
1014 .data = &(struct clk_regmap_gate_data){
1046 .data = &(struct clk_regmap_mux_data){
1049 .shift = 12,
1067 .data = &(struct clk_regmap_div_data){
1069 .shift = 0,
1084 .data = &(struct clk_regmap_gate_data){
1354 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
1361 .name = "axg-clkc",