Lines Matching +full:data +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
13 #include "clk-regmap.h"
14 #include "clk-pll.h"
15 #include "clk-mpll.h"
16 #include "meson-eeclk.h"
17 #include "vid-pll-div.h"
86 .data = &(struct meson_clk_pll_data){
90 .width = 1,
95 .width = 9,
100 .width = 5,
105 .width = 12,
110 .width = 1,
115 .width = 1,
129 .data = &(struct clk_regmap_div_data){
132 .width = 2,
163 .data = &(struct meson_clk_pll_data){
167 .width = 1,
172 .width = 9,
177 .width = 5,
182 .width = 12,
187 .width = 1,
192 .width = 1,
211 .data = &(struct meson_clk_pll_data){
215 .width = 1,
220 .width = 9,
225 .width = 5,
236 .width = 10,
241 .width = 1,
246 .width = 1,
265 .data = &(struct clk_regmap_div_data){
268 .width = 2,
283 .data = &(struct clk_regmap_div_data){
286 .width = 2,
301 .data = &(struct clk_regmap_div_data){
304 .width = 2,
319 .data = &(struct clk_regmap_div_data){
322 .width = 2,
337 .data = &(struct clk_regmap_div_data){
340 .width = 2,
355 .data = &(struct clk_regmap_div_data){
358 .width = 2,
373 .data = &(struct meson_clk_pll_data){
377 .width = 1,
382 .width = 9,
387 .width = 5,
392 .width = 1,
397 .width = 1,
411 .data = &(struct clk_regmap_div_data){
414 .width = 2,
435 .data = &(struct meson_clk_pll_data){
439 .width = 1,
444 .width = 9,
449 .width = 5,
454 .width = 1,
459 .width = 1,
484 .data = &(struct meson_clk_pll_data){
488 .width = 1,
493 .width = 9,
498 .width = 5,
503 .width = 10,
508 .width = 1,
513 .width = 1,
530 .data = &(struct clk_regmap_div_data){
533 .width = 2,
548 .index = -1,
569 .data = &(struct clk_regmap_gate_data){
596 .data = &(struct clk_regmap_gate_data){
615 * b) CCF has a clock hand-off mechanism to make the sure the
634 .data = &(struct clk_regmap_gate_data){
660 .data = &(struct clk_regmap_gate_data){
686 .data = &(struct clk_regmap_gate_data){
701 .data = &(struct clk_regmap_div_data){
704 .width = 1,
715 .data = &(struct meson_clk_mpll_data){
719 .width = 14,
724 .width = 1,
729 .width = 9,
744 .data = &(struct meson_clk_mpll_data){
748 .width = 14,
753 .width = 1,
758 .width = 9,
773 .data = &(struct clk_regmap_gate_data){
788 .index = -1,
796 .data = &(struct meson_clk_mpll_data){
800 .width = 14,
805 .width = 1,
810 .width = 9,
825 .data = &(struct clk_regmap_gate_data){
839 .data = &(struct meson_clk_mpll_data){
843 .width = 14,
848 .width = 1,
853 .width = 9,
868 .data = &(struct clk_regmap_gate_data){
893 .data = &(struct clk_regmap_mux_data){
913 .data = &(struct clk_regmap_div_data){
916 .width = 7,
930 .data = &(struct clk_regmap_gate_data){
946 .data = &(struct clk_regmap_mux_data){
964 .data = &(struct clk_regmap_div_data){
967 .width = 8,
981 .data = &(struct clk_regmap_gate_data){
998 * muxed by a glitch-free switch. The CCF can manage this glitch-free
999 * mux because it does top-to-bottom updates the each clock tree and
1015 .data = &(struct clk_regmap_mux_data){
1036 .data = &(struct clk_regmap_div_data){
1039 .width = 7,
1053 .data = &(struct clk_regmap_gate_data){
1069 .data = &(struct clk_regmap_mux_data){
1090 .data = &(struct clk_regmap_div_data){
1093 .width = 7,
1107 .data = &(struct clk_regmap_gate_data){
1128 .data = &(struct clk_regmap_mux_data){
1143 .data = &(struct clk_regmap_mux_data){
1163 .data = &(struct clk_regmap_div_data) {
1166 .width = 8,
1181 .data = &(struct clk_regmap_gate_data){
1197 .data = &(struct clk_regmap_mux_data){
1217 .data = &(struct clk_regmap_div_data){
1220 .width = 8,
1235 .data = &(struct clk_regmap_gate_data){
1251 .data = &(struct clk_regmap_mux_data){
1265 *The parent is specific to origin of the audio data. Let the
1279 { .name = "cts_slow_oscin", .index = -1 },
1285 .data = &(struct clk_regmap_mux_data){
1300 .data = &(struct clk_regmap_div_data){
1303 .width = 14,
1317 .data = &(struct clk_regmap_gate_data){
1348 .data = &(struct clk_regmap_mux_data){
1363 .data = &(struct clk_regmap_div_data){
1366 .width = 7,
1381 .data = &(struct clk_regmap_gate_data){
1398 .data = &(struct clk_regmap_mux_data){
1413 .data = &(struct clk_regmap_div_data){
1416 .width = 7,
1431 .data = &(struct clk_regmap_gate_data){
1448 .data = &(struct clk_regmap_mux_data){
1463 .data = &(struct clk_regmap_div_data){
1466 .width = 7,
1481 .data = &(struct clk_regmap_gate_data){
1506 .data = &(struct clk_regmap_mux_data){
1525 .data = &(struct clk_regmap_div_data){
1528 .width = 7,
1540 .data = &(struct clk_regmap_gate_data){
1554 .data = &(struct clk_regmap_mux_data){
1573 .data = &(struct clk_regmap_div_data){
1576 .width = 7,
1588 .data = &(struct clk_regmap_gate_data){
1602 .data = &(struct clk_regmap_mux_data){
1633 .data = &(struct clk_regmap_mux_data){
1652 .data = &(struct clk_regmap_div_data){
1655 .width = 7,
1669 .data = &(struct clk_regmap_gate_data){
1685 .data = &(struct clk_regmap_mux_data){
1704 .data = &(struct clk_regmap_div_data){
1707 .width = 7,
1721 .data = &(struct clk_regmap_gate_data){
1737 .data = &(struct clk_regmap_mux_data){
1759 .data = &(struct clk_regmap_gate_data){
1775 .data = &(struct meson_vid_pll_div_data){
1779 .width = 15,
1784 .width = 2,
1799 .index = -1,
1815 { .name = "hdmi_pll", .index = -1 },
1819 .data = &(struct clk_regmap_mux_data){
1838 .data = &(struct clk_regmap_gate_data){
1864 .data = &(struct clk_regmap_mux_data){
1884 .data = &(struct clk_regmap_mux_data){
1904 .data = &(struct clk_regmap_gate_data){
1918 .data = &(struct clk_regmap_gate_data){
1932 .data = &(struct clk_regmap_div_data){
1935 .width = 8,
1949 .data = &(struct clk_regmap_div_data){
1952 .width = 8,
1966 .data = &(struct clk_regmap_gate_data){
1980 .data = &(struct clk_regmap_gate_data){
1994 .data = &(struct clk_regmap_gate_data){
2008 .data = &(struct clk_regmap_gate_data){
2022 .data = &(struct clk_regmap_gate_data){
2036 .data = &(struct clk_regmap_gate_data){
2050 .data = &(struct clk_regmap_gate_data){
2064 .data = &(struct clk_regmap_gate_data){
2078 .data = &(struct clk_regmap_gate_data){
2092 .data = &(struct clk_regmap_gate_data){
2106 .data = &(struct clk_regmap_gate_data){
2120 .data = &(struct clk_regmap_gate_data){
2252 .data = &(struct clk_regmap_mux_data){
2268 .data = &(struct clk_regmap_mux_data){
2284 .data = &(struct clk_regmap_mux_data){
2315 .data = &(struct clk_regmap_mux_data){
2337 .data = &(struct clk_regmap_gate_data){
2353 .data = &(struct clk_regmap_gate_data){
2369 .data = &(struct clk_regmap_gate_data){
2385 .data = &(struct clk_regmap_gate_data){
2410 .data = &(struct clk_regmap_mux_data){
2426 .data = &(struct clk_regmap_div_data){
2429 .width = 7,
2441 .data = &(struct clk_regmap_gate_data){
2464 .data = &(struct clk_regmap_mux_data){
2480 .data = &(struct clk_regmap_div_data){
2483 .width = 7,
2498 .data = &(struct clk_regmap_gate_data){
2514 .data = &(struct clk_regmap_mux_data){
2530 .data = &(struct clk_regmap_div_data){
2533 .width = 7,
2548 .data = &(struct clk_regmap_gate_data){
2580 .data = &(struct clk_regmap_mux_data){
2601 .data = &(struct clk_regmap_div_data){
2604 .width = 11,
2618 .data = &(struct clk_regmap_gate_data){
3556 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3557 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3564 .name = "gxbb-clkc",