Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
15 #include <linux/reset-controller.h>
20 #include "clk-regmap.h"
21 #include "clk-pll.h"
22 #include "clk-mpll.h"
65 .data = &(struct meson_clk_pll_data){
68 .shift = 30,
73 .shift = 0,
78 .shift = 9,
83 .shift = 0,
88 .shift = 31,
93 .shift = 29,
103 .index = -1,
110 .data = &(struct clk_regmap_div_data){
112 .shift = 16,
131 .data = &(struct meson_clk_pll_data){
134 .shift = 30,
139 .shift = 0,
144 .shift = 10,
149 .shift = 0,
154 .shift = 31,
159 .shift = 29,
170 .index = -1,
177 .data = &(struct clk_regmap_div_data){
179 .shift = 16,
195 .data = &(struct clk_regmap_div_data){
197 .shift = 18,
213 .data = &(struct meson_clk_pll_data){
216 .shift = 30,
221 .shift = 0,
226 .shift = 9,
231 .shift = 31,
236 .shift = 29,
247 .index = -1,
254 .data = &(struct clk_regmap_div_data){
256 .shift = 16,
285 .data = &(struct clk_regmap_gate_data){
313 .data = &(struct clk_regmap_gate_data){
341 .data = &(struct clk_regmap_gate_data){
369 .data = &(struct clk_regmap_gate_data){
397 .data = &(struct clk_regmap_gate_data){
412 .data = &(struct clk_regmap_div_data){
414 .shift = 12,
428 .data = &(struct meson_clk_mpll_data){
431 .shift = 0,
436 .shift = 15,
441 .shift = 16,
446 .shift = 25,
462 .data = &(struct clk_regmap_gate_data){
478 .data = &(struct meson_clk_mpll_data){
481 .shift = 0,
486 .shift = 15,
491 .shift = 16,
507 .data = &(struct clk_regmap_gate_data){
523 .data = &(struct meson_clk_mpll_data){
526 .shift = 0,
531 .shift = 15,
536 .shift = 16,
552 .data = &(struct clk_regmap_gate_data){
569 .data = &(struct clk_regmap_mux_data){
572 .shift = 12,
593 .data = &(struct clk_regmap_div_data){
595 .shift = 0,
609 .data = &(struct clk_regmap_gate_data){
625 .data = &(struct clk_regmap_mux_data){
628 .shift = 0,
634 { .fw_name = "xtal", .name = "xtal", .index = -1, },
684 .data = &(struct clk_regmap_div_data){
686 .shift = 20,
704 .data = &(struct clk_regmap_mux_data){
707 .shift = 2,
730 .data = &(struct clk_regmap_mux_data){
733 .shift = 7,
739 { .fw_name = "xtal", .name = "xtal", .index = -1, },
750 .data = &(struct clk_regmap_mux_data){
753 .shift = 9,
765 { .fw_name = "xtal", .name = "xtal", .index = -1, },
773 .data = &(struct clk_regmap_div_data){
775 .shift = 0,
791 .data = &(struct clk_regmap_gate_data){
899 .data = &(struct clk_regmap_mux_data){
902 .shift = 3,
922 .data = &(struct clk_regmap_gate_data){
939 .data = &(struct clk_regmap_mux_data){
942 .shift = 6,
961 .data = &(struct clk_regmap_gate_data){
979 .data = &(struct clk_regmap_mux_data){
982 .shift = 9,
1002 .data = &(struct clk_regmap_gate_data){
1019 .data = &(struct clk_regmap_mux_data){
1022 .shift = 12,
1041 .data = &(struct clk_regmap_gate_data){
1058 .data = &(struct clk_regmap_mux_data){
1061 .shift = 15,
1081 .data = &(struct clk_regmap_gate_data){
1097 .data = &(struct clk_regmap_div_data){
1099 .shift = 4,
1114 .data = &(struct clk_regmap_div_data){
1116 .shift = 12,
1131 .data = &(struct clk_regmap_mux_data){
1134 .shift = 8,
1150 .data = &(struct clk_regmap_div_data){
1152 .shift = 0,
1177 .data = &(struct clk_regmap_mux_data){
1180 .shift = 16,
1192 .data = &(struct clk_regmap_gate_data){
1208 .data = &(struct clk_regmap_gate_data){
1224 .data = &(struct clk_regmap_gate_data){
1254 .data = &(struct clk_regmap_gate_data){
1284 .data = &(struct clk_regmap_gate_data){
1314 .data = &(struct clk_regmap_gate_data){
1344 .data = &(struct clk_regmap_gate_data){
1360 .data = &(struct clk_regmap_mux_data){
1363 .shift = 16,
1375 .data = &(struct clk_regmap_gate_data){
1391 .data = &(struct clk_regmap_gate_data){
1407 .data = &(struct clk_regmap_gate_data){
1437 .data = &(struct clk_regmap_gate_data){
1467 .data = &(struct clk_regmap_gate_data){
1497 .data = &(struct clk_regmap_gate_data){
1527 .data = &(struct clk_regmap_gate_data){
1551 .data = &(struct clk_regmap_mux_data){
1554 .shift = 20,
1566 .data = &(struct clk_regmap_gate_data){
1582 .data = &(struct clk_regmap_mux_data){
1585 .shift = 24,
1597 .data = &(struct clk_regmap_gate_data){
1613 .data = &(struct clk_regmap_mux_data){
1616 .shift = 28,
1628 .data = &(struct clk_regmap_gate_data){
1644 .data = &(struct clk_regmap_mux_data){
1647 .shift = 16,
1659 .data = &(struct clk_regmap_gate_data){
1683 .data = &(struct clk_regmap_mux_data){
1686 .shift = 12,
1698 .data = &(struct clk_regmap_gate_data){
1714 .data = &(struct clk_regmap_mux_data){
1717 .shift = 28,
1729 .data = &(struct clk_regmap_gate_data){
1745 .data = &(struct clk_regmap_mux_data){
1748 .shift = 9,
1758 .index = -1,
1766 .data = &(struct clk_regmap_div_data){
1768 .shift = 0,
1783 .data = &(struct clk_regmap_gate_data){
1800 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
1801 * actually manage this glitch-free mux because it does top-to-bottom
1804 * Meson8 only has mali_0 and no glitch-free mux.
1807 { .fw_name = "xtal", .name = "xtal", .index = -1, },
1819 .data = &(struct clk_regmap_mux_data){
1822 .shift = 9,
1841 .data = &(struct clk_regmap_div_data){
1843 .shift = 0,
1858 .data = &(struct clk_regmap_gate_data){
1874 .data = &(struct clk_regmap_mux_data){
1877 .shift = 25,
1896 .data = &(struct clk_regmap_div_data){
1898 .shift = 16,
1913 .data = &(struct clk_regmap_gate_data){
1929 .data = &(struct clk_regmap_mux_data){
1932 .shift = 31,
1959 .data = &(struct meson_clk_pll_data){
1962 .shift = 30,
1967 .shift = 0,
1972 .shift = 9,
1977 .shift = 31,
1982 .shift = 29,
1995 .index = -1,
2002 .data = &(struct clk_regmap_div_data){
2004 .shift = 16,
2034 .data = &(struct clk_regmap_mux_data){
2037 .shift = 9,
2049 .data = &(struct clk_regmap_mux_data){
2052 .shift = 9,
2064 .data = &(struct clk_regmap_div_data){
2066 .shift = 0,
2081 .index = -1,
2089 .data = &(struct clk_regmap_gate_data){
2105 .data = &(struct clk_regmap_mux_data){
2108 .shift = 25,
2120 .data = &(struct clk_regmap_mux_data){
2123 .shift = 25,
2135 .data = &(struct clk_regmap_div_data){
2137 .shift = 16,
2152 .index = -1,
2160 .data = &(struct clk_regmap_gate_data){
2177 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
2178 * actually manage this glitch-free mux because it does top-to-bottom
2181 * Meson8 only has vpu_0 and no glitch-free mux.
2184 .data = &(struct clk_regmap_mux_data){
2187 .shift = 31,
2211 .data = &(struct clk_regmap_mux_data){
2214 .shift = 9,
2227 .data = &(struct clk_regmap_div_data){
2229 .shift = 0,
2245 .data = &(struct clk_regmap_gate_data){
2261 .data = &(struct clk_regmap_div_data){
2263 .shift = 0,
2279 .data = &(struct clk_regmap_gate_data){
2295 .data = &(struct clk_regmap_mux_data){
2298 .shift = 15,
2314 .data = &(struct clk_regmap_mux_data){
2317 .shift = 25,
2330 .data = &(struct clk_regmap_div_data){
2332 .shift = 16,
2348 .data = &(struct clk_regmap_gate_data){
2364 .data = &(struct clk_regmap_mux_data){
2367 .shift = 9,
2380 .data = &(struct clk_regmap_div_data){
2382 .shift = 0,
2398 .data = &(struct clk_regmap_gate_data){
2414 .data = &(struct clk_regmap_mux_data){
2417 .shift = 25,
2430 .data = &(struct clk_regmap_div_data){
2432 .shift = 16,
2448 .data = &(struct clk_regmap_gate_data){
2464 .data = &(struct clk_regmap_mux_data){
2467 .shift = 31,
2492 .data = &(struct clk_regmap_mux_data){
2495 .shift = 9,
2508 .data = &(struct clk_regmap_div_data) {
2510 .shift = 0,
2526 .data = &(struct clk_regmap_gate_data){
2551 .data = &(struct clk_regmap_mux_data){
2554 .shift = 25,
2567 .data = &(struct clk_regmap_div_data){
2569 .shift = 16,
2585 .data = &(struct clk_regmap_gate_data){
2601 .data = &(struct clk_regmap_mux_data){
2604 .shift = 27,
2615 * The parent is specific to origin of the audio data. Let the
3653 return -EINVAL; in meson8b_clk_reset_update()
3657 if (assert != reset->active_low) in meson8b_clk_reset_update()
3658 value = BIT(reset->bit_idx); in meson8b_clk_reset_update()
3662 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, in meson8b_clk_reset_update()
3663 BIT(reset->bit_idx), value); in meson8b_clk_reset_update()
3693 unsigned long event, void *data) in meson8b_cpu_clk_notifier_cb() argument
3703 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0); in meson8b_cpu_clk_notifier_cb()
3708 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1); in meson8b_cpu_clk_notifier_cb()
3715 ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk); in meson8b_cpu_clk_notifier_cb()
3746 pr_info("failed to get HHI regmap - Trying obsolete regs\n"); in meson8b_clkc_init_common()
3748 /* Generic clocks, PLLs and some of the reset-bits */ in meson8b_clkc_init_common()
3765 rstc->regmap = map; in meson8b_clkc_init_common()
3766 rstc->reset.ops = &meson8b_clk_reset_ops; in meson8b_clkc_init_common()
3767 rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits); in meson8b_clkc_init_common()
3768 rstc->reset.of_node = np; in meson8b_clkc_init_common()
3769 ret = reset_controller_register(&rstc->reset); in meson8b_clkc_init_common()
3778 meson8b_clk_regmaps[i]->map = map; in meson8b_clkc_init_common()
3792 if (!clk_hw_onecell_data->hws[i]) in meson8b_clkc_init_common()
3795 ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]); in meson8b_clkc_init_common()
3800 meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK]; in meson8b_clkc_init_common()
3837 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
3839 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
3841 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",