21  * rate - rate is adjustable.  clk->rate = ceiling(parent->rate / divisor)
49 					 unsigned long rate, u16 flags)  in zynqmp_divider_get_val()  argument
55 		up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);  in zynqmp_divider_get_val()
56 		down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate);  in zynqmp_divider_get_val()
64 		return (rate - up_rate) <= (down_rate - rate) ? up : down;  in zynqmp_divider_get_val()
67 		return DIV_ROUND_CLOSEST(parent_rate, rate);  in zynqmp_divider_get_val()
72  * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
74  * @parent_rate:	rate of parent clock
113 				    unsigned long rate,  in zynqmp_get_divider2_val()  argument
137 			long new_error = ((div1_prate / div1) / div2) - rate;  in zynqmp_get_divider2_val()
156  * zynqmp_clk_divider_round_rate() - Round rate of divider clock
158  * @rate:		rate of clock to be set
159  * @prate:		rate of parent clock
164 					  unsigned long rate,  in zynqmp_clk_divider_round_rate()  argument
192 	bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags);  in zynqmp_clk_divider_round_rate()
201 		zynqmp_get_divider2_val(hw, rate, divider, &bestdiv);  in zynqmp_clk_divider_round_rate()
205 		bestdiv = rate % *prate ? 1 : bestdiv;  in zynqmp_clk_divider_round_rate()
208 	*prate = rate * bestdiv;  in zynqmp_clk_divider_round_rate()
210 	return rate;  in zynqmp_clk_divider_round_rate()
214  * zynqmp_clk_divider_set_rate() - Set rate of divider clock
216  * @rate:		rate of clock to be set
217  * @parent_rate:	rate of parent clock
221 static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,  in zynqmp_clk_divider_set_rate()  argument
231 	value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);  in zynqmp_clk_divider_set_rate()
328 	 * To achieve best possible rate, maximum limit of divider is required  in zynqmp_clk_register_divider()