1 // SPDX-License-Identifier: GPL-2.0
5  *  Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14  * struct zynqmp_pll - PLL clock
15  * @hw:		Handle between common and hardware-specific interfaces
16  * @clk_id:	PLL clock ID
43  * zynqmp_pll_get_mode() - Get mode of PLL
44  * @hw:		Handle between common and hardware-specific interfaces
46  * Return: Mode of PLL
51 	u32 clk_id = clk->clk_id;  in zynqmp_pll_get_mode()
58 		pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n",  in zynqmp_pll_get_mode()
65  * zynqmp_pll_set_mode() - Set the PLL mode
66  * @hw:		Handle between common and hardware-specific interfaces
67  * @on:		Flag to determine the mode
72 	u32 clk_id = clk->clk_id;  in zynqmp_pll_set_mode()
75 	u32 mode;  in zynqmp_pll_set_mode()  local
78 		mode = PLL_MODE_FRAC;  in zynqmp_pll_set_mode()
80 		mode = PLL_MODE_INT;  in zynqmp_pll_set_mode()
82 	ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode);  in zynqmp_pll_set_mode()
84 		pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n",  in zynqmp_pll_set_mode()
87 		clk->set_pll_mode = true;  in zynqmp_pll_set_mode()
91  * zynqmp_pll_round_rate() - Round a clock frequency
92  * @hw:		Handle between common and hardware-specific interfaces
93  * @rate:	Desired clock frequency
94  * @prate:	Clock frequency of parent clock
104 	/* Enable the fractional mode if needed */  in zynqmp_pll_round_rate()
125  * zynqmp_pll_recalc_rate() - Recalculate clock frequency
126  * @hw:			Handle between common and hardware-specific interfaces
127  * @parent_rate:	Clock frequency of parent clock
129  * Return: Current clock frequency
135 	u32 clk_id = clk->clk_id;  in zynqmp_pll_recalc_rate()
159  * zynqmp_pll_set_rate() - Set rate of PLL
160  * @hw:			Handle between common and hardware-specific interfaces
161  * @rate:		Frequency of clock to be set
162  * @parent_rate:	Clock frequency of parent clock
172 	u32 clk_id = clk->clk_id;  in zynqmp_pll_set_rate()
189 		if (ret == -EUSERS)  in zynqmp_pll_set_rate()
211  * zynqmp_pll_is_enabled() - Check if a clock is enabled
212  * @hw:		Handle between common and hardware-specific interfaces
214  * Return: 1 if the clock is enabled, 0 otherwise
220 	u32 clk_id = clk->clk_id;  in zynqmp_pll_is_enabled()
226 		pr_warn_once("%s() clock get state failed for %s, ret = %d\n",  in zynqmp_pll_is_enabled()
228 		return -EIO;  in zynqmp_pll_is_enabled()
235  * zynqmp_pll_enable() - Enable clock
236  * @hw:		Handle between common and hardware-specific interfaces
244 	u32 clk_id = clk->clk_id;  in zynqmp_pll_enable()
248 	 * Don't skip enabling clock if there is an IOCTL_SET_PLL_FRAC_MODE request  in zynqmp_pll_enable()
251 	if (zynqmp_pll_is_enabled(hw) && (!clk->set_pll_mode))  in zynqmp_pll_enable()
254 	clk->set_pll_mode = false;  in zynqmp_pll_enable()
258 		pr_warn_once("%s() clock enable failed for %s, ret = %d\n",  in zynqmp_pll_enable()
265  * zynqmp_pll_disable() - Disable clock
266  * @hw:		Handle between common and hardware-specific interfaces
272 	u32 clk_id = clk->clk_id;  in zynqmp_pll_disable()
280 		pr_warn_once("%s() clock disable failed for %s, ret = %d\n",  in zynqmp_pll_disable()
294  * zynqmp_clk_register_pll() - Register PLL with the clock framework
296  * @clk_id:		Clock ID
297  * @parents:		Name of this clock's parents
299  * @nodes:		Clock topology node
301  * Return: clock hardware to the registered clock
315 	init.flags = nodes->flag;  in zynqmp_clk_register_pll()
321 		return ERR_PTR(-ENOMEM);  in zynqmp_clk_register_pll()
323 	pll->hw.init = &init;  in zynqmp_clk_register_pll()
324 	pll->clk_id = clk_id;  in zynqmp_clk_register_pll()
326 	hw = &pll->hw;  in zynqmp_clk_register_pll()