Lines Matching +full:0 +full:- +full:32
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2009 ST-Ericsson AB
35 /* Reset OS Timer 32bit (-/W) */
36 #define U300_TIMER_APP_ROST (0x0000)
37 #define U300_TIMER_APP_ROST_TIMER_RESET (0x00000000)
38 /* Enable OS Timer 32bit (-/W) */
39 #define U300_TIMER_APP_EOST (0x0004)
40 #define U300_TIMER_APP_EOST_TIMER_ENABLE (0x00000000)
41 /* Disable OS Timer 32bit (-/W) */
42 #define U300_TIMER_APP_DOST (0x0008)
43 #define U300_TIMER_APP_DOST_TIMER_DISABLE (0x00000000)
44 /* OS Timer Mode Register 32bit (-/W) */
45 #define U300_TIMER_APP_SOSTM (0x000c)
46 #define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS (0x00000000)
47 #define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT (0x00000001)
48 /* OS Timer Status Register 32bit (R/-) */
49 #define U300_TIMER_APP_OSTS (0x0010)
50 #define U300_TIMER_APP_OSTS_TIMER_STATE_MASK (0x0000000F)
51 #define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE (0x00000001)
52 #define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE (0x00000002)
53 #define U300_TIMER_APP_OSTS_ENABLE_IND (0x00000010)
54 #define U300_TIMER_APP_OSTS_MODE_MASK (0x00000020)
55 #define U300_TIMER_APP_OSTS_MODE_CONTINUOUS (0x00000000)
56 #define U300_TIMER_APP_OSTS_MODE_ONE_SHOT (0x00000020)
57 #define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND (0x00000040)
58 #define U300_TIMER_APP_OSTS_IRQ_PENDING_IND (0x00000080)
59 /* OS Timer Current Count Register 32bit (R/-) */
60 #define U300_TIMER_APP_OSTCC (0x0014)
61 /* OS Timer Terminal Count Register 32bit (R/W) */
62 #define U300_TIMER_APP_OSTTC (0x0018)
63 /* OS Timer Interrupt Enable Register 32bit (-/W) */
64 #define U300_TIMER_APP_OSTIE (0x001c)
65 #define U300_TIMER_APP_OSTIE_IRQ_DISABLE (0x00000000)
66 #define U300_TIMER_APP_OSTIE_IRQ_ENABLE (0x00000001)
67 /* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
68 #define U300_TIMER_APP_OSTIA (0x0020)
69 #define U300_TIMER_APP_OSTIA_IRQ_ACK (0x00000080)
71 /* Reset DD Timer 32bit (-/W) */
72 #define U300_TIMER_APP_RDDT (0x0040)
73 #define U300_TIMER_APP_RDDT_TIMER_RESET (0x00000000)
74 /* Enable DD Timer 32bit (-/W) */
75 #define U300_TIMER_APP_EDDT (0x0044)
76 #define U300_TIMER_APP_EDDT_TIMER_ENABLE (0x00000000)
77 /* Disable DD Timer 32bit (-/W) */
78 #define U300_TIMER_APP_DDDT (0x0048)
79 #define U300_TIMER_APP_DDDT_TIMER_DISABLE (0x00000000)
80 /* DD Timer Mode Register 32bit (-/W) */
81 #define U300_TIMER_APP_SDDTM (0x004c)
82 #define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS (0x00000000)
83 #define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT (0x00000001)
84 /* DD Timer Status Register 32bit (R/-) */
85 #define U300_TIMER_APP_DDTS (0x0050)
86 #define U300_TIMER_APP_DDTS_TIMER_STATE_MASK (0x0000000F)
87 #define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE (0x00000001)
88 #define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE (0x00000002)
89 #define U300_TIMER_APP_DDTS_ENABLE_IND (0x00000010)
90 #define U300_TIMER_APP_DDTS_MODE_MASK (0x00000020)
91 #define U300_TIMER_APP_DDTS_MODE_CONTINUOUS (0x00000000)
92 #define U300_TIMER_APP_DDTS_MODE_ONE_SHOT (0x00000020)
93 #define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND (0x00000040)
94 #define U300_TIMER_APP_DDTS_IRQ_PENDING_IND (0x00000080)
95 /* DD Timer Current Count Register 32bit (R/-) */
96 #define U300_TIMER_APP_DDTCC (0x0054)
97 /* DD Timer Terminal Count Register 32bit (R/W) */
98 #define U300_TIMER_APP_DDTTC (0x0058)
99 /* DD Timer Interrupt Enable Register 32bit (-/W) */
100 #define U300_TIMER_APP_DDTIE (0x005c)
101 #define U300_TIMER_APP_DDTIE_IRQ_DISABLE (0x00000000)
102 #define U300_TIMER_APP_DDTIE_IRQ_ENABLE (0x00000001)
103 /* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
104 #define U300_TIMER_APP_DDTIA (0x0060)
105 #define U300_TIMER_APP_DDTIA_IRQ_ACK (0x00000080)
107 /* Reset GP1 Timer 32bit (-/W) */
108 #define U300_TIMER_APP_RGPT1 (0x0080)
109 #define U300_TIMER_APP_RGPT1_TIMER_RESET (0x00000000)
110 /* Enable GP1 Timer 32bit (-/W) */
111 #define U300_TIMER_APP_EGPT1 (0x0084)
112 #define U300_TIMER_APP_EGPT1_TIMER_ENABLE (0x00000000)
113 /* Disable GP1 Timer 32bit (-/W) */
114 #define U300_TIMER_APP_DGPT1 (0x0088)
115 #define U300_TIMER_APP_DGPT1_TIMER_DISABLE (0x00000000)
116 /* GP1 Timer Mode Register 32bit (-/W) */
117 #define U300_TIMER_APP_SGPT1M (0x008c)
118 #define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS (0x00000000)
119 #define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT (0x00000001)
120 /* GP1 Timer Status Register 32bit (R/-) */
121 #define U300_TIMER_APP_GPT1S (0x0090)
122 #define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK (0x0000000F)
123 #define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE (0x00000001)
124 #define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE (0x00000002)
125 #define U300_TIMER_APP_GPT1S_ENABLE_IND (0x00000010)
126 #define U300_TIMER_APP_GPT1S_MODE_MASK (0x00000020)
127 #define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS (0x00000000)
128 #define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT (0x00000020)
129 #define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND (0x00000040)
130 #define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND (0x00000080)
131 /* GP1 Timer Current Count Register 32bit (R/-) */
132 #define U300_TIMER_APP_GPT1CC (0x0094)
133 /* GP1 Timer Terminal Count Register 32bit (R/W) */
134 #define U300_TIMER_APP_GPT1TC (0x0098)
135 /* GP1 Timer Interrupt Enable Register 32bit (-/W) */
136 #define U300_TIMER_APP_GPT1IE (0x009c)
137 #define U300_TIMER_APP_GPT1IE_IRQ_DISABLE (0x00000000)
138 #define U300_TIMER_APP_GPT1IE_IRQ_ENABLE (0x00000001)
139 /* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
140 #define U300_TIMER_APP_GPT1IA (0x00a0)
141 #define U300_TIMER_APP_GPT1IA_IRQ_ACK (0x00000080)
143 /* Reset GP2 Timer 32bit (-/W) */
144 #define U300_TIMER_APP_RGPT2 (0x00c0)
145 #define U300_TIMER_APP_RGPT2_TIMER_RESET (0x00000000)
146 /* Enable GP2 Timer 32bit (-/W) */
147 #define U300_TIMER_APP_EGPT2 (0x00c4)
148 #define U300_TIMER_APP_EGPT2_TIMER_ENABLE (0x00000000)
149 /* Disable GP2 Timer 32bit (-/W) */
150 #define U300_TIMER_APP_DGPT2 (0x00c8)
151 #define U300_TIMER_APP_DGPT2_TIMER_DISABLE (0x00000000)
152 /* GP2 Timer Mode Register 32bit (-/W) */
153 #define U300_TIMER_APP_SGPT2M (0x00cc)
154 #define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS (0x00000000)
155 #define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT (0x00000001)
156 /* GP2 Timer Status Register 32bit (R/-) */
157 #define U300_TIMER_APP_GPT2S (0x00d0)
158 #define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK (0x0000000F)
159 #define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE (0x00000001)
160 #define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE (0x00000002)
161 #define U300_TIMER_APP_GPT2S_ENABLE_IND (0x00000010)
162 #define U300_TIMER_APP_GPT2S_MODE_MASK (0x00000020)
163 #define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS (0x00000000)
164 #define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT (0x00000020)
165 #define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND (0x00000040)
166 #define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND (0x00000080)
167 /* GP2 Timer Current Count Register 32bit (R/-) */
168 #define U300_TIMER_APP_GPT2CC (0x00d4)
169 /* GP2 Timer Terminal Count Register 32bit (R/W) */
170 #define U300_TIMER_APP_GPT2TC (0x00d8)
171 /* GP2 Timer Interrupt Enable Register 32bit (-/W) */
172 #define U300_TIMER_APP_GPT2IE (0x00dc)
173 #define U300_TIMER_APP_GPT2IE_IRQ_DISABLE (0x00000000)
174 #define U300_TIMER_APP_GPT2IE_IRQ_ENABLE (0x00000001)
175 /* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
176 #define U300_TIMER_APP_GPT2IA (0x00e0)
177 #define U300_TIMER_APP_GPT2IA_IRQ_ACK (0x00000080)
179 /* Clock request control register - all four timers */
180 #define U300_TIMER_APP_CRC (0x100)
181 #define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001)
198 return 0; in u300_shutdown()
223 writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC); in u300_set_oneshot()
233 return 0; in u300_set_oneshot()
251 writel(cevdata->ticks_per_jiffy, in u300_set_periodic()
265 return 0; in u300_set_periodic()
303 return 0; in u300_set_next_event()
329 evt->event_handler(evt); in u300_timer_interrupt()
363 u300_timer_base = of_iomap(np, 0); in u300_timer_init_of()
366 return -ENXIO; in u300_timer_init_of()
373 return -EINVAL; in u300_timer_init_of()
379 clk = of_clk_get(np, 0); in u300_timer_init_of()
391 sched_clock_register(u300_read_sched_clock, 32, rate); in u300_timer_init_of()
398 * Disable the "OS" and "DD" timers - these are designed for Symbian! in u300_timer_init_of()
426 writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC); in u300_timer_init_of()
439 "GPT2", rate, 300, 32, clocksource_mmio_readl_up); in u300_timer_init_of()
447 1, 0xffffffff); in u300_timer_init_of()
453 return 0; in u300_timer_init_of()
456 TIMER_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",