Lines Matching +full:block +full:- +full:fetch
1 // SPDX-License-Identifier: GPL-2.0-only
15 #include "mtk-platform.h"
77 * Host Interface Adapter(HIA) - the main interface between the host
82 * Command Descriptor Ring Manager(CDR Manager) - keeps track of how many
84 * CD-FIFO and if there's sufficient space for the next block of descriptors,
85 * then it fires off a DMA request to fetch a block of CDs.
87 * Data fetch engine(DFE) - It is responsible for parsing the CD and
91 * Result Descriptor Ring Manager(RDR Manager) - same as CDR Manager,
98 * Data Store Engine(DSE) - It is responsible for parsing the prepared RD
102 * Advanced Interrupt Controllers(AICs) - receive interrupt request signals
105 * - One for the HIA global and processing engine interrupts.
106 * - The others for the descriptor ring interrupts.
123 writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DFE_THR_CTRL); in mtk_desc_ring_link()
124 writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DSE_THR_CTRL); in mtk_desc_ring_link()
130 u32 width = MTK_HIA_DATA_WIDTH(cap->hia_opt) + 2; in mtk_dfe_dse_buf_setup()
131 u32 len = MTK_HIA_DMA_LENGTH(cap->hia_opt) - 1; in mtk_dfe_dse_buf_setup()
132 u32 ipbuf = min((u32)MTK_IN_DBUF_SIZE(cap->hw_opt) + width, len); in mtk_dfe_dse_buf_setup()
133 u32 opbuf = min((u32)MTK_OUT_DBUF_SIZE(cap->hw_opt) + width, len); in mtk_dfe_dse_buf_setup()
134 u32 itbuf = min((u32)MTK_IN_TBUF_SIZE(cap->hw_opt) + width, len); in mtk_dfe_dse_buf_setup()
136 writel(MTK_DFSE_MIN_DATA(ipbuf - 1) | in mtk_dfe_dse_buf_setup()
138 MTK_DFE_MIN_CTRL(itbuf - 1) | in mtk_dfe_dse_buf_setup()
140 cryp->base + DFE_CFG); in mtk_dfe_dse_buf_setup()
142 writel(MTK_DFSE_MIN_DATA(opbuf - 1) | in mtk_dfe_dse_buf_setup()
144 cryp->base + DSE_CFG); in mtk_dfe_dse_buf_setup()
146 writel(MTK_IN_BUF_MIN_THRESH(ipbuf - 1) | in mtk_dfe_dse_buf_setup()
148 cryp->base + PE_IN_DBUF_THRESH); in mtk_dfe_dse_buf_setup()
150 writel(MTK_IN_BUF_MIN_THRESH(itbuf - 1) | in mtk_dfe_dse_buf_setup()
152 cryp->base + PE_IN_TBUF_THRESH); in mtk_dfe_dse_buf_setup()
154 writel(MTK_OUT_BUF_MIN_THRESH(opbuf - 1) | in mtk_dfe_dse_buf_setup()
156 cryp->base + PE_OUT_DBUF_THRESH); in mtk_dfe_dse_buf_setup()
158 writel(0, cryp->base + PE_OUT_TBUF_THRESH); in mtk_dfe_dse_buf_setup()
159 writel(0, cryp->base + PE_OUT_BUF_CTRL); in mtk_dfe_dse_buf_setup()
164 int ret = -EINVAL; in mtk_dfe_dse_state_check()
168 val = readl(cryp->base + DFE_THR_STAT); in mtk_dfe_dse_state_check()
170 val = readl(cryp->base + DSE_THR_STAT); in mtk_dfe_dse_state_check()
177 writel(0, cryp->base + DFE_THR_CTRL); in mtk_dfe_dse_state_check()
178 writel(0, cryp->base + DSE_THR_CTRL); in mtk_dfe_dse_state_check()
180 return -EBUSY; in mtk_dfe_dse_state_check()
189 writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DFE_THR_CTRL); in mtk_dfe_dse_reset()
190 writel(0, cryp->base + DFE_PRIO_0); in mtk_dfe_dse_reset()
191 writel(0, cryp->base + DFE_PRIO_1); in mtk_dfe_dse_reset()
192 writel(0, cryp->base + DFE_PRIO_2); in mtk_dfe_dse_reset()
193 writel(0, cryp->base + DFE_PRIO_3); in mtk_dfe_dse_reset()
195 writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DSE_THR_CTRL); in mtk_dfe_dse_reset()
196 writel(0, cryp->base + DSE_PRIO_0); in mtk_dfe_dse_reset()
197 writel(0, cryp->base + DSE_PRIO_1); in mtk_dfe_dse_reset()
198 writel(0, cryp->base + DSE_PRIO_2); in mtk_dfe_dse_reset()
199 writel(0, cryp->base + DSE_PRIO_3); in mtk_dfe_dse_reset()
209 ((1 << MTK_CMD_FIFO_SIZE(cap->hia_opt)) / MTK_DESC_SZ) - 1; in mtk_cmd_desc_ring_setup()
212 writel(0, cryp->base + CDR_CFG(i)); in mtk_cmd_desc_ring_setup()
215 writel(MTK_CNT_RST, cryp->base + CDR_PREP_COUNT(i)); in mtk_cmd_desc_ring_setup()
216 writel(MTK_CNT_RST, cryp->base + CDR_PROC_COUNT(i)); in mtk_cmd_desc_ring_setup()
218 writel(0, cryp->base + CDR_PREP_PNTR(i)); in mtk_cmd_desc_ring_setup()
219 writel(0, cryp->base + CDR_PROC_PNTR(i)); in mtk_cmd_desc_ring_setup()
220 writel(0, cryp->base + CDR_DMA_CFG(i)); in mtk_cmd_desc_ring_setup()
223 writel(0, cryp->base + CDR_BASE_ADDR_HI(i)); in mtk_cmd_desc_ring_setup()
224 writel(cryp->ring[i]->cmd_dma, cryp->base + CDR_BASE_ADDR_LO(i)); in mtk_cmd_desc_ring_setup()
226 writel(MTK_DESC_RING_SZ, cryp->base + CDR_RING_SIZE(i)); in mtk_cmd_desc_ring_setup()
229 writel(MTK_CDR_STAT_CLR, cryp->base + CDR_STAT(i)); in mtk_cmd_desc_ring_setup()
238 cryp->base + CDR_DESC_SIZE(i)); in mtk_cmd_desc_ring_setup()
242 cryp->base + CDR_CFG(i)); in mtk_cmd_desc_ring_setup()
249 u32 count = ((1 << MTK_RES_FIFO_SIZE(cap->hia_opt)) / rndup) - 1; in mtk_res_desc_ring_setup()
252 writel(0, cryp->base + RDR_CFG(i)); in mtk_res_desc_ring_setup()
255 writel(MTK_CNT_RST, cryp->base + RDR_PREP_COUNT(i)); in mtk_res_desc_ring_setup()
256 writel(MTK_CNT_RST, cryp->base + RDR_PROC_COUNT(i)); in mtk_res_desc_ring_setup()
258 writel(0, cryp->base + RDR_PREP_PNTR(i)); in mtk_res_desc_ring_setup()
259 writel(0, cryp->base + RDR_PROC_PNTR(i)); in mtk_res_desc_ring_setup()
260 writel(0, cryp->base + RDR_DMA_CFG(i)); in mtk_res_desc_ring_setup()
263 writel(0, cryp->base + RDR_BASE_ADDR_HI(i)); in mtk_res_desc_ring_setup()
264 writel(cryp->ring[i]->res_dma, cryp->base + RDR_BASE_ADDR_LO(i)); in mtk_res_desc_ring_setup()
266 writel(MTK_DESC_RING_SZ, cryp->base + RDR_RING_SIZE(i)); in mtk_res_desc_ring_setup()
267 writel(MTK_RDR_STAT_CLR, cryp->base + RDR_STAT(i)); in mtk_res_desc_ring_setup()
270 * RDR manager generates update interrupts on a per-completed-packet, in mtk_res_desc_ring_setup()
275 cryp->base + RDR_THRESH(i)); in mtk_res_desc_ring_setup()
278 * Configure a threshold and time-out value for the processed in mtk_res_desc_ring_setup()
283 cryp->base + RDR_DESC_SIZE(i)); in mtk_res_desc_ring_setup()
286 * Configure HIA fetch size and fetch threshold that are used to in mtk_res_desc_ring_setup()
287 * fetch blocks of multiple descriptors. in mtk_res_desc_ring_setup()
292 cryp->base + RDR_CFG(i)); in mtk_res_desc_ring_setup()
301 cap.hia_ver = readl(cryp->base + HIA_VERSION); in mtk_packet_engine_setup()
302 cap.hia_opt = readl(cryp->base + HIA_OPTIONS); in mtk_packet_engine_setup()
303 cap.hw_opt = readl(cryp->base + EIP97_OPTIONS); in mtk_packet_engine_setup()
306 return -EINVAL; in mtk_packet_engine_setup()
309 writel(0, cryp->base + EIP97_MST_CTRL); in mtk_packet_engine_setup()
312 val = readl(cryp->base + HIA_MST_CTRL); in mtk_packet_engine_setup()
315 writel(val, cryp->base + HIA_MST_CTRL); in mtk_packet_engine_setup()
319 dev_err(cryp->dev, "Failed to reset DFE and DSE.\n"); in mtk_packet_engine_setup()
334 cryp->base + PE_TOKEN_CTRL_STAT); in mtk_packet_engine_setup()
337 writel(MTK_AIC_G_CLR, cryp->base + AIC_G_ACK); in mtk_packet_engine_setup()
344 cryp->base + PE_INTERRUPT_CTRL_STAT); in mtk_packet_engine_setup()
354 val = readl(cryp->base + AIC_G_VERSION); in mtk_aic_cap_check()
356 val = readl(cryp->base + AIC_VERSION(hw)); in mtk_aic_cap_check()
360 return -ENXIO; in mtk_aic_cap_check()
363 val = readl(cryp->base + AIC_G_OPTIONS); in mtk_aic_cap_check()
365 val = readl(cryp->base + AIC_OPTIONS(hw)); in mtk_aic_cap_check()
369 return -ENXIO; in mtk_aic_cap_check()
384 writel(0, cryp->base + AIC_G_ENABLE_CTRL); in mtk_aic_init()
385 writel(0, cryp->base + AIC_G_POL_CTRL); in mtk_aic_init()
386 writel(0, cryp->base + AIC_G_TYPE_CTRL); in mtk_aic_init()
387 writel(0, cryp->base + AIC_G_ENABLE_SET); in mtk_aic_init()
389 writel(0, cryp->base + AIC_ENABLE_CTRL(hw)); in mtk_aic_init()
390 writel(0, cryp->base + AIC_POL_CTRL(hw)); in mtk_aic_init()
391 writel(0, cryp->base + AIC_TYPE_CTRL(hw)); in mtk_aic_init()
392 writel(0, cryp->base + AIC_ENABLE_SET(hw)); in mtk_aic_init()
406 dev_err(cryp->dev, "Failed to initialize AIC.\n"); in mtk_accelerator_init()
414 dev_err(cryp->dev, "Failed to configure packet engine.\n"); in mtk_accelerator_init()
426 dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ, in mtk_desc_dma_free()
427 cryp->ring[i]->res_base, in mtk_desc_dma_free()
428 cryp->ring[i]->res_dma); in mtk_desc_dma_free()
429 dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ, in mtk_desc_dma_free()
430 cryp->ring[i]->cmd_base, in mtk_desc_dma_free()
431 cryp->ring[i]->cmd_dma); in mtk_desc_dma_free()
432 kfree(cryp->ring[i]); in mtk_desc_dma_free()
438 struct mtk_ring **ring = cryp->ring; in mtk_desc_ring_alloc()
446 ring[i]->cmd_base = dma_alloc_coherent(cryp->dev, in mtk_desc_ring_alloc()
448 &ring[i]->cmd_dma, in mtk_desc_ring_alloc()
450 if (!ring[i]->cmd_base) in mtk_desc_ring_alloc()
453 ring[i]->res_base = dma_alloc_coherent(cryp->dev, in mtk_desc_ring_alloc()
455 &ring[i]->res_dma, in mtk_desc_ring_alloc()
457 if (!ring[i]->res_base) in mtk_desc_ring_alloc()
460 ring[i]->cmd_next = ring[i]->cmd_base; in mtk_desc_ring_alloc()
461 ring[i]->res_next = ring[i]->res_base; in mtk_desc_ring_alloc()
467 dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ, in mtk_desc_ring_alloc()
468 ring[i]->res_base, ring[i]->res_dma); in mtk_desc_ring_alloc()
469 dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ, in mtk_desc_ring_alloc()
470 ring[i]->cmd_base, ring[i]->cmd_dma); in mtk_desc_ring_alloc()
472 } while (i--); in mtk_desc_ring_alloc()
473 return -ENOMEM; in mtk_desc_ring_alloc()
481 cryp = devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL); in mtk_crypto_probe()
483 return -ENOMEM; in mtk_crypto_probe()
485 cryp->base = devm_platform_ioremap_resource(pdev, 0); in mtk_crypto_probe()
486 if (IS_ERR(cryp->base)) in mtk_crypto_probe()
487 return PTR_ERR(cryp->base); in mtk_crypto_probe()
490 cryp->irq[i] = platform_get_irq(pdev, i); in mtk_crypto_probe()
491 if (cryp->irq[i] < 0) in mtk_crypto_probe()
492 return cryp->irq[i]; in mtk_crypto_probe()
495 cryp->clk_cryp = devm_clk_get(&pdev->dev, "cryp"); in mtk_crypto_probe()
496 if (IS_ERR(cryp->clk_cryp)) in mtk_crypto_probe()
497 return -EPROBE_DEFER; in mtk_crypto_probe()
499 cryp->dev = &pdev->dev; in mtk_crypto_probe()
500 pm_runtime_enable(cryp->dev); in mtk_crypto_probe()
501 pm_runtime_get_sync(cryp->dev); in mtk_crypto_probe()
503 err = clk_prepare_enable(cryp->clk_cryp); in mtk_crypto_probe()
510 dev_err(cryp->dev, "Unable to allocate descriptor rings.\n"); in mtk_crypto_probe()
517 dev_err(cryp->dev, "Failed to initialize cryptographic engine.\n"); in mtk_crypto_probe()
523 dev_err(cryp->dev, "Unable to register cipher algorithm.\n"); in mtk_crypto_probe()
529 dev_err(cryp->dev, "Unable to register hash algorithm.\n"); in mtk_crypto_probe()
543 clk_disable_unprepare(cryp->clk_cryp); in mtk_crypto_probe()
545 pm_runtime_put_sync(cryp->dev); in mtk_crypto_probe()
546 pm_runtime_disable(cryp->dev); in mtk_crypto_probe()
559 clk_disable_unprepare(cryp->clk_cryp); in mtk_crypto_remove()
561 pm_runtime_put_sync(cryp->dev); in mtk_crypto_remove()
562 pm_runtime_disable(cryp->dev); in mtk_crypto_remove()
569 { .compatible = "mediatek,eip97-crypto" },
578 .name = "mtk-crypto",