Lines Matching +full:aips +full:- +full:bus
1 // SPDX-License-Identifier: GPL-2.0+
3 // drivers/dma/imx-sdma.c
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
26 #include <linux/dma-mapping.h>
38 #include <linux/platform_data/dma-imx-sdma.h>
39 #include <linux/platform_data/dma-imx.h>
42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
45 #include "virt-dma.h"
129 * 0-7 Lower WML Lower watermark level
137 * 0: Source on AIPS
139 * 0: Destination on AIPS
140 * 13-15 --------- MUST BE 0
141 * 16-23 Higher WML HWML
142 * 24-27 N Total number of samples after
153 * 30 --------- MUST BE 0
185 * Mode/Count of data node descriptors - IPCv2
204 * struct sdma_channel_control - Channel control Block
218 * struct sdma_state_registers - SDMA context for a channel
247 * struct sdma_context_data - sdma context specific to a channel
305 * struct sdma_desc - descriptor structor for one transfer
312 * @chn_real_count: the real count updated from bd->mode.count
331 * struct sdma_channel - housekeeping for a SDMA channel
396 * struct sdma_firmware_header - Layout of the firmware image
570 .name = "imx25-sdma",
573 .name = "imx31-sdma",
576 .name = "imx35-sdma",
579 .name = "imx51-sdma",
582 .name = "imx53-sdma",
585 .name = "imx6q-sdma",
588 .name = "imx7d-sdma",
591 .name = "imx8mq-sdma",
600 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
601 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
602 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
603 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
604 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
605 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
606 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
607 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
613 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
619 u32 chnenbl0 = sdma->drvdata->chnenbl0; in chnenbl_ofs()
626 struct sdma_engine *sdma = sdmac->sdma; in sdma_config_ownership()
627 int channel = sdmac->channel; in sdma_config_ownership()
631 return -EINVAL; in sdma_config_ownership()
633 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
634 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
635 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
652 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
653 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
654 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
661 writel(BIT(channel), sdma->regs + SDMA_H_START); in sdma_enable_channel()
665 * sdma_run_channel0 - run a channel and wait till it's done
674 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, in sdma_run_channel0()
677 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); in sdma_run_channel0()
680 reg = readl(sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
683 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
692 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_script()
698 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); in sdma_load_script()
700 return -ENOMEM; in sdma_load_script()
703 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_script()
705 bd0->mode.command = C0_SETPM; in sdma_load_script()
706 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; in sdma_load_script()
707 bd0->mode.count = size / 2; in sdma_load_script()
708 bd0->buffer_addr = buf_phys; in sdma_load_script()
709 bd0->ext_buffer_addr = address; in sdma_load_script()
715 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_script()
717 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); in sdma_load_script()
724 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_enable()
725 int channel = sdmac->channel; in sdma_event_enable()
729 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_enable()
731 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_enable()
736 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_disable()
737 int channel = sdmac->channel; in sdma_event_disable()
741 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_disable()
743 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_disable()
753 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc); in sdma_start_desc()
755 struct sdma_engine *sdma = sdmac->sdma; in sdma_start_desc()
756 int channel = sdmac->channel; in sdma_start_desc()
759 sdmac->desc = NULL; in sdma_start_desc()
762 sdmac->desc = desc = to_sdma_desc(&vd->tx); in sdma_start_desc()
764 list_del(&vd->node); in sdma_start_desc()
766 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys; in sdma_start_desc()
767 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys; in sdma_start_desc()
768 sdma_enable_channel(sdma, sdmac->channel); in sdma_start_desc()
775 enum dma_status old_status = sdmac->status; in sdma_update_channel_loop()
778 * loop mode. Iterate over descriptors, re-setup them and in sdma_update_channel_loop()
781 while (sdmac->desc) { in sdma_update_channel_loop()
782 struct sdma_desc *desc = sdmac->desc; in sdma_update_channel_loop()
784 bd = &desc->bd[desc->buf_tail]; in sdma_update_channel_loop()
786 if (bd->mode.status & BD_DONE) in sdma_update_channel_loop()
789 if (bd->mode.status & BD_RROR) { in sdma_update_channel_loop()
790 bd->mode.status &= ~BD_RROR; in sdma_update_channel_loop()
791 sdmac->status = DMA_ERROR; in sdma_update_channel_loop()
792 error = -EIO; in sdma_update_channel_loop()
796 * We use bd->mode.count to calculate the residue, since contains in sdma_update_channel_loop()
800 desc->chn_real_count = bd->mode.count; in sdma_update_channel_loop()
801 bd->mode.status |= BD_DONE; in sdma_update_channel_loop()
802 bd->mode.count = desc->period_len; in sdma_update_channel_loop()
803 desc->buf_ptail = desc->buf_tail; in sdma_update_channel_loop()
804 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd; in sdma_update_channel_loop()
812 spin_unlock(&sdmac->vc.lock); in sdma_update_channel_loop()
813 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL); in sdma_update_channel_loop()
814 spin_lock(&sdmac->vc.lock); in sdma_update_channel_loop()
817 sdmac->status = old_status; in sdma_update_channel_loop()
827 sdmac->desc->chn_real_count = 0; in mxc_sdma_handle_channel_normal()
832 for (i = 0; i < sdmac->desc->num_bd; i++) { in mxc_sdma_handle_channel_normal()
833 bd = &sdmac->desc->bd[i]; in mxc_sdma_handle_channel_normal()
835 if (bd->mode.status & (BD_DONE | BD_RROR)) in mxc_sdma_handle_channel_normal()
836 error = -EIO; in mxc_sdma_handle_channel_normal()
837 sdmac->desc->chn_real_count += bd->mode.count; in mxc_sdma_handle_channel_normal()
841 sdmac->status = DMA_ERROR; in mxc_sdma_handle_channel_normal()
843 sdmac->status = DMA_COMPLETE; in mxc_sdma_handle_channel_normal()
851 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); in sdma_int_handler()
852 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); in sdma_int_handler()
857 int channel = fls(stat) - 1; in sdma_int_handler()
858 struct sdma_channel *sdmac = &sdma->channel[channel]; in sdma_int_handler()
861 spin_lock(&sdmac->vc.lock); in sdma_int_handler()
862 desc = sdmac->desc; in sdma_int_handler()
864 if (sdmac->flags & IMX_DMA_SG_LOOP) { in sdma_int_handler()
868 vchan_cookie_complete(&desc->vd); in sdma_int_handler()
873 spin_unlock(&sdmac->vc.lock); in sdma_int_handler()
886 struct sdma_engine *sdma = sdmac->sdma; in sdma_get_pc()
890 * two peripherals or memory-to-memory transfers in sdma_get_pc()
894 sdmac->pc_from_device = 0; in sdma_get_pc()
895 sdmac->pc_to_device = 0; in sdma_get_pc()
896 sdmac->device_to_device = 0; in sdma_get_pc()
897 sdmac->pc_to_pc = 0; in sdma_get_pc()
901 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; in sdma_get_pc()
904 emi_2_per = sdma->script_addrs->bp_2_ap_addr; in sdma_get_pc()
905 per_2_emi = sdma->script_addrs->ap_2_bp_addr; in sdma_get_pc()
908 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; in sdma_get_pc()
909 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; in sdma_get_pc()
912 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; in sdma_get_pc()
913 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
916 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; in sdma_get_pc()
917 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
920 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; in sdma_get_pc()
921 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; in sdma_get_pc()
927 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
928 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
931 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; in sdma_get_pc()
932 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; in sdma_get_pc()
940 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
941 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
944 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
945 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
946 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
949 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
950 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
951 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
954 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; in sdma_get_pc()
955 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; in sdma_get_pc()
958 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; in sdma_get_pc()
961 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; in sdma_get_pc()
962 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; in sdma_get_pc()
965 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; in sdma_get_pc()
971 sdmac->pc_from_device = per_2_emi; in sdma_get_pc()
972 sdmac->pc_to_device = emi_2_per; in sdma_get_pc()
973 sdmac->device_to_device = per_2_per; in sdma_get_pc()
974 sdmac->pc_to_pc = emi_2_emi; in sdma_get_pc()
979 struct sdma_engine *sdma = sdmac->sdma; in sdma_load_context()
980 int channel = sdmac->channel; in sdma_load_context()
982 struct sdma_context_data *context = sdma->context; in sdma_load_context()
983 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_context()
987 if (sdmac->direction == DMA_DEV_TO_MEM) in sdma_load_context()
988 load_address = sdmac->pc_from_device; in sdma_load_context()
989 else if (sdmac->direction == DMA_DEV_TO_DEV) in sdma_load_context()
990 load_address = sdmac->device_to_device; in sdma_load_context()
991 else if (sdmac->direction == DMA_MEM_TO_MEM) in sdma_load_context()
992 load_address = sdmac->pc_to_pc; in sdma_load_context()
994 load_address = sdmac->pc_to_device; in sdma_load_context()
999 dev_dbg(sdma->dev, "load_address = %d\n", load_address); in sdma_load_context()
1000 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); in sdma_load_context()
1001 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); in sdma_load_context()
1002 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); in sdma_load_context()
1003 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); in sdma_load_context()
1004 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); in sdma_load_context()
1006 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_context()
1009 context->channel_state.pc = load_address; in sdma_load_context()
1014 context->gReg[0] = sdmac->event_mask[1]; in sdma_load_context()
1015 context->gReg[1] = sdmac->event_mask[0]; in sdma_load_context()
1016 context->gReg[2] = sdmac->per_addr; in sdma_load_context()
1017 context->gReg[6] = sdmac->shp_addr; in sdma_load_context()
1018 context->gReg[7] = sdmac->watermark_level; in sdma_load_context()
1020 bd0->mode.command = C0_SETDM; in sdma_load_context()
1021 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; in sdma_load_context()
1022 bd0->mode.count = sizeof(*context) / 4; in sdma_load_context()
1023 bd0->buffer_addr = sdma->context_phys; in sdma_load_context()
1024 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; in sdma_load_context()
1027 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_context()
1040 struct sdma_engine *sdma = sdmac->sdma; in sdma_disable_channel()
1041 int channel = sdmac->channel; in sdma_disable_channel()
1043 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); in sdma_disable_channel()
1044 sdmac->status = DMA_ERROR; in sdma_disable_channel()
1063 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_channel_terminate_work()
1064 vchan_get_all_descriptors(&sdmac->vc, &head); in sdma_channel_terminate_work()
1065 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_channel_terminate_work()
1066 vchan_dma_desc_free_list(&sdmac->vc, &head); in sdma_channel_terminate_work()
1074 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_terminate_all()
1078 if (sdmac->desc) { in sdma_terminate_all()
1079 vchan_terminate_vdesc(&sdmac->desc->vd); in sdma_terminate_all()
1080 sdmac->desc = NULL; in sdma_terminate_all()
1081 schedule_work(&sdmac->terminate_worker); in sdma_terminate_all()
1084 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_terminate_all()
1093 vchan_synchronize(&sdmac->vc); in sdma_channel_synchronize()
1095 flush_work(&sdmac->terminate_worker); in sdma_channel_synchronize()
1100 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_watermarklevel_for_p2p()
1102 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML; in sdma_set_watermarklevel_for_p2p()
1103 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16; in sdma_set_watermarklevel_for_p2p()
1105 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]); in sdma_set_watermarklevel_for_p2p()
1106 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]); in sdma_set_watermarklevel_for_p2p()
1108 if (sdmac->event_id0 > 31) in sdma_set_watermarklevel_for_p2p()
1109 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE; in sdma_set_watermarklevel_for_p2p()
1111 if (sdmac->event_id1 > 31) in sdma_set_watermarklevel_for_p2p()
1112 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE; in sdma_set_watermarklevel_for_p2p()
1120 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML | in sdma_set_watermarklevel_for_p2p()
1122 sdmac->watermark_level |= hwml; in sdma_set_watermarklevel_for_p2p()
1123 sdmac->watermark_level |= lwml << 16; in sdma_set_watermarklevel_for_p2p()
1124 swap(sdmac->event_mask[0], sdmac->event_mask[1]); in sdma_set_watermarklevel_for_p2p()
1127 if (sdmac->per_address2 >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1128 sdmac->per_address2 <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1129 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP; in sdma_set_watermarklevel_for_p2p()
1131 if (sdmac->per_address >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1132 sdmac->per_address <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1133 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; in sdma_set_watermarklevel_for_p2p()
1135 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; in sdma_set_watermarklevel_for_p2p()
1144 sdmac->event_mask[0] = 0; in sdma_config_channel()
1145 sdmac->event_mask[1] = 0; in sdma_config_channel()
1146 sdmac->shp_addr = 0; in sdma_config_channel()
1147 sdmac->per_addr = 0; in sdma_config_channel()
1149 switch (sdmac->peripheral_type) { in sdma_config_channel()
1161 sdma_get_pc(sdmac, sdmac->peripheral_type); in sdma_config_channel()
1163 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && in sdma_config_channel()
1164 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { in sdma_config_channel()
1166 if (sdmac->event_id1) { in sdma_config_channel()
1167 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || in sdma_config_channel()
1168 sdmac->peripheral_type == IMX_DMATYPE_ASRC) in sdma_config_channel()
1171 __set_bit(sdmac->event_id0, sdmac->event_mask); in sdma_config_channel()
1174 sdmac->shp_addr = sdmac->per_address; in sdma_config_channel()
1175 sdmac->per_addr = sdmac->per_address2; in sdma_config_channel()
1177 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ in sdma_config_channel()
1186 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_channel_priority()
1187 int channel = sdmac->channel; in sdma_set_channel_priority()
1191 return -EINVAL; in sdma_set_channel_priority()
1194 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); in sdma_set_channel_priority()
1201 int ret = -EBUSY; in sdma_request_channel0()
1203 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys, in sdma_request_channel0()
1205 if (!sdma->bd0) { in sdma_request_channel0()
1206 ret = -ENOMEM; in sdma_request_channel0()
1210 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1211 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1213 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); in sdma_request_channel0()
1223 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); in sdma_alloc_bd()
1226 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size, in sdma_alloc_bd()
1227 &desc->bd_phys, GFP_NOWAIT); in sdma_alloc_bd()
1228 if (!desc->bd) { in sdma_alloc_bd()
1229 ret = -ENOMEM; in sdma_alloc_bd()
1238 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); in sdma_free_bd()
1240 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, in sdma_free_bd()
1241 desc->bd_phys); in sdma_free_bd()
1255 struct imx_dma_data *data = chan->private; in sdma_alloc_chan_resources()
1260 * MEMCPY may never setup chan->private by filter function such as in sdma_alloc_chan_resources()
1262 * Please note in any other slave case, you have to setup chan->private in sdma_alloc_chan_resources()
1269 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n"); in sdma_alloc_chan_resources()
1279 switch (data->priority) { in sdma_alloc_chan_resources()
1292 sdmac->peripheral_type = data->peripheral_type; in sdma_alloc_chan_resources()
1293 sdmac->event_id0 = data->dma_request; in sdma_alloc_chan_resources()
1294 sdmac->event_id1 = data->dma_request2; in sdma_alloc_chan_resources()
1296 ret = clk_enable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1299 ret = clk_enable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1310 clk_disable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1312 clk_disable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1319 struct sdma_engine *sdma = sdmac->sdma; in sdma_free_chan_resources()
1325 sdma_event_disable(sdmac, sdmac->event_id0); in sdma_free_chan_resources()
1326 if (sdmac->event_id1) in sdma_free_chan_resources()
1327 sdma_event_disable(sdmac, sdmac->event_id1); in sdma_free_chan_resources()
1329 sdmac->event_id0 = 0; in sdma_free_chan_resources()
1330 sdmac->event_id1 = 0; in sdma_free_chan_resources()
1334 clk_disable(sdma->clk_ipg); in sdma_free_chan_resources()
1335 clk_disable(sdma->clk_ahb); in sdma_free_chan_resources()
1347 sdmac->status = DMA_IN_PROGRESS; in sdma_transfer_init()
1348 sdmac->direction = direction; in sdma_transfer_init()
1349 sdmac->flags = 0; in sdma_transfer_init()
1351 desc->chn_count = 0; in sdma_transfer_init()
1352 desc->chn_real_count = 0; in sdma_transfer_init()
1353 desc->buf_tail = 0; in sdma_transfer_init()
1354 desc->buf_ptail = 0; in sdma_transfer_init()
1355 desc->sdmac = sdmac; in sdma_transfer_init()
1356 desc->num_bd = bds; in sdma_transfer_init()
1381 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_memcpy()
1382 int channel = sdmac->channel; in sdma_prep_memcpy()
1391 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", in sdma_prep_memcpy()
1401 bd = &desc->bd[i]; in sdma_prep_memcpy()
1402 bd->buffer_addr = dma_src; in sdma_prep_memcpy()
1403 bd->ext_buffer_addr = dma_dst; in sdma_prep_memcpy()
1404 bd->mode.count = count; in sdma_prep_memcpy()
1405 desc->chn_count += count; in sdma_prep_memcpy()
1406 bd->mode.command = 0; in sdma_prep_memcpy()
1410 len -= count; in sdma_prep_memcpy()
1421 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n", in sdma_prep_memcpy()
1422 i, count, bd->buffer_addr, in sdma_prep_memcpy()
1426 bd->mode.status = param; in sdma_prep_memcpy()
1429 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_memcpy()
1438 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_slave_sg()
1440 int channel = sdmac->channel; in sdma_prep_slave_sg()
1444 sdma_config_write(chan, &sdmac->slave_config, direction); in sdma_prep_slave_sg()
1450 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", in sdma_prep_slave_sg()
1454 struct sdma_buffer_descriptor *bd = &desc->bd[i]; in sdma_prep_slave_sg()
1457 bd->buffer_addr = sg->dma_address; in sdma_prep_slave_sg()
1462 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", in sdma_prep_slave_sg()
1467 bd->mode.count = count; in sdma_prep_slave_sg()
1468 desc->chn_count += count; in sdma_prep_slave_sg()
1470 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_slave_sg()
1473 switch (sdmac->word_size) { in sdma_prep_slave_sg()
1475 bd->mode.command = 0; in sdma_prep_slave_sg()
1476 if (count & 3 || sg->dma_address & 3) in sdma_prep_slave_sg()
1480 bd->mode.command = 2; in sdma_prep_slave_sg()
1481 if (count & 1 || sg->dma_address & 1) in sdma_prep_slave_sg()
1485 bd->mode.command = 1; in sdma_prep_slave_sg()
1499 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", in sdma_prep_slave_sg()
1500 i, count, (u64)sg->dma_address, in sdma_prep_slave_sg()
1504 bd->mode.status = param; in sdma_prep_slave_sg()
1507 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_slave_sg()
1512 sdmac->status = DMA_ERROR; in sdma_prep_slave_sg()
1522 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_dma_cyclic()
1524 int channel = sdmac->channel; in sdma_prep_dma_cyclic()
1528 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); in sdma_prep_dma_cyclic()
1530 sdma_config_write(chan, &sdmac->slave_config, direction); in sdma_prep_dma_cyclic()
1536 desc->period_len = period_len; in sdma_prep_dma_cyclic()
1538 sdmac->flags |= IMX_DMA_SG_LOOP; in sdma_prep_dma_cyclic()
1541 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", in sdma_prep_dma_cyclic()
1547 struct sdma_buffer_descriptor *bd = &desc->bd[i]; in sdma_prep_dma_cyclic()
1550 bd->buffer_addr = dma_addr; in sdma_prep_dma_cyclic()
1552 bd->mode.count = period_len; in sdma_prep_dma_cyclic()
1554 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_dma_cyclic()
1556 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_dma_cyclic()
1557 bd->mode.command = 0; in sdma_prep_dma_cyclic()
1559 bd->mode.command = sdmac->word_size; in sdma_prep_dma_cyclic()
1565 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n", in sdma_prep_dma_cyclic()
1570 bd->mode.status = param; in sdma_prep_dma_cyclic()
1578 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_dma_cyclic()
1583 sdmac->status = DMA_ERROR; in sdma_prep_dma_cyclic()
1594 sdmac->per_address = dmaengine_cfg->src_addr; in sdma_config_write()
1595 sdmac->watermark_level = dmaengine_cfg->src_maxburst * in sdma_config_write()
1596 dmaengine_cfg->src_addr_width; in sdma_config_write()
1597 sdmac->word_size = dmaengine_cfg->src_addr_width; in sdma_config_write()
1599 sdmac->per_address2 = dmaengine_cfg->src_addr; in sdma_config_write()
1600 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1601 sdmac->watermark_level = dmaengine_cfg->src_maxburst & in sdma_config_write()
1603 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & in sdma_config_write()
1605 sdmac->word_size = dmaengine_cfg->dst_addr_width; in sdma_config_write()
1607 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1608 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * in sdma_config_write()
1609 dmaengine_cfg->dst_addr_width; in sdma_config_write()
1610 sdmac->word_size = dmaengine_cfg->dst_addr_width; in sdma_config_write()
1612 sdmac->direction = direction; in sdma_config_write()
1621 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); in sdma_config()
1624 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1625 return -EINVAL; in sdma_config()
1626 sdma_event_enable(sdmac, sdmac->event_id0); in sdma_config()
1628 if (sdmac->event_id1) { in sdma_config()
1629 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1630 return -EINVAL; in sdma_config()
1631 sdma_event_enable(sdmac, sdmac->event_id1); in sdma_config()
1652 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_tx_status()
1654 vd = vchan_find_desc(&sdmac->vc, cookie); in sdma_tx_status()
1656 desc = to_sdma_desc(&vd->tx); in sdma_tx_status()
1657 else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) in sdma_tx_status()
1658 desc = sdmac->desc; in sdma_tx_status()
1661 if (sdmac->flags & IMX_DMA_SG_LOOP) in sdma_tx_status()
1662 residue = (desc->num_bd - desc->buf_ptail) * in sdma_tx_status()
1663 desc->period_len - desc->chn_real_count; in sdma_tx_status()
1665 residue = desc->chn_count - desc->chn_real_count; in sdma_tx_status()
1670 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_tx_status()
1672 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, in sdma_tx_status()
1675 return sdmac->status; in sdma_tx_status()
1683 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_issue_pending()
1684 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc) in sdma_issue_pending()
1686 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_issue_pending()
1698 s32 *saddr_arr = (u32 *)sdma->script_addrs; in sdma_add_scripts()
1702 if (!sdma->script_number) in sdma_add_scripts()
1703 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_add_scripts()
1705 if (sdma->script_number > sizeof(struct sdma_script_start_addrs) in sdma_add_scripts()
1707 dev_err(sdma->dev, in sdma_add_scripts()
1709 sdma->script_number); in sdma_add_scripts()
1713 for (i = 0; i < sdma->script_number; i++) in sdma_add_scripts()
1726 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); in sdma_load_firmware()
1731 if (fw->size < sizeof(*header)) in sdma_load_firmware()
1734 header = (struct sdma_firmware_header *)fw->data; in sdma_load_firmware()
1736 if (header->magic != SDMA_FIRMWARE_MAGIC) in sdma_load_firmware()
1738 if (header->ram_code_start + header->ram_code_size > fw->size) in sdma_load_firmware()
1740 switch (header->version_major) { in sdma_load_firmware()
1742 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_load_firmware()
1745 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; in sdma_load_firmware()
1748 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; in sdma_load_firmware()
1751 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; in sdma_load_firmware()
1754 dev_err(sdma->dev, "unknown firmware version\n"); in sdma_load_firmware()
1758 addr = (void *)header + header->script_addrs_start; in sdma_load_firmware()
1759 ram_code = (void *)header + header->ram_code_start; in sdma_load_firmware()
1761 clk_enable(sdma->clk_ipg); in sdma_load_firmware()
1762 clk_enable(sdma->clk_ahb); in sdma_load_firmware()
1765 header->ram_code_size, in sdma_load_firmware()
1766 addr->ram_code_start_addr); in sdma_load_firmware()
1767 clk_disable(sdma->clk_ipg); in sdma_load_firmware()
1768 clk_disable(sdma->clk_ahb); in sdma_load_firmware()
1772 dev_info(sdma->dev, "loaded firmware %d.%d\n", in sdma_load_firmware()
1773 header->version_major, in sdma_load_firmware()
1774 header->version_minor); in sdma_load_firmware()
1784 struct device_node *np = sdma->dev->of_node; in sdma_event_remap()
1788 char propname[] = "fsl,sdma-event-remap"; in sdma_event_remap()
1796 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; in sdma_event_remap()
1798 dev_dbg(sdma->dev, "no event needs to be remapped\n"); in sdma_event_remap()
1801 dev_err(sdma->dev, "the property %s must modulo %d\n", in sdma_event_remap()
1803 ret = -EINVAL; in sdma_event_remap()
1809 dev_err(sdma->dev, "failed to get gpr regmap\n"); in sdma_event_remap()
1817 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
1824 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
1831 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
1852 FW_ACTION_HOTPLUG, fw_name, sdma->dev, in sdma_get_firmware()
1863 ret = clk_enable(sdma->clk_ipg); in sdma_init()
1866 ret = clk_enable(sdma->clk_ahb); in sdma_init()
1870 if (sdma->drvdata->check_ratio && in sdma_init()
1871 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) in sdma_init()
1872 sdma->clk_ratio = 1; in sdma_init()
1875 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); in sdma_init()
1877 sdma->channel_control = dma_alloc_coherent(sdma->dev, in sdma_init()
1882 if (!sdma->channel_control) { in sdma_init()
1883 ret = -ENOMEM; in sdma_init()
1887 sdma->context = (void *)sdma->channel_control + in sdma_init()
1889 sdma->context_phys = ccb_phys + in sdma_init()
1893 for (i = 0; i < sdma->drvdata->num_events; i++) in sdma_init()
1894 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); in sdma_init()
1898 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); in sdma_init()
1904 sdma_config_ownership(&sdma->channel[0], false, true, false); in sdma_init()
1907 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); in sdma_init()
1910 if (sdma->clk_ratio) in sdma_init()
1911 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); in sdma_init()
1913 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); in sdma_init()
1915 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); in sdma_init()
1918 sdma_set_channel_priority(&sdma->channel[0], 7); in sdma_init()
1920 clk_disable(sdma->clk_ipg); in sdma_init()
1921 clk_disable(sdma->clk_ahb); in sdma_init()
1926 clk_disable(sdma->clk_ahb); in sdma_init()
1928 clk_disable(sdma->clk_ipg); in sdma_init()
1929 dev_err(sdma->dev, "initialisation failed with %d\n", ret); in sdma_init()
1941 sdmac->data = *data; in sdma_filter_fn()
1942 chan->private = &sdmac->data; in sdma_filter_fn()
1950 struct sdma_engine *sdma = ofdma->of_dma_data; in sdma_xlate()
1951 dma_cap_mask_t mask = sdma->dma_device.cap_mask; in sdma_xlate()
1954 if (dma_spec->args_count != 3) in sdma_xlate()
1957 data.dma_request = dma_spec->args[0]; in sdma_xlate()
1958 data.peripheral_type = dma_spec->args[1]; in sdma_xlate()
1959 data.priority = dma_spec->args[2]; in sdma_xlate()
1963 * chan->private will point to the imx_dma_data, and in in sdma_xlate()
1965 * be set to sdmac->event_id1. in sdma_xlate()
1970 ofdma->of_node); in sdma_xlate()
1976 of_match_device(sdma_dt_ids, &pdev->dev); in sdma_probe()
1977 struct device_node *np = pdev->dev.of_node; in sdma_probe()
1984 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev); in sdma_probe()
1991 drvdata = of_id->data; in sdma_probe()
1992 else if (pdev->id_entry) in sdma_probe()
1993 drvdata = (void *)pdev->id_entry->driver_data; in sdma_probe()
1996 dev_err(&pdev->dev, "unable to find driver data\n"); in sdma_probe()
1997 return -EINVAL; in sdma_probe()
2000 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in sdma_probe()
2004 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); in sdma_probe()
2006 return -ENOMEM; in sdma_probe()
2008 spin_lock_init(&sdma->channel_0_lock); in sdma_probe()
2010 sdma->dev = &pdev->dev; in sdma_probe()
2011 sdma->drvdata = drvdata; in sdma_probe()
2018 sdma->regs = devm_ioremap_resource(&pdev->dev, iores); in sdma_probe()
2019 if (IS_ERR(sdma->regs)) in sdma_probe()
2020 return PTR_ERR(sdma->regs); in sdma_probe()
2022 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdma_probe()
2023 if (IS_ERR(sdma->clk_ipg)) in sdma_probe()
2024 return PTR_ERR(sdma->clk_ipg); in sdma_probe()
2026 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdma_probe()
2027 if (IS_ERR(sdma->clk_ahb)) in sdma_probe()
2028 return PTR_ERR(sdma->clk_ahb); in sdma_probe()
2030 ret = clk_prepare(sdma->clk_ipg); in sdma_probe()
2034 ret = clk_prepare(sdma->clk_ahb); in sdma_probe()
2038 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma", in sdma_probe()
2043 sdma->irq = irq; in sdma_probe()
2045 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); in sdma_probe()
2046 if (!sdma->script_addrs) { in sdma_probe()
2047 ret = -ENOMEM; in sdma_probe()
2052 saddr_arr = (s32 *)sdma->script_addrs; in sdma_probe()
2053 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++) in sdma_probe()
2054 saddr_arr[i] = -EINVAL; in sdma_probe()
2056 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); in sdma_probe()
2057 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); in sdma_probe()
2058 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask); in sdma_probe()
2060 INIT_LIST_HEAD(&sdma->dma_device.channels); in sdma_probe()
2063 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_probe()
2065 sdmac->sdma = sdma; in sdma_probe()
2067 sdmac->channel = i; in sdma_probe()
2068 sdmac->vc.desc_free = sdma_desc_free; in sdma_probe()
2069 INIT_WORK(&sdmac->terminate_worker, in sdma_probe()
2077 vchan_init(&sdmac->vc, &sdma->dma_device); in sdma_probe()
2088 if (sdma->drvdata->script_addrs) in sdma_probe()
2089 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); in sdma_probe()
2090 if (pdata && pdata->script_addrs) in sdma_probe()
2091 sdma_add_scripts(sdma, pdata->script_addrs); in sdma_probe()
2093 sdma->dma_device.dev = &pdev->dev; in sdma_probe()
2095 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; in sdma_probe()
2096 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; in sdma_probe()
2097 sdma->dma_device.device_tx_status = sdma_tx_status; in sdma_probe()
2098 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; in sdma_probe()
2099 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; in sdma_probe()
2100 sdma->dma_device.device_config = sdma_config; in sdma_probe()
2101 sdma->dma_device.device_terminate_all = sdma_terminate_all; in sdma_probe()
2102 sdma->dma_device.device_synchronize = sdma_channel_synchronize; in sdma_probe()
2103 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2104 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2105 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; in sdma_probe()
2106 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in sdma_probe()
2107 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy; in sdma_probe()
2108 sdma->dma_device.device_issue_pending = sdma_issue_pending; in sdma_probe()
2109 sdma->dma_device.copy_align = 2; in sdma_probe()
2110 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT); in sdma_probe()
2114 ret = dma_async_device_register(&sdma->dma_device); in sdma_probe()
2116 dev_err(&pdev->dev, "unable to register\n"); in sdma_probe()
2123 dev_err(&pdev->dev, "failed to register controller\n"); in sdma_probe()
2127 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); in sdma_probe()
2130 sdma->spba_start_addr = spba_res.start; in sdma_probe()
2131 sdma->spba_end_addr = spba_res.end; in sdma_probe()
2143 ret = sdma_get_firmware(sdma, pdata->fw_name); in sdma_probe()
2145 dev_warn(&pdev->dev, "failed to get firmware from platform data\n"); in sdma_probe()
2152 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", in sdma_probe()
2155 dev_warn(&pdev->dev, "failed to get firmware name\n"); in sdma_probe()
2159 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); in sdma_probe()
2166 dma_async_device_unregister(&sdma->dma_device); in sdma_probe()
2168 kfree(sdma->script_addrs); in sdma_probe()
2170 clk_unprepare(sdma->clk_ahb); in sdma_probe()
2172 clk_unprepare(sdma->clk_ipg); in sdma_probe()
2181 devm_free_irq(&pdev->dev, sdma->irq, sdma); in sdma_remove()
2182 dma_async_device_unregister(&sdma->dma_device); in sdma_remove()
2183 kfree(sdma->script_addrs); in sdma_remove()
2184 clk_unprepare(sdma->clk_ahb); in sdma_remove()
2185 clk_unprepare(sdma->clk_ipg); in sdma_remove()
2188 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_remove()
2190 tasklet_kill(&sdmac->vc.task); in sdma_remove()
2191 sdma_free_chan_resources(&sdmac->vc.chan); in sdma_remove()
2200 .name = "imx-sdma",
2213 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2216 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");