Lines Matching +full:max +full:- +full:burst +full:- +full:len
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
22 #include <linux/dma/pxa-dma.h>
25 #include "virt-dma.h"
36 #define PXA_DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
38 #define PXA_DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
39 #define PXA_DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
64 #define PXA_DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
65 #define PXA_DCMD_BURST8 (1 << 16) /* 8 byte burst */
66 #define PXA_DCMD_BURST16 (2 << 16) /* 16 byte burst */
67 #define PXA_DCMD_BURST32 (3 << 16) /* 32 byte burst */
71 #define PXA_DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
74 #define PDMA_MAX_DESC_BYTES (PXA_DCMD_LENGTH & ~((1 << PDMA_ALIGNMENT) - 1))
86 size_t len; /* Number of bytes xfered */ member
115 /* protected by vc->lock */
146 readl_relaxed((phy)->base + _reg((phy)->idx))
150 _v = readl_relaxed((phy)->base + _reg((phy)->idx)); \
151 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
158 writel((val), (phy)->base + _reg((phy)->idx)); \
159 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
165 writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \
166 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
190 struct pxad_phy *phy = s->private; in requester_chan_show()
194 seq_printf(s, "DMA channel %d requester :\n", phy->idx); in requester_chan_show()
196 drcmr = readl_relaxed(phy->base + pxad_drcmr(i)); in requester_chan_show()
197 if ((drcmr & DRCMR_CHLNUM) == phy->idx) in requester_chan_show()
206 int burst = (dcmd >> 16) & 0x3; in dbg_burst_from_dcmd() local
208 return burst ? 4 << burst : 0; in dbg_burst_from_dcmd()
221 struct pxad_phy *phy = s->private; in descriptors_show()
222 int i, max_show = 20, burst, width; in descriptors_show() local
229 seq_printf(s, "DMA channel %d descriptors :\n", phy->idx); in descriptors_show()
233 dcmd = desc->dcmd; in descriptors_show()
234 burst = dbg_burst_from_dcmd(dcmd); in descriptors_show()
239 seq_printf(s, "\tDDADR = %08x\n", desc->ddadr); in descriptors_show()
240 seq_printf(s, "\tDSADR = %08x\n", desc->dsadr); in descriptors_show()
241 seq_printf(s, "\tDTADR = %08x\n", desc->dtadr); in descriptors_show()
242 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n", in descriptors_show()
247 PXA_DCMD_STR(ENDIAN), burst, width, in descriptors_show()
249 phys_desc = desc->ddadr; in descriptors_show()
252 seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n", in descriptors_show()
264 struct pxad_phy *phy = s->private; in chan_state_show()
266 int burst, width; in chan_state_show() local
273 burst = dbg_burst_from_dcmd(dcmd); in chan_state_show()
276 seq_printf(s, "DMA channel %d\n", phy->idx); in chan_state_show()
278 str_prio[(phy->idx & 0xf) / 4]); in chan_state_show()
280 _phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ? in chan_state_show()
292 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n", in chan_state_show()
297 PXA_DCMD_STR(ENDIAN), burst, width, dcmd & PXA_DCMD_LENGTH); in chan_state_show()
307 struct pxad_device *pdev = s->private; in state_show()
311 seq_printf(s, "\tChannel number: %d\n", pdev->nr_chans); in state_show()
330 dt = (void *)&pdev->phys[ch]; in pxad_dbg_alloc_chan()
344 pdev->dbgfs_chan = in pxad_init_debugfs()
345 kmalloc_array(pdev->nr_chans, sizeof(struct dentry *), in pxad_init_debugfs()
347 if (!pdev->dbgfs_chan) in pxad_init_debugfs()
350 pdev->dbgfs_root = debugfs_create_dir(dev_name(pdev->slave.dev), NULL); in pxad_init_debugfs()
352 debugfs_create_file("state", 0400, pdev->dbgfs_root, pdev, &state_fops); in pxad_init_debugfs()
354 chandir = debugfs_create_dir("channels", pdev->dbgfs_root); in pxad_init_debugfs()
356 for (i = 0; i < pdev->nr_chans; i++) in pxad_init_debugfs()
357 pdev->dbgfs_chan[i] = pxad_dbg_alloc_chan(pdev, i, chandir); in pxad_init_debugfs()
362 debugfs_remove_recursive(pdev->dbgfs_root); in pxad_cleanup_debugfs()
372 struct pxad_device *pdev = to_pxad_dev(pchan->vc.chan.device); in lookup_phy()
378 * ch 0 - 3, 16 - 19 <--> (0) in lookup_phy()
379 * ch 4 - 7, 20 - 23 <--> (1) in lookup_phy()
380 * ch 8 - 11, 24 - 27 <--> (2) in lookup_phy()
381 * ch 12 - 15, 28 - 31 <--> (3) in lookup_phy()
384 spin_lock_irqsave(&pdev->phy_lock, flags); in lookup_phy()
385 for (prio = pchan->prio; prio >= PXAD_PRIO_HIGHEST; prio--) { in lookup_phy()
386 for (i = 0; i < pdev->nr_chans; i++) { in lookup_phy()
389 phy = &pdev->phys[i]; in lookup_phy()
390 if (!phy->vchan) { in lookup_phy()
391 phy->vchan = pchan; in lookup_phy()
399 spin_unlock_irqrestore(&pdev->phy_lock, flags); in lookup_phy()
400 dev_dbg(&pchan->vc.chan.dev->device, in lookup_phy()
402 found ? found->idx : -1); in lookup_phy()
409 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); in pxad_free_phy()
413 dev_dbg(&chan->vc.chan.dev->device, in pxad_free_phy()
415 if (!chan->phy) in pxad_free_phy()
419 if (chan->drcmr <= pdev->nr_requestors) { in pxad_free_phy()
420 reg = pxad_drcmr(chan->drcmr); in pxad_free_phy()
421 writel_relaxed(0, chan->phy->base + reg); in pxad_free_phy()
424 spin_lock_irqsave(&pdev->phy_lock, flags); in pxad_free_phy()
425 chan->phy->vchan = NULL; in pxad_free_phy()
426 chan->phy = NULL; in pxad_free_phy()
427 spin_unlock_irqrestore(&pdev->phy_lock, flags); in pxad_free_phy()
433 struct pxad_phy *phy = chan->phy; in is_chan_running()
445 BUG_ON(!chan->phy); in is_running_chan_misaligned()
446 dalgn = phy_readl_relaxed(chan->phy, DALGN); in is_running_chan_misaligned()
447 return dalgn & (BIT(chan->phy->idx)); in is_running_chan_misaligned()
455 if (!phy->vchan) in phy_enable()
458 dev_dbg(&phy->vchan->vc.chan.dev->device, in phy_enable()
460 phy, phy->idx, misaligned); in phy_enable()
462 pdev = to_pxad_dev(phy->vchan->vc.chan.device); in phy_enable()
463 if (phy->vchan->drcmr <= pdev->nr_requestors) { in phy_enable()
464 reg = pxad_drcmr(phy->vchan->drcmr); in phy_enable()
465 writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg); in phy_enable()
470 dalgn |= BIT(phy->idx); in phy_enable()
472 dalgn &= ~BIT(phy->idx); in phy_enable()
487 dev_dbg(&phy->vchan->vc.chan.dev->device, in phy_disable()
488 "%s(): phy=%p(%d)\n", __func__, phy, phy->idx); in phy_disable()
495 dev_dbg(&chan->vc.chan.dev->device, in pxad_launch_chan()
497 if (!chan->phy) { in pxad_launch_chan()
498 chan->phy = lookup_phy(chan); in pxad_launch_chan()
499 if (!chan->phy) { in pxad_launch_chan()
500 dev_dbg(&chan->vc.chan.dev->device, in pxad_launch_chan()
505 chan->bus_error = 0; in pxad_launch_chan()
511 phy_writel(chan->phy, desc->first, DDADR); in pxad_launch_chan()
512 phy_enable(chan->phy, chan->misaligned); in pxad_launch_chan()
513 wake_up(&chan->wq_state); in pxad_launch_chan()
520 sw_desc->hw_desc[sw_desc->nb_desc - 1]; in set_updater_desc()
521 dma_addr_t dma = sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr; in set_updater_desc()
523 updater->ddadr = DDADR_STOP; in set_updater_desc()
524 updater->dsadr = dma; in set_updater_desc()
525 updater->dtadr = dma + 8; in set_updater_desc()
526 updater->dcmd = PXA_DCMD_WIDTH4 | PXA_DCMD_BURST32 | in set_updater_desc()
529 updater->dcmd |= PXA_DCMD_ENDIRQEN; in set_updater_desc()
530 if (sw_desc->cyclic) in set_updater_desc()
531 sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr = sw_desc->first; in set_updater_desc()
538 sw_desc->hw_desc[sw_desc->nb_desc - 1]; in is_desc_completed()
540 return updater->dtadr != (updater->dsadr + 8); in is_desc_completed()
550 dma_to_chain = desc2->first; in pxad_desc_chain()
551 desc1->hw_desc[desc1->nb_desc - 1]->ddadr = dma_to_chain; in pxad_desc_chain()
558 struct pxad_chan *chan = to_pxad_chan(&vc->chan); in pxad_try_hotchain()
568 BUG_ON(list_empty(&vc->desc_issued)); in pxad_try_hotchain()
571 to_pxad_sw_desc(vd)->misaligned) in pxad_try_hotchain()
574 vd_last_issued = list_entry(vc->desc_issued.prev, in pxad_try_hotchain()
587 u32 dint = readl(phy->base + DINT); in clear_chan_irq()
589 if (!(dint & BIT(phy->idx))) in clear_chan_irq()
595 if ((dcsr & PXA_DCSR_BUSERR) && (phy->vchan)) in clear_chan_irq()
596 dev_warn(&phy->vchan->vc.chan.dev->device, in clear_chan_irq()
598 __func__, &phy->vchan); in clear_chan_irq()
606 struct pxad_chan *chan = phy->vchan; in pxad_chan_handler()
619 spin_lock_irqsave(&chan->vc.lock, flags); in pxad_chan_handler()
620 list_for_each_entry_safe(vd, tmp, &chan->vc.desc_issued, node) { in pxad_chan_handler()
622 dev_dbg(&chan->vc.chan.dev->device, in pxad_chan_handler()
624 __func__, vd, vd->tx.cookie, vd_completed, in pxad_chan_handler()
626 last_started = vd->tx.cookie; in pxad_chan_handler()
627 if (to_pxad_sw_desc(vd)->cyclic) { in pxad_chan_handler()
632 list_del(&vd->node); in pxad_chan_handler()
640 chan->bus_error = last_started; in pxad_chan_handler()
644 if (!chan->bus_error && dcsr & PXA_DCSR_STOPSTATE) { in pxad_chan_handler()
645 dev_dbg(&chan->vc.chan.dev->device, in pxad_chan_handler()
648 list_empty(&chan->vc.desc_submitted), in pxad_chan_handler()
649 list_empty(&chan->vc.desc_issued)); in pxad_chan_handler()
652 if (list_empty(&chan->vc.desc_issued)) { in pxad_chan_handler()
653 chan->misaligned = in pxad_chan_handler()
654 !list_empty(&chan->vc.desc_submitted); in pxad_chan_handler()
656 vd = list_first_entry(&chan->vc.desc_issued, in pxad_chan_handler()
661 spin_unlock_irqrestore(&chan->vc.lock, flags); in pxad_chan_handler()
662 wake_up(&chan->wq_state); in pxad_chan_handler()
671 u32 dint = readl(pdev->base + DINT); in pxad_int_handler()
676 dint &= (dint - 1); in pxad_int_handler()
677 phy = &pdev->phys[i]; in pxad_int_handler()
688 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); in pxad_alloc_chan_resources()
690 if (chan->desc_pool) in pxad_alloc_chan_resources()
693 chan->desc_pool = dma_pool_create(dma_chan_name(dchan), in pxad_alloc_chan_resources()
694 pdev->slave.dev, in pxad_alloc_chan_resources()
698 if (!chan->desc_pool) { in pxad_alloc_chan_resources()
699 dev_err(&chan->vc.chan.dev->device, in pxad_alloc_chan_resources()
702 return -ENOMEM; in pxad_alloc_chan_resources()
712 vchan_free_chan_resources(&chan->vc); in pxad_free_chan_resources()
713 dma_pool_destroy(chan->desc_pool); in pxad_free_chan_resources()
714 chan->desc_pool = NULL; in pxad_free_chan_resources()
716 chan->drcmr = U32_MAX; in pxad_free_chan_resources()
717 chan->prio = PXAD_PRIO_LOWEST; in pxad_free_chan_resources()
726 BUG_ON(sw_desc->nb_desc == 0); in pxad_free_desc()
727 for (i = sw_desc->nb_desc - 1; i >= 0; i--) { in pxad_free_desc()
729 dma = sw_desc->hw_desc[i - 1]->ddadr; in pxad_free_desc()
731 dma = sw_desc->first; in pxad_free_desc()
732 dma_pool_free(sw_desc->desc_pool, in pxad_free_desc()
733 sw_desc->hw_desc[i], dma); in pxad_free_desc()
735 sw_desc->nb_desc = 0; in pxad_free_desc()
751 sw_desc->desc_pool = chan->desc_pool; in pxad_alloc_desc()
754 sw_desc->hw_desc[i] = dma_pool_alloc(sw_desc->desc_pool, in pxad_alloc_desc()
756 if (!sw_desc->hw_desc[i]) { in pxad_alloc_desc()
757 dev_err(&chan->vc.chan.dev->device, in pxad_alloc_desc()
759 __func__, i, sw_desc->desc_pool); in pxad_alloc_desc()
764 sw_desc->first = dma; in pxad_alloc_desc()
766 sw_desc->hw_desc[i - 1]->ddadr = dma; in pxad_alloc_desc()
767 sw_desc->nb_desc++; in pxad_alloc_desc()
772 pxad_free_desc(&sw_desc->vd); in pxad_alloc_desc()
778 struct virt_dma_chan *vc = to_virt_chan(tx->chan); in pxad_tx_submit()
779 struct pxad_chan *chan = to_pxad_chan(&vc->chan); in pxad_tx_submit()
785 set_updater_desc(to_pxad_sw_desc(vd), tx->flags); in pxad_tx_submit()
787 spin_lock_irqsave(&vc->lock, flags); in pxad_tx_submit()
790 if (list_empty(&vc->desc_submitted) && pxad_try_hotchain(vc, vd)) { in pxad_tx_submit()
791 list_move_tail(&vd->node, &vc->desc_issued); in pxad_tx_submit()
792 dev_dbg(&chan->vc.chan.dev->device, in pxad_tx_submit()
801 if (!list_empty(&vc->desc_submitted)) { in pxad_tx_submit()
802 vd_chained = list_entry(vc->desc_submitted.prev, in pxad_tx_submit()
810 if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned) in pxad_tx_submit()
815 dev_dbg(&chan->vc.chan.dev->device, in pxad_tx_submit()
818 list_move_tail(&vd->node, &vc->desc_submitted); in pxad_tx_submit()
819 chan->misaligned |= to_pxad_sw_desc(vd)->misaligned; in pxad_tx_submit()
822 spin_unlock_irqrestore(&vc->lock, flags); in pxad_tx_submit()
832 spin_lock_irqsave(&chan->vc.lock, flags); in pxad_issue_pending()
833 if (list_empty(&chan->vc.desc_submitted)) in pxad_issue_pending()
836 vd_first = list_first_entry(&chan->vc.desc_submitted, in pxad_issue_pending()
838 dev_dbg(&chan->vc.chan.dev->device, in pxad_issue_pending()
839 "%s(): txd %p[%x]", __func__, vd_first, vd_first->tx.cookie); in pxad_issue_pending()
841 vchan_issue_pending(&chan->vc); in pxad_issue_pending()
842 if (!pxad_try_hotchain(&chan->vc, vd_first)) in pxad_issue_pending()
845 spin_unlock_irqrestore(&chan->vc.lock, flags); in pxad_issue_pending()
855 INIT_LIST_HEAD(&vd->node); in pxad_tx_prep()
857 tx->tx_submit = pxad_tx_submit; in pxad_tx_prep()
858 dev_dbg(&chan->vc.chan.dev->device, in pxad_tx_prep()
860 vc, vd, vd->tx.cookie, in pxad_tx_prep()
872 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); in pxad_get_config()
876 maxburst = chan->cfg.src_maxburst; in pxad_get_config()
877 width = chan->cfg.src_addr_width; in pxad_get_config()
878 dev_addr = chan->cfg.src_addr; in pxad_get_config()
881 if (chan->drcmr <= pdev->nr_requestors) in pxad_get_config()
885 maxburst = chan->cfg.dst_maxburst; in pxad_get_config()
886 width = chan->cfg.dst_addr_width; in pxad_get_config()
887 dev_addr = chan->cfg.dst_addr; in pxad_get_config()
890 if (chan->drcmr <= pdev->nr_requestors) in pxad_get_config()
897 dev_dbg(&chan->vc.chan.dev->device, in pxad_get_config()
919 size_t len, unsigned long flags) in pxad_prep_memcpy() argument
928 if (!dchan || !len) in pxad_prep_memcpy()
931 dev_dbg(&chan->vc.chan.dev->device, in pxad_prep_memcpy()
932 "%s(): dma_dst=0x%lx dma_src=0x%lx len=%zu flags=%lx\n", in pxad_prep_memcpy()
934 len, flags); in pxad_prep_memcpy()
937 nb_desc = DIV_ROUND_UP(len, PDMA_MAX_DESC_BYTES); in pxad_prep_memcpy()
941 sw_desc->len = len; in pxad_prep_memcpy()
945 sw_desc->misaligned = true; in pxad_prep_memcpy()
949 hw_desc = sw_desc->hw_desc[i++]; in pxad_prep_memcpy()
950 copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES); in pxad_prep_memcpy()
951 hw_desc->dcmd = dcmd | (PXA_DCMD_LENGTH & copy); in pxad_prep_memcpy()
952 hw_desc->dsadr = dma_src; in pxad_prep_memcpy()
953 hw_desc->dtadr = dma_dst; in pxad_prep_memcpy()
954 len -= copy; in pxad_prep_memcpy()
957 } while (len); in pxad_prep_memcpy()
960 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); in pxad_prep_memcpy()
970 size_t len, avail; in pxad_prep_slave_sg() local
980 dev_dbg(&chan->vc.chan.dev->device, in pxad_prep_slave_sg()
992 sw_desc->len += avail; in pxad_prep_slave_sg()
995 len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES); in pxad_prep_slave_sg()
997 sw_desc->misaligned = true; in pxad_prep_slave_sg()
999 sw_desc->hw_desc[j]->dcmd = in pxad_prep_slave_sg()
1000 dcmd | (PXA_DCMD_LENGTH & len); in pxad_prep_slave_sg()
1001 sw_desc->hw_desc[j]->dsadr = dsadr ? dsadr : dma; in pxad_prep_slave_sg()
1002 sw_desc->hw_desc[j++]->dtadr = dtadr ? dtadr : dma; in pxad_prep_slave_sg()
1004 dma += len; in pxad_prep_slave_sg()
1005 avail -= len; in pxad_prep_slave_sg()
1010 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); in pxad_prep_slave_sg()
1015 dma_addr_t buf_addr, size_t len, size_t period_len, in pxad_prep_dma_cyclic() argument
1025 if (!dchan || !len || !period_len) in pxad_prep_dma_cyclic()
1028 dev_err(&chan->vc.chan.dev->device, in pxad_prep_dma_cyclic()
1033 if (len % period_len != 0 || period_len > PDMA_MAX_DESC_BYTES || in pxad_prep_dma_cyclic()
1039 dev_dbg(&chan->vc.chan.dev->device, in pxad_prep_dma_cyclic()
1040 "%s(): buf_addr=0x%lx len=%zu period=%zu dir=%d flags=%lx\n", in pxad_prep_dma_cyclic()
1041 __func__, (unsigned long)buf_addr, len, period_len, dir, flags); in pxad_prep_dma_cyclic()
1044 nb_desc *= DIV_ROUND_UP(len, period_len); in pxad_prep_dma_cyclic()
1048 sw_desc->cyclic = true; in pxad_prep_dma_cyclic()
1049 sw_desc->len = len; in pxad_prep_dma_cyclic()
1051 phw_desc = sw_desc->hw_desc; in pxad_prep_dma_cyclic()
1054 phw_desc[0]->dsadr = dsadr ? dsadr : dma; in pxad_prep_dma_cyclic()
1055 phw_desc[0]->dtadr = dtadr ? dtadr : dma; in pxad_prep_dma_cyclic()
1056 phw_desc[0]->dcmd = dcmd; in pxad_prep_dma_cyclic()
1059 len -= period_len; in pxad_prep_dma_cyclic()
1060 } while (len); in pxad_prep_dma_cyclic()
1063 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); in pxad_prep_dma_cyclic()
1072 return -EINVAL; in pxad_config()
1074 chan->cfg = *cfg; in pxad_config()
1081 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); in pxad_terminate_all()
1087 dev_dbg(&chan->vc.chan.dev->device, in pxad_terminate_all()
1088 "%s(): vchan %p: terminate all\n", __func__, &chan->vc); in pxad_terminate_all()
1090 spin_lock_irqsave(&chan->vc.lock, flags); in pxad_terminate_all()
1091 vchan_get_all_descriptors(&chan->vc, &head); in pxad_terminate_all()
1094 dev_dbg(&chan->vc.chan.dev->device, in pxad_terminate_all()
1096 vd, vd->tx.cookie, is_desc_completed(vd)); in pxad_terminate_all()
1099 phy = chan->phy; in pxad_terminate_all()
1101 phy_disable(chan->phy); in pxad_terminate_all()
1103 chan->phy = NULL; in pxad_terminate_all()
1104 spin_lock(&pdev->phy_lock); in pxad_terminate_all()
1105 phy->vchan = NULL; in pxad_terminate_all()
1106 spin_unlock(&pdev->phy_lock); in pxad_terminate_all()
1108 spin_unlock_irqrestore(&chan->vc.lock, flags); in pxad_terminate_all()
1109 vchan_dma_desc_free_list(&chan->vc, &head); in pxad_terminate_all()
1120 u32 curr, start, len, end, residue = 0; in pxad_residue() local
1129 if (!chan->phy) in pxad_residue()
1132 spin_lock_irqsave(&chan->vc.lock, flags); in pxad_residue()
1134 vd = vchan_find_desc(&chan->vc, cookie); in pxad_residue()
1139 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR) in pxad_residue()
1140 curr = phy_readl_relaxed(chan->phy, DSADR); in pxad_residue()
1142 curr = phy_readl_relaxed(chan->phy, DTADR); in pxad_residue()
1154 for (i = 0; i < sw_desc->nb_desc - 1; i++) { in pxad_residue()
1155 hw_desc = sw_desc->hw_desc[i]; in pxad_residue()
1156 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR) in pxad_residue()
1157 start = hw_desc->dsadr; in pxad_residue()
1159 start = hw_desc->dtadr; in pxad_residue()
1160 len = hw_desc->dcmd & PXA_DCMD_LENGTH; in pxad_residue()
1161 end = start + len; in pxad_residue()
1173 residue += len; in pxad_residue()
1175 residue += end - curr; in pxad_residue()
1180 residue = sw_desc->len; in pxad_residue()
1183 spin_unlock_irqrestore(&chan->vc.lock, flags); in pxad_residue()
1184 dev_dbg(&chan->vc.chan.dev->device, in pxad_residue()
1197 if (cookie == chan->bus_error) in pxad_tx_status()
1211 wait_event(chan->wq_state, !is_chan_running(chan)); in pxad_synchronize()
1212 vchan_synchronize(&chan->vc); in pxad_synchronize()
1219 list_for_each_entry_safe(c, cn, &dmadev->channels, in pxad_free_channels()
1221 list_del(&c->vc.chan.device_node); in pxad_free_channels()
1222 tasklet_kill(&c->vc.task); in pxad_free_channels()
1231 pxad_free_channels(&pdev->slave); in pxad_remove()
1246 pdev->phys = devm_kcalloc(&op->dev, nb_phy_chans, in pxad_init_phys()
1247 sizeof(pdev->phys[0]), GFP_KERNEL); in pxad_init_phys()
1248 if (!pdev->phys) in pxad_init_phys()
1249 return -ENOMEM; in pxad_init_phys()
1256 phy = &pdev->phys[i]; in pxad_init_phys()
1257 phy->base = pdev->base; in pxad_init_phys()
1258 phy->idx = i; in pxad_init_phys()
1261 ret = devm_request_irq(&op->dev, irq, in pxad_init_phys()
1263 IRQF_SHARED, "pxa-dma", phy); in pxad_init_phys()
1265 ret = devm_request_irq(&op->dev, irq0, in pxad_init_phys()
1267 IRQF_SHARED, "pxa-dma", pdev); in pxad_init_phys()
1269 dev_err(pdev->slave.dev, in pxad_init_phys()
1280 { .compatible = "marvell,pdma-1.0", },
1288 struct pxad_device *d = ofdma->of_dma_data; in pxad_dma_xlate()
1291 chan = dma_get_any_slave_channel(&d->slave); in pxad_dma_xlate()
1295 to_pxad_chan(chan)->drcmr = dma_spec->args[0]; in pxad_dma_xlate()
1296 to_pxad_chan(chan)->prio = dma_spec->args[1]; in pxad_dma_xlate()
1310 pdev->nr_chans = nr_phy_chans; in pxad_init_dmadev()
1311 pdev->nr_requestors = nr_requestors; in pxad_init_dmadev()
1312 INIT_LIST_HEAD(&pdev->slave.channels); in pxad_init_dmadev()
1313 pdev->slave.device_alloc_chan_resources = pxad_alloc_chan_resources; in pxad_init_dmadev()
1314 pdev->slave.device_free_chan_resources = pxad_free_chan_resources; in pxad_init_dmadev()
1315 pdev->slave.device_tx_status = pxad_tx_status; in pxad_init_dmadev()
1316 pdev->slave.device_issue_pending = pxad_issue_pending; in pxad_init_dmadev()
1317 pdev->slave.device_config = pxad_config; in pxad_init_dmadev()
1318 pdev->slave.device_synchronize = pxad_synchronize; in pxad_init_dmadev()
1319 pdev->slave.device_terminate_all = pxad_terminate_all; in pxad_init_dmadev()
1321 if (op->dev.coherent_dma_mask) in pxad_init_dmadev()
1322 dma_set_mask(&op->dev, op->dev.coherent_dma_mask); in pxad_init_dmadev()
1324 dma_set_mask(&op->dev, DMA_BIT_MASK(32)); in pxad_init_dmadev()
1331 c = devm_kzalloc(&op->dev, sizeof(*c), GFP_KERNEL); in pxad_init_dmadev()
1333 return -ENOMEM; in pxad_init_dmadev()
1335 c->drcmr = U32_MAX; in pxad_init_dmadev()
1336 c->prio = PXAD_PRIO_LOWEST; in pxad_init_dmadev()
1337 c->vc.desc_free = pxad_free_desc; in pxad_init_dmadev()
1338 vchan_init(&c->vc, &pdev->slave); in pxad_init_dmadev()
1339 init_waitqueue_head(&c->wq_state); in pxad_init_dmadev()
1342 return dmaenginem_async_device_register(&pdev->slave); in pxad_init_dmadev()
1350 struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev); in pxad_probe()
1357 pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL); in pxad_probe()
1359 return -ENOMEM; in pxad_probe()
1361 spin_lock_init(&pdev->phy_lock); in pxad_probe()
1364 pdev->base = devm_ioremap_resource(&op->dev, iores); in pxad_probe()
1365 if (IS_ERR(pdev->base)) in pxad_probe()
1366 return PTR_ERR(pdev->base); in pxad_probe()
1368 of_id = of_match_device(pxad_dt_ids, &op->dev); in pxad_probe()
1370 of_property_read_u32(op->dev.of_node, "#dma-channels", in pxad_probe()
1372 ret = of_property_read_u32(op->dev.of_node, "#dma-requests", in pxad_probe()
1375 dev_warn(pdev->slave.dev, in pxad_probe()
1376 "#dma-requests set to default 32 as missing in OF: %d", in pxad_probe()
1380 } else if (pdata && pdata->dma_channels) { in pxad_probe()
1381 dma_channels = pdata->dma_channels; in pxad_probe()
1382 nb_requestors = pdata->nb_requestors; in pxad_probe()
1383 slave_map = pdata->slave_map; in pxad_probe()
1384 slave_map_cnt = pdata->slave_map_cnt; in pxad_probe()
1389 dma_cap_set(DMA_SLAVE, pdev->slave.cap_mask); in pxad_probe()
1390 dma_cap_set(DMA_MEMCPY, pdev->slave.cap_mask); in pxad_probe()
1391 dma_cap_set(DMA_CYCLIC, pdev->slave.cap_mask); in pxad_probe()
1392 dma_cap_set(DMA_PRIVATE, pdev->slave.cap_mask); in pxad_probe()
1393 pdev->slave.device_prep_dma_memcpy = pxad_prep_memcpy; in pxad_probe()
1394 pdev->slave.device_prep_slave_sg = pxad_prep_slave_sg; in pxad_probe()
1395 pdev->slave.device_prep_dma_cyclic = pxad_prep_dma_cyclic; in pxad_probe()
1396 pdev->slave.filter.map = slave_map; in pxad_probe()
1397 pdev->slave.filter.mapcnt = slave_map_cnt; in pxad_probe()
1398 pdev->slave.filter.fn = pxad_filter_fn; in pxad_probe()
1400 pdev->slave.copy_align = PDMA_ALIGNMENT; in pxad_probe()
1401 pdev->slave.src_addr_widths = widths; in pxad_probe()
1402 pdev->slave.dst_addr_widths = widths; in pxad_probe()
1403 pdev->slave.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); in pxad_probe()
1404 pdev->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; in pxad_probe()
1405 pdev->slave.descriptor_reuse = true; in pxad_probe()
1407 pdev->slave.dev = &op->dev; in pxad_probe()
1410 dev_err(pdev->slave.dev, "unable to register\n"); in pxad_probe()
1414 if (op->dev.of_node) { in pxad_probe()
1415 /* Device-tree DMA controller registration */ in pxad_probe()
1416 ret = of_dma_controller_register(op->dev.of_node, in pxad_probe()
1419 dev_err(pdev->slave.dev, in pxad_probe()
1427 dev_info(pdev->slave.dev, "initialized %d channels on %d requestors\n", in pxad_probe()
1433 { "pxa-dma", },
1439 .name = "pxa-dma",
1452 if (chan->device->dev->driver != &pxad_driver.driver) in pxad_filter_fn()
1455 c->drcmr = p->drcmr; in pxad_filter_fn()
1456 c->prio = p->prio; in pxad_filter_fn()