Lines Matching +full:use +full:- +full:minimum +full:- +full:ecc
1 // SPDX-License-Identifier: GPL-2.0-only
8 * Set by command line parameter. If BIOS has enabled the ECC, this override is
9 * cleared to prevent re-enabling the hardware by this driver.
18 /* Per-node stuff */
26 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
68 func, PCI_FUNC(pdev->devfn), offset); in __amd64_read_pci_cfg_dword()
81 func, PCI_FUNC(pdev->devfn), offset); in __amd64_write_pci_cfg_dword()
93 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); in f15h_select_dct()
94 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
96 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
106 * DCT0 -> F2x040..
107 * DCT1 -> F2x140..
116 switch (pvt->fam) { in amd64_read_dct_pci_cfg()
119 return -EINVAL; in amd64_read_dct_pci_cfg()
141 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
147 return -EINVAL; in amd64_read_dct_pci_cfg()
153 return amd64_read_pci_cfg(pvt->F2, offset, val); in amd64_read_dct_pci_cfg()
163 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
178 scrubval -= 0x5; in __f17h_set_scrubval()
179 pci_write_bits32(pvt->F6, F17H_SCR_LIMIT_ADDR, scrubval, 0xF); in __f17h_set_scrubval()
180 pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 1, 0x1); in __f17h_set_scrubval()
182 pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 0, 0x1); in __f17h_set_scrubval()
187 * issue. If requested is too big, then use last maximum value found.
203 for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) { in __set_scrub_rate()
217 if (pvt->umc) { in __set_scrub_rate()
219 } else if (pvt->fam == 0x15 && pvt->model == 0x60) { in __set_scrub_rate()
221 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
223 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
225 pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
236 struct amd64_pvt *pvt = mci->pvt_info; in set_scrub_rate()
239 if (pvt->fam == 0xf) in set_scrub_rate()
242 if (pvt->fam == 0x15) { in set_scrub_rate()
244 if (pvt->model < 0x10) in set_scrub_rate()
247 if (pvt->model == 0x60) in set_scrub_rate()
255 struct amd64_pvt *pvt = mci->pvt_info; in get_scrub_rate()
256 int i, retval = -EINVAL; in get_scrub_rate()
259 if (pvt->umc) { in get_scrub_rate()
260 amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval); in get_scrub_rate()
262 amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval); in get_scrub_rate()
268 } else if (pvt->fam == 0x15) { in get_scrub_rate()
270 if (pvt->model < 0x10) in get_scrub_rate()
273 if (pvt->model == 0x60) in get_scrub_rate()
274 amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); in get_scrub_rate()
276 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
278 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
300 /* The K8 treats this as a 40-bit value. However, bits 63-40 will be in base_limit_match()
302 * Here we discard bits 63-40. See section 3.4.2 of AMD publication in base_limit_match()
303 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 in base_limit_match()
326 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section in find_mc_by_sys_addr()
329 pvt = mci->pvt_info; in find_mc_by_sys_addr()
391 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in get_cs_base_and_mask()
392 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
393 csmask = pvt->csels[dct].csmasks[csrow]; in get_cs_base_and_mask()
402 } else if (pvt->fam == 0x16 || in get_cs_base_and_mask()
403 (pvt->fam == 0x15 && pvt->model >= 0x30)) { in get_cs_base_and_mask()
404 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
405 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
420 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
421 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
424 if (pvt->fam == 0x15) in get_cs_base_and_mask()
442 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
445 pvt->csels[dct].csbases[i]
448 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
451 for (i = 0; i < fam_type->max_mcs; i++)
455 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
463 pvt = mci->pvt_info; in input_addr_to_csrow()
476 pvt->mc_node_id); in input_addr_to_csrow()
482 (unsigned long)input_addr, pvt->mc_node_id); in input_addr_to_csrow()
484 return -1; in input_addr_to_csrow()
493 * - The revision of the node is not E or greater. In this case, the DRAM Hole
496 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
500 * complete 32-bit values despite the fact that the bitfields in the DHAR
501 * only represent bits 31-24 of the base and offset values.
506 struct amd64_pvt *pvt = mci->pvt_info; in amd64_get_dram_hole_info()
509 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) { in amd64_get_dram_hole_info()
511 pvt->ext_model, pvt->mc_node_id); in amd64_get_dram_hole_info()
516 if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) { in amd64_get_dram_hole_info()
523 pvt->mc_node_id); in amd64_get_dram_hole_info()
529 /* +------------------+--------------------+--------------------+----- in amd64_get_dram_hole_info()
531 * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | in amd64_get_dram_hole_info()
535 * | | | (0xffffffff-x))] | in amd64_get_dram_hole_info()
536 * +------------------+--------------------+--------------------+----- in amd64_get_dram_hole_info()
546 *hole_size = (1ULL << 32) - *hole_base; in amd64_get_dram_hole_info()
548 *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt) in amd64_get_dram_hole_info()
552 pvt->mc_node_id, (unsigned long)*hole_base, in amd64_get_dram_hole_info()
590 struct amd64_pvt *pvt = mci->pvt_info; in sys_addr_to_dram_addr()
594 dram_base = get_dram_base(pvt, pvt->mc_node_id); in sys_addr_to_dram_addr()
601 /* use DHAR to translate SysAddr to DramAddr */ in sys_addr_to_dram_addr()
602 dram_addr = sys_addr - hole_offset; in sys_addr_to_dram_addr()
614 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 in sys_addr_to_dram_addr()
615 * only deals with 40-bit values. Therefore we discard bits 63-40 of in sys_addr_to_dram_addr()
618 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture in sys_addr_to_dram_addr()
621 dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base; in sys_addr_to_dram_addr()
650 pvt = mci->pvt_info; in dram_addr_to_input_addr()
653 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) in dram_addr_to_input_addr()
688 err->page = (u32) (error_address >> PAGE_SHIFT); in error_address_to_page_and_offset()
689 err->offset = ((u32) error_address) & ~PAGE_MASK; in error_address_to_page_and_offset()
695 * of a node that detected an ECC memory error. mci represents the node that
697 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
706 if (csrow == -1) in sys_addr_to_csrow()
715 * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
716 * are ECC capable.
723 if (pvt->umc) { in determine_edac_cap()
727 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) in determine_edac_cap()
733 if (pvt->umc[i].umc_cfg & BIT(12)) in determine_edac_cap()
740 bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) in determine_edac_cap()
744 if (pvt->dclr0 & BIT(bit)) in determine_edac_cap()
757 if (pvt->dram_type == MEM_LRDDR3) { in debug_dump_dramcfg_low()
758 u32 dcsm = pvt->csels[chan].csmasks[0]; in debug_dump_dramcfg_low()
761 * same 'type' until proven otherwise. So, use a cs in debug_dump_dramcfg_low()
767 edac_dbg(1, "All DIMMs support ECC:%s\n", in debug_dump_dramcfg_low()
774 if (pvt->fam == 0x10) in debug_dump_dramcfg_low()
805 /* Asymmetric dual-rank DIMM support. */ in f17_get_cs_mode()
818 pvt->csels[ctrl].csmasks[0] == pvt->csels[ctrl].csmasks[1]) { in f17_get_cs_mode()
819 edac_dbg(1, "3R interleaving in use.\n"); in f17_get_cs_mode()
838 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs0); in debug_display_dimm_sizes_df()
839 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs1); in debug_display_dimm_sizes_df()
854 umc = &pvt->umc[i]; in __dump_misc_regs_df()
856 edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg); in __dump_misc_regs_df()
857 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg); in __dump_misc_regs_df()
858 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl); in __dump_misc_regs_df()
859 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in __dump_misc_regs_df()
861 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp); in __dump_misc_regs_df()
862 edac_dbg(1, "UMC%d ECC bad symbol: 0x%x\n", i, tmp); in __dump_misc_regs_df()
864 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp); in __dump_misc_regs_df()
866 edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi); in __dump_misc_regs_df()
868 edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n", in __dump_misc_regs_df()
869 i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no", in __dump_misc_regs_df()
870 (umc->umc_cap_hi & BIT(31)) ? "yes" : "no"); in __dump_misc_regs_df()
871 edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n", in __dump_misc_regs_df()
872 i, (umc->umc_cfg & BIT(12)) ? "yes" : "no"); in __dump_misc_regs_df()
874 i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no"); in __dump_misc_regs_df()
876 i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no"); in __dump_misc_regs_df()
878 if (pvt->dram_type == MEM_LRDDR4) { in __dump_misc_regs_df()
879 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ADDR_CFG, &tmp); in __dump_misc_regs_df()
888 pvt->dhar, dhar_base(pvt)); in __dump_misc_regs_df()
894 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); in __dump_misc_regs()
897 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); in __dump_misc_regs()
899 edac_dbg(1, " ECC capable: %s, ChipKill ECC capable: %s\n", in __dump_misc_regs()
900 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", in __dump_misc_regs()
901 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); in __dump_misc_regs()
903 debug_dump_dramcfg_low(pvt, pvt->dclr0, 0); in __dump_misc_regs()
905 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); in __dump_misc_regs()
908 pvt->dhar, dhar_base(pvt), in __dump_misc_regs()
909 (pvt->fam == 0xf) ? k8_dhar_offset(pvt) in __dump_misc_regs()
915 if (pvt->fam == 0xf) in __dump_misc_regs()
922 debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); in __dump_misc_regs()
928 if (pvt->umc) in dump_misc_regs()
935 amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz); in dump_misc_regs()
943 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in prep_chip_selects()
944 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in prep_chip_selects()
945 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; in prep_chip_selects()
946 } else if (pvt->fam == 0x15 && pvt->model == 0x30) { in prep_chip_selects()
947 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4; in prep_chip_selects()
948 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; in prep_chip_selects()
949 } else if (pvt->fam >= 0x17) { in prep_chip_selects()
953 pvt->csels[umc].b_cnt = 4; in prep_chip_selects()
954 pvt->csels[umc].m_cnt = 2; in prep_chip_selects()
958 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in prep_chip_selects()
959 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; in prep_chip_selects()
978 base = &pvt->csels[umc].csbases[cs]; in read_umc_base_mask()
979 base_sec = &pvt->csels[umc].csbases_sec[cs]; in read_umc_base_mask()
984 if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) in read_umc_base_mask()
988 if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, base_sec)) in read_umc_base_mask()
997 mask = &pvt->csels[umc].csmasks[cs]; in read_umc_base_mask()
998 mask_sec = &pvt->csels[umc].csmasks_sec[cs]; in read_umc_base_mask()
1003 if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) in read_umc_base_mask()
1007 if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, mask_sec)) in read_umc_base_mask()
1023 if (pvt->umc) in read_dct_base_mask()
1029 u32 *base0 = &pvt->csels[0].csbases[cs]; in read_dct_base_mask()
1030 u32 *base1 = &pvt->csels[1].csbases[cs]; in read_dct_base_mask()
1036 if (pvt->fam == 0xf) in read_dct_base_mask()
1041 cs, *base1, (pvt->fam == 0x10) ? reg1 in read_dct_base_mask()
1048 u32 *mask0 = &pvt->csels[0].csmasks[cs]; in read_dct_base_mask()
1049 u32 *mask1 = &pvt->csels[1].csmasks[cs]; in read_dct_base_mask()
1055 if (pvt->fam == 0xf) in read_dct_base_mask()
1060 cs, *mask1, (pvt->fam == 0x10) ? reg1 in read_dct_base_mask()
1069 if (pvt->umc) { in determine_memory_type()
1070 if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) in determine_memory_type()
1071 pvt->dram_type = MEM_LRDDR4; in determine_memory_type()
1072 else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) in determine_memory_type()
1073 pvt->dram_type = MEM_RDDR4; in determine_memory_type()
1075 pvt->dram_type = MEM_DDR4; in determine_memory_type()
1079 switch (pvt->fam) { in determine_memory_type()
1081 if (pvt->ext_model >= K8_REV_F) in determine_memory_type()
1084 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; in determine_memory_type()
1088 if (pvt->dchr0 & DDR3_MODE) in determine_memory_type()
1091 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; in determine_memory_type()
1095 if (pvt->model < 0x60) in determine_memory_type()
1101 * We use a Chip Select value of '0' to obtain dcsm. in determine_memory_type()
1108 dcsm = pvt->csels[0].csmasks[0]; in determine_memory_type()
1111 pvt->dram_type = MEM_DDR4; in determine_memory_type()
1112 else if (pvt->dclr0 & BIT(16)) in determine_memory_type()
1113 pvt->dram_type = MEM_DDR3; in determine_memory_type()
1115 pvt->dram_type = MEM_LRDDR3; in determine_memory_type()
1117 pvt->dram_type = MEM_RDDR3; in determine_memory_type()
1125 WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); in determine_memory_type()
1126 pvt->dram_type = MEM_EMPTY; in determine_memory_type()
1131 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; in determine_memory_type()
1139 if (pvt->ext_model >= K8_REV_F) in k8_early_channel_count()
1141 flag = pvt->dclr0 & WIDTH_128; in k8_early_channel_count()
1144 flag = pvt->dclr0 & REVE_WIDTH_128; in k8_early_channel_count()
1147 pvt->dclr1 = 0; in k8_early_channel_count()
1155 u16 mce_nid = amd_get_nb_id(m->extcpu); in get_error_address()
1165 pvt = mci->pvt_info; in get_error_address()
1167 if (pvt->fam == 0xf) { in get_error_address()
1172 addr = m->addr & GENMASK_ULL(end_bit, start_bit); in get_error_address()
1177 if (pvt->fam == 0x15) { in get_error_address()
1186 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); in get_error_address()
1201 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); in get_error_address()
1225 if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) && in pci_get_related_function()
1226 (dev->bus->number == related->bus->number) && in pci_get_related_function()
1227 (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) in pci_get_related_function()
1242 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); in read_dram_base_limit_regs()
1243 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); in read_dram_base_limit_regs()
1245 if (pvt->fam == 0xf) in read_dram_base_limit_regs()
1251 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); in read_dram_base_limit_regs()
1252 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); in read_dram_base_limit_regs()
1255 if (pvt->fam != 0x15) in read_dram_base_limit_regs()
1262 if (pvt->model == 0x60) in read_dram_base_limit_regs()
1264 else if (pvt->model == 0x30) in read_dram_base_limit_regs()
1269 f1 = pci_get_related_function(nb->misc->vendor, pci_func, nb->misc); in read_dram_base_limit_regs()
1275 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0); in read_dram_base_limit_regs()
1278 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; in read_dram_base_limit_regs()
1280 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0); in read_dram_base_limit_regs()
1283 pvt->ranges[range].lim.hi |= llim >> 13; in read_dram_base_limit_regs()
1291 struct amd64_pvt *pvt = mci->pvt_info; in k8_map_sysaddr_to_csrow()
1299 err->src_mci = find_mc_by_sys_addr(mci, sys_addr); in k8_map_sysaddr_to_csrow()
1300 if (!err->src_mci) { in k8_map_sysaddr_to_csrow()
1303 err->err_code = ERR_NODE; in k8_map_sysaddr_to_csrow()
1308 err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr); in k8_map_sysaddr_to_csrow()
1309 if (err->csrow < 0) { in k8_map_sysaddr_to_csrow()
1310 err->err_code = ERR_CSROW; in k8_map_sysaddr_to_csrow()
1315 if (pvt->nbcfg & NBCFG_CHIPKILL) { in k8_map_sysaddr_to_csrow()
1316 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); in k8_map_sysaddr_to_csrow()
1317 if (err->channel < 0) { in k8_map_sysaddr_to_csrow()
1323 amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - " in k8_map_sysaddr_to_csrow()
1325 err->syndrome); in k8_map_sysaddr_to_csrow()
1326 err->err_code = ERR_CHANNEL; in k8_map_sysaddr_to_csrow()
1331 * non-chipkill ecc mode in k8_map_sysaddr_to_csrow()
1334 * channel number when using non-chipkill memory. This method in k8_map_sysaddr_to_csrow()
1336 * (Wish the email was placed in this comment - norsk) in k8_map_sysaddr_to_csrow()
1338 err->channel = ((sys_addr & BIT(3)) != 0); in k8_map_sysaddr_to_csrow()
1359 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in k8_dbam_to_chip_select()
1361 if (pvt->ext_model >= K8_REV_F) { in k8_dbam_to_chip_select()
1365 else if (pvt->ext_model >= K8_REV_D) { in k8_dbam_to_chip_select()
1395 return 32 << (cs_mode - diff); in k8_dbam_to_chip_select()
1404 * Get the number of DCT channels in use.
1416 if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128)) in f1x_early_channel_count()
1427 edac_dbg(0, "Data width is not 128 bits - need more decoding\n"); in f1x_early_channel_count()
1435 u32 dbam = (i ? pvt->dbam1 : pvt->dbam0); in f1x_early_channel_count()
1459 channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT); in f17_early_channel_count()
1472 cs_size = -1; in ddr3_cs_size()
1482 if (cs_size != -1) in ddr3_cs_size()
1494 cs_size = -1; in ddr3_lrdimm_cs_size()
1502 if (cs_size != -1) in ddr3_lrdimm_cs_size()
1513 cs_size = -1; in ddr4_cs_size()
1526 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in f10_dbam_to_chip_select()
1530 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) in f10_dbam_to_chip_select()
1552 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; in f15_m60h_dbam_to_chip_select()
1556 if (pvt->dram_type == MEM_DDR4) { in f15_m60h_dbam_to_chip_select()
1558 return -1; in f15_m60h_dbam_to_chip_select()
1561 } else if (pvt->dram_type == MEM_LRDDR3) { in f15_m60h_dbam_to_chip_select()
1568 /* Minimum cs size is 512mb for F15hM60h*/ in f15_m60h_dbam_to_chip_select()
1570 return -1; in f15_m60h_dbam_to_chip_select()
1588 return -1; in f16_dbam_to_chip_select()
1614 * CS0 and CS1 -> DIMM0 in f17_addr_mask_to_cs_size()
1615 * CS2 and CS3 -> DIMM1 in f17_addr_mask_to_cs_size()
1619 /* Asymmetric dual-rank DIMM support. */ in f17_addr_mask_to_cs_size()
1621 addr_mask_orig = pvt->csels[umc].csmasks_sec[dimm]; in f17_addr_mask_to_cs_size()
1623 addr_mask_orig = pvt->csels[umc].csmasks[dimm]; in f17_addr_mask_to_cs_size()
1636 msb = fls(addr_mask_orig) - 1; in f17_addr_mask_to_cs_size()
1638 num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE); in f17_addr_mask_to_cs_size()
1641 addr_mask_deinterleaved = GENMASK_ULL(msb - num_zero_bits, 1); in f17_addr_mask_to_cs_size()
1657 if (pvt->fam == 0xf) in read_dram_ctl_register()
1660 if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) { in read_dram_ctl_register()
1662 pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); in read_dram_ctl_register()
1671 edac_dbg(0, " data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n", in read_dram_ctl_register()
1681 amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi); in read_dram_ctl_register()
1722 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; in f1x_determine_channel()
1731 * see F2x110[DctSelIntLvAddr] - channel interleave mode in f1x_determine_channel()
1770 u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16; in f1x_get_norm_dct_addr()
1807 return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23)); in f1x_get_norm_dct_addr()
1836 * -EINVAL: NOT FOUND
1837 * 0..csrow = Chip-Select Row
1844 int cs_found = -EINVAL; in f1x_lookup_addr_in_dct()
1851 pvt = mci->pvt_info; in f1x_lookup_addr_in_dct()
1870 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in f1x_lookup_addr_in_dct()
1884 * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is
1885 * swapped with a region located at the bottom of memory so that the GPU can use
1892 if (pvt->fam == 0x10) { in f1x_swap_interleaved_region()
1894 if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3)) in f1x_swap_interleaved_region()
1898 amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg); in f1x_swap_interleaved_region()
1921 int cs_found = -EINVAL; in f1x_match_to_this_node()
1939 return -EINVAL; in f1x_match_to_this_node()
1943 return -EINVAL; in f1x_match_to_this_node()
2001 int cs_found = -EINVAL; in f15_m30h_match_to_this_node()
2013 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg); in f15_m30h_match_to_this_node()
2014 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg); in f15_m30h_match_to_this_node()
2024 return -EINVAL; in f15_m30h_match_to_this_node()
2031 return -EINVAL; in f15_m30h_match_to_this_node()
2041 return -EINVAL; in f15_m30h_match_to_this_node()
2047 return -EINVAL; in f15_m30h_match_to_this_node()
2049 if (pvt->model >= 0x60) in f15_m30h_match_to_this_node()
2057 return -EINVAL; in f15_m30h_match_to_this_node()
2067 chan_addr = sys_addr - chan_offset; in f15_m30h_match_to_this_node()
2078 return -EINVAL; in f15_m30h_match_to_this_node()
2088 return -EINVAL; in f15_m30h_match_to_this_node()
2092 amd64_read_pci_cfg(pvt->F1, in f15_m30h_match_to_this_node()
2107 * pvt->csels[1]. So we need to use '1' here to get correct info. in f15_m30h_match_to_this_node()
2124 int cs_found = -EINVAL; in f1x_translate_sysaddr_to_cs()
2131 if (pvt->fam == 0x15 && pvt->model >= 0x30) in f1x_translate_sysaddr_to_cs()
2157 struct amd64_pvt *pvt = mci->pvt_info; in f1x_map_sysaddr_to_csrow()
2161 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel); in f1x_map_sysaddr_to_csrow()
2162 if (err->csrow < 0) { in f1x_map_sysaddr_to_csrow()
2163 err->err_code = ERR_CSROW; in f1x_map_sysaddr_to_csrow()
2173 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); in f1x_map_sysaddr_to_csrow()
2183 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; in debug_display_dimm_sizes()
2184 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; in debug_display_dimm_sizes()
2186 if (pvt->fam == 0xf) { in debug_display_dimm_sizes()
2188 if (pvt->ext_model < K8_REV_F) in debug_display_dimm_sizes()
2194 if (pvt->fam == 0x10) { in debug_display_dimm_sizes()
2195 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 in debug_display_dimm_sizes()
2196 : pvt->dbam0; in debug_display_dimm_sizes()
2198 pvt->csels[1].csbases : in debug_display_dimm_sizes()
2199 pvt->csels[0].csbases; in debug_display_dimm_sizes()
2201 dbam = pvt->dbam0; in debug_display_dimm_sizes()
2202 dcsb = pvt->csels[1].csbases; in debug_display_dimm_sizes()
2220 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, in debug_display_dimm_sizes()
2226 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, in debug_display_dimm_sizes()
2477 return -1; in decode_syndrome()
2503 return -1; in map_err_sym_to_channel()
2516 return -1; in map_err_sym_to_channel()
2521 struct amd64_pvt *pvt = mci->pvt_info; in get_channel_from_ecc_syndrome()
2522 int err_sym = -1; in get_channel_from_ecc_syndrome()
2524 if (pvt->ecc_sym_sz == 8) in get_channel_from_ecc_syndrome()
2527 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2528 else if (pvt->ecc_sym_sz == 4) in get_channel_from_ecc_syndrome()
2531 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2533 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2537 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2557 switch (err->err_code) { in __log_ecc_error()
2568 string = "Unknown syndrome - possible error reporting race"; in __log_ecc_error()
2571 string = "MCA_SYND not valid - unknown syndrome and csrow"; in __log_ecc_error()
2582 err->page, err->offset, err->syndrome, in __log_ecc_error()
2583 err->csrow, err->channel, -1, in __log_ecc_error()
2591 u8 ecc_type = (m->status >> 45) & 0x3; in decode_bus_error()
2592 u8 xec = XEC(m->status, 0x1f); in decode_bus_error()
2593 u16 ec = EC(m->status); in decode_bus_error()
2601 pvt = mci->pvt_info; in decode_bus_error()
2607 /* Do only ECC errors */ in decode_bus_error()
2616 err.syndrome = extract_syndrome(m->status); in decode_bus_error()
2618 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err); in decode_bus_error()
2634 return (m->ipid & GENMASK(31, 0)) >> 20; in find_umc_channel()
2639 u8 ecc_type = (m->status >> 45) & 0x3; in decode_umc_error()
2649 pvt = mci->pvt_info; in decode_umc_error()
2653 if (m->status & MCI_STATUS_DEFERRED) in decode_umc_error()
2658 if (!(m->status & MCI_STATUS_SYNDV)) { in decode_umc_error()
2664 u8 length = (m->synd >> 18) & 0x3f; in decode_umc_error()
2667 err.syndrome = (m->synd >> 32) & GENMASK(length - 1, 0); in decode_umc_error()
2672 err.csrow = m->synd & 0x7; in decode_umc_error()
2674 if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) { in decode_umc_error()
2686 * Use pvt->F3 which contains the F3 CPU PCI device to get the related
2693 if (pvt->umc) { in reserve_mc_sibling_devs()
2694 pvt->F0 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); in reserve_mc_sibling_devs()
2695 if (!pvt->F0) { in reserve_mc_sibling_devs()
2697 return -ENODEV; in reserve_mc_sibling_devs()
2700 pvt->F6 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); in reserve_mc_sibling_devs()
2701 if (!pvt->F6) { in reserve_mc_sibling_devs()
2702 pci_dev_put(pvt->F0); in reserve_mc_sibling_devs()
2703 pvt->F0 = NULL; in reserve_mc_sibling_devs()
2706 return -ENODEV; in reserve_mc_sibling_devs()
2710 pci_ctl_dev = &pvt->F0->dev; in reserve_mc_sibling_devs()
2712 edac_dbg(1, "F0: %s\n", pci_name(pvt->F0)); in reserve_mc_sibling_devs()
2713 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2714 edac_dbg(1, "F6: %s\n", pci_name(pvt->F6)); in reserve_mc_sibling_devs()
2720 pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); in reserve_mc_sibling_devs()
2721 if (!pvt->F1) { in reserve_mc_sibling_devs()
2723 return -ENODEV; in reserve_mc_sibling_devs()
2727 pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); in reserve_mc_sibling_devs()
2728 if (!pvt->F2) { in reserve_mc_sibling_devs()
2729 pci_dev_put(pvt->F1); in reserve_mc_sibling_devs()
2730 pvt->F1 = NULL; in reserve_mc_sibling_devs()
2733 return -ENODEV; in reserve_mc_sibling_devs()
2737 pci_ctl_dev = &pvt->F2->dev; in reserve_mc_sibling_devs()
2739 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1)); in reserve_mc_sibling_devs()
2740 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2)); in reserve_mc_sibling_devs()
2741 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2748 if (pvt->umc) { in free_mc_sibling_devs()
2749 pci_dev_put(pvt->F0); in free_mc_sibling_devs()
2750 pci_dev_put(pvt->F6); in free_mc_sibling_devs()
2752 pci_dev_put(pvt->F1); in free_mc_sibling_devs()
2753 pci_dev_put(pvt->F2); in free_mc_sibling_devs()
2759 pvt->ecc_sym_sz = 4; in determine_ecc_sym_sz()
2761 if (pvt->umc) { in determine_ecc_sym_sz()
2766 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in determine_ecc_sym_sz()
2767 if (pvt->umc[i].ecc_ctrl & BIT(9)) { in determine_ecc_sym_sz()
2768 pvt->ecc_sym_sz = 16; in determine_ecc_sym_sz()
2770 } else if (pvt->umc[i].ecc_ctrl & BIT(7)) { in determine_ecc_sym_sz()
2771 pvt->ecc_sym_sz = 8; in determine_ecc_sym_sz()
2776 } else if (pvt->fam >= 0x10) { in determine_ecc_sym_sz()
2779 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); in determine_ecc_sym_sz()
2781 if (pvt->fam != 0x16) in determine_ecc_sym_sz()
2782 amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1); in determine_ecc_sym_sz()
2784 /* F10h, revD and later can do x8 ECC too. */ in determine_ecc_sym_sz()
2785 if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25)) in determine_ecc_sym_sz()
2786 pvt->ecc_sym_sz = 8; in determine_ecc_sym_sz()
2795 u8 nid = pvt->mc_node_id; in __read_mc_regs_df()
2803 umc = &pvt->umc[i]; in __read_mc_regs_df()
2805 amd_smn_read(nid, umc_base + UMCCH_DIMM_CFG, &umc->dimm_cfg); in __read_mc_regs_df()
2806 amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg); in __read_mc_regs_df()
2807 amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl); in __read_mc_regs_df()
2808 amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); in __read_mc_regs_df()
2809 amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi); in __read_mc_regs_df()
2824 * those are Read-As-Zero. in read_mc_regs()
2826 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); in read_mc_regs()
2827 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); in read_mc_regs()
2832 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); in read_mc_regs()
2833 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); in read_mc_regs()
2838 if (pvt->umc) { in read_mc_regs()
2840 amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar); in read_mc_regs()
2845 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); in read_mc_regs()
2866 (rw & 0x1) ? "R" : "-", in read_mc_regs()
2867 (rw & 0x2) ? "W" : "-", in read_mc_regs()
2872 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); in read_mc_regs()
2873 amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0); in read_mc_regs()
2875 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); in read_mc_regs()
2877 amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0); in read_mc_regs()
2878 amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0); in read_mc_regs()
2881 amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); in read_mc_regs()
2882 amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); in read_mc_regs()
2889 edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); in read_mc_regs()
2898 * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1)
2899 * k8 private pointer to -->
2907 * 0-3 CSROWs 0 and 1
2908 * 4-7 CSROWs 2 and 3
2909 * 8-11 CSROWs 4 and 5
2910 * 12-15 CSROWs 6 and 7
2913 * The meaning of the values depends on CPU revision and dual-channel state,
2930 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; in get_csrow_nr_pages()
2934 if (!pvt->umc) { in get_csrow_nr_pages()
2941 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); in get_csrow_nr_pages()
2942 nr_pages <<= 20 - PAGE_SHIFT; in get_csrow_nr_pages()
2953 struct amd64_pvt *pvt = mci->pvt_info; in init_csrows_df()
2960 if (mci->edac_ctl_cap & EDAC_FLAG_S16ECD16ED) { in init_csrows_df()
2963 } else if (mci->edac_ctl_cap & EDAC_FLAG_S8ECD8ED) { in init_csrows_df()
2966 } else if (mci->edac_ctl_cap & EDAC_FLAG_S4ECD4ED) { in init_csrows_df()
2969 } else if (mci->edac_ctl_cap & EDAC_FLAG_SECDED) { in init_csrows_df()
2979 dimm = mci->csrows[cs]->channels[umc]->dimm; in init_csrows_df()
2982 pvt->mc_node_id, cs); in init_csrows_df()
2984 dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs); in init_csrows_df()
2985 dimm->mtype = pvt->dram_type; in init_csrows_df()
2986 dimm->edac_mode = edac_mode; in init_csrows_df()
2987 dimm->dtype = dev_type; in init_csrows_df()
2988 dimm->grain = 64; in init_csrows_df()
3001 struct amd64_pvt *pvt = mci->pvt_info; in init_csrows()
3009 if (pvt->umc) in init_csrows()
3012 amd64_read_pci_cfg(pvt->F3, NBCFG, &val); in init_csrows()
3014 pvt->nbcfg = val; in init_csrows()
3017 pvt->mc_node_id, val, in init_csrows()
3027 if (pvt->fam != 0xf) in init_csrows()
3033 csrow = mci->csrows[i]; in init_csrows()
3037 pvt->mc_node_id, i); in init_csrows()
3041 csrow->channels[0]->dimm->nr_pages = nr_pages; in init_csrows()
3045 if (pvt->fam != 0xf && row_dct1) { in init_csrows()
3048 csrow->channels[1]->dimm->nr_pages = row_dct1_pages; in init_csrows()
3054 /* Determine DIMM ECC mode: */ in init_csrows()
3055 if (pvt->nbcfg & NBCFG_ECC_ENABLE) { in init_csrows()
3056 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) in init_csrows()
3061 for (j = 0; j < pvt->channel_count; j++) { in init_csrows()
3062 dimm = csrow->channels[j]->dimm; in init_csrows()
3063 dimm->mtype = pvt->dram_type; in init_csrows()
3064 dimm->edac_mode = edac_mode; in init_csrows()
3065 dimm->grain = 64; in init_csrows()
3100 nbe = reg->l & MSR_MCGCTL_NBE; in nb_mce_bank_enabled_on_node()
3103 cpu, reg->q, in nb_mce_bank_enabled_on_node()
3123 return -ENOMEM; in toggle_ecc_err_reporting()
3135 if (reg->l & MSR_MCGCTL_NBE) in toggle_ecc_err_reporting()
3136 s->flags.nb_mce_enable = 1; in toggle_ecc_err_reporting()
3138 reg->l |= MSR_MCGCTL_NBE; in toggle_ecc_err_reporting()
3143 if (!s->flags.nb_mce_enable) in toggle_ecc_err_reporting()
3144 reg->l &= ~MSR_MCGCTL_NBE; in toggle_ecc_err_reporting()
3161 amd64_warn("Error enabling ECC reporting over MCGCTL!\n"); in enable_ecc_error_reporting()
3167 s->old_nbctl = value & mask; in enable_ecc_error_reporting()
3168 s->nbctl_valid = true; in enable_ecc_error_reporting()
3179 amd64_warn("DRAM ECC disabled on this node, enabling...\n"); in enable_ecc_error_reporting()
3181 s->flags.nb_ecc_prev = 0; in enable_ecc_error_reporting()
3183 /* Attempt to turn on DRAM ECC Enable */ in enable_ecc_error_reporting()
3190 amd64_warn("Hardware rejected DRAM ECC enable," in enable_ecc_error_reporting()
3194 amd64_info("Hardware accepted DRAM ECC Enable\n"); in enable_ecc_error_reporting()
3197 s->flags.nb_ecc_prev = 1; in enable_ecc_error_reporting()
3211 if (!s->nbctl_valid) in restore_ecc_error_reporting()
3216 value |= s->old_nbctl; in restore_ecc_error_reporting()
3220 /* restore previous BIOS DRAM ECC "off" setting we force-enabled */ in restore_ecc_error_reporting()
3221 if (!s->flags.nb_ecc_prev) { in restore_ecc_error_reporting()
3234 u16 nid = pvt->mc_node_id; in ecc_enabled()
3244 umc = &pvt->umc[i]; in ecc_enabled()
3247 if (!(umc->sdp_ctrl & UMC_SDP_INIT)) in ecc_enabled()
3252 if (umc->umc_cap_hi & UMC_ECC_ENABLED) in ecc_enabled()
3265 amd64_read_pci_cfg(pvt->F3, NBCFG, &value); in ecc_enabled()
3275 amd64_info("Node %d: DRAM ECC %s.\n", in ecc_enabled()
3290 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in f17h_determine_edac_ctl_cap()
3291 ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED); in f17h_determine_edac_ctl_cap()
3292 cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP); in f17h_determine_edac_ctl_cap()
3294 dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6)); in f17h_determine_edac_ctl_cap()
3295 dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7)); in f17h_determine_edac_ctl_cap()
3299 /* Set chipkill only if ECC is enabled: */ in f17h_determine_edac_ctl_cap()
3301 mci->edac_ctl_cap |= EDAC_FLAG_SECDED; in f17h_determine_edac_ctl_cap()
3307 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; in f17h_determine_edac_ctl_cap()
3309 mci->edac_ctl_cap |= EDAC_FLAG_S16ECD16ED; in f17h_determine_edac_ctl_cap()
3311 mci->edac_ctl_cap |= EDAC_FLAG_S8ECD8ED; in f17h_determine_edac_ctl_cap()
3317 struct amd64_pvt *pvt = mci->pvt_info; in setup_mci_misc_attrs()
3319 mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; in setup_mci_misc_attrs()
3320 mci->edac_ctl_cap = EDAC_FLAG_NONE; in setup_mci_misc_attrs()
3322 if (pvt->umc) { in setup_mci_misc_attrs()
3325 if (pvt->nbcap & NBCAP_SECDED) in setup_mci_misc_attrs()
3326 mci->edac_ctl_cap |= EDAC_FLAG_SECDED; in setup_mci_misc_attrs()
3328 if (pvt->nbcap & NBCAP_CHIPKILL) in setup_mci_misc_attrs()
3329 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; in setup_mci_misc_attrs()
3332 mci->edac_cap = determine_edac_cap(pvt); in setup_mci_misc_attrs()
3333 mci->mod_name = EDAC_MOD_STR; in setup_mci_misc_attrs()
3334 mci->ctl_name = fam_type->ctl_name; in setup_mci_misc_attrs()
3335 mci->dev_name = pci_name(pvt->F3); in setup_mci_misc_attrs()
3336 mci->ctl_page_to_phys = NULL; in setup_mci_misc_attrs()
3339 mci->set_sdram_scrub_rate = set_scrub_rate; in setup_mci_misc_attrs()
3340 mci->get_sdram_scrub_rate = get_scrub_rate; in setup_mci_misc_attrs()
3348 pvt->ext_model = boot_cpu_data.x86_model >> 4; in per_family_init()
3349 pvt->stepping = boot_cpu_data.x86_stepping; in per_family_init()
3350 pvt->model = boot_cpu_data.x86_model; in per_family_init()
3351 pvt->fam = boot_cpu_data.x86; in per_family_init()
3353 switch (pvt->fam) { in per_family_init()
3356 pvt->ops = &family_types[K8_CPUS].ops; in per_family_init()
3361 pvt->ops = &family_types[F10_CPUS].ops; in per_family_init()
3365 if (pvt->model == 0x30) { in per_family_init()
3367 pvt->ops = &family_types[F15_M30H_CPUS].ops; in per_family_init()
3369 } else if (pvt->model == 0x60) { in per_family_init()
3371 pvt->ops = &family_types[F15_M60H_CPUS].ops; in per_family_init()
3374 } else if (pvt->model == 0x13) { in per_family_init()
3378 pvt->ops = &family_types[F15_CPUS].ops; in per_family_init()
3383 if (pvt->model == 0x30) { in per_family_init()
3385 pvt->ops = &family_types[F16_M30H_CPUS].ops; in per_family_init()
3389 pvt->ops = &family_types[F16_CPUS].ops; in per_family_init()
3393 if (pvt->model >= 0x10 && pvt->model <= 0x2f) { in per_family_init()
3395 pvt->ops = &family_types[F17_M10H_CPUS].ops; in per_family_init()
3397 } else if (pvt->model >= 0x30 && pvt->model <= 0x3f) { in per_family_init()
3399 pvt->ops = &family_types[F17_M30H_CPUS].ops; in per_family_init()
3401 } else if (pvt->model >= 0x60 && pvt->model <= 0x6f) { in per_family_init()
3403 pvt->ops = &family_types[F17_M60H_CPUS].ops; in per_family_init()
3405 } else if (pvt->model >= 0x70 && pvt->model <= 0x7f) { in per_family_init()
3407 pvt->ops = &family_types[F17_M70H_CPUS].ops; in per_family_init()
3413 pvt->ops = &family_types[F17_CPUS].ops; in per_family_init()
3415 if (pvt->fam == 0x18) in per_family_init()
3420 if (pvt->model >= 0x20 && pvt->model <= 0x2f) { in per_family_init()
3422 pvt->ops = &family_types[F17_M70H_CPUS].ops; in per_family_init()
3423 fam_type->ctl_name = "F19h_M20h"; in per_family_init()
3427 pvt->ops = &family_types[F19_CPUS].ops; in per_family_init()
3436 amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name, in per_family_init()
3437 (pvt->fam == 0xf ? in per_family_init()
3438 (pvt->ext_model >= K8_REV_F ? "revF or later " in per_family_init()
3440 : ""), pvt->mc_node_id); in per_family_init()
3459 if (pvt->fam >= 0x17) { in hw_info_get()
3460 pvt->umc = kcalloc(fam_type->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); in hw_info_get()
3461 if (!pvt->umc) in hw_info_get()
3462 return -ENOMEM; in hw_info_get()
3464 pci_id1 = fam_type->f0_id; in hw_info_get()
3465 pci_id2 = fam_type->f6_id; in hw_info_get()
3467 pci_id1 = fam_type->f1_id; in hw_info_get()
3468 pci_id2 = fam_type->f2_id; in hw_info_get()
3482 if (pvt->F0 || pvt->F1) in hw_info_put()
3485 kfree(pvt->umc); in hw_info_put()
3492 int ret = -EINVAL; in init_one_instance()
3495 * We need to determine how many memory channels there are. Then use in init_one_instance()
3499 pvt->channel_count = pvt->ops->early_channel_count(pvt); in init_one_instance()
3500 if (pvt->channel_count < 0) in init_one_instance()
3503 ret = -ENOMEM; in init_one_instance()
3505 layers[0].size = pvt->csels[0].b_cnt; in init_one_instance()
3514 layers[1].size = fam_type->max_mcs; in init_one_instance()
3517 mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layers, 0); in init_one_instance()
3521 mci->pvt_info = pvt; in init_one_instance()
3522 mci->pdev = &pvt->F3->dev; in init_one_instance()
3527 mci->edac_cap = EDAC_FLAG_NONE; in init_one_instance()
3529 ret = -ENODEV; in init_one_instance()
3544 for (dct = 0; dct < fam_type->max_mcs; dct++) { in instance_has_memory()
3554 struct pci_dev *F3 = node_to_amd_nb(nid)->misc; in probe_one_instance()
3559 ret = -ENOMEM; in probe_one_instance()
3570 pvt->mc_node_id = nid; in probe_one_instance()
3571 pvt->F3 = F3; in probe_one_instance()
3573 ret = -ENODEV; in probe_one_instance()
3589 ret = -ENODEV; in probe_one_instance()
3595 amd64_warn("Forcing ECC on is not recommended on newer systems. Please enable ECC in BIOS."); in probe_one_instance()
3598 amd64_warn("Forcing ECC on!\n"); in probe_one_instance()
3632 struct pci_dev *F3 = node_to_amd_nb(nid)->misc; in remove_one_instance()
3638 mci = edac_mc_del_mc(&F3->dev); in remove_one_instance()
3642 pvt = mci->pvt_info; in remove_one_instance()
3650 mci->pvt_info = NULL; in remove_one_instance()
3684 int err = -ENODEV; in amd64_edac_init()
3689 return -EBUSY; in amd64_edac_init()
3692 return -ENODEV; in amd64_edac_init()
3695 return -ENODEV; in amd64_edac_init()
3699 err = -ENOMEM; in amd64_edac_init()
3712 while (--i >= 0) in amd64_edac_init()
3720 err = -ENODEV; in amd64_edac_init()
3733 amd64_err("%s on 32-bit is unsupported. USE AT YOUR OWN RISK!\n", EDAC_MOD_STR); in amd64_edac_init()
3784 MODULE_DESCRIPTION("MC support for AMD64 memory controllers - "