Lines Matching +full:reg +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-or-later
21 * MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
101 const enum aspeed_sgpio_reg reg) in bank_reg() argument
103 switch (reg) { in bank_reg()
105 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
107 return gpio->base + bank->rdata_reg; in bank_reg()
109 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
111 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
113 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
115 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
117 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
128 static const struct aspeed_sgpio_bank *to_bank(unsigned int offset) in to_bank() argument
132 bank = GPIO_BANK(offset); in to_bank()
142 int n = sgpio->n_sgpio; in aspeed_sgpio_init_valid_mask()
143 int c = SGPIO_OUTPUT_OFFSET - n; in aspeed_sgpio_init_valid_mask()
162 int n = sgpio->n_sgpio; in aspeed_sgpio_irq_init_valid_mask()
168 bitmap_clear(valid_mask, n, ngpios - n); in aspeed_sgpio_irq_init_valid_mask()
171 static bool aspeed_sgpio_is_input(unsigned int offset) in aspeed_sgpio_is_input() argument
173 return offset < SGPIO_OUTPUT_OFFSET; in aspeed_sgpio_is_input()
176 static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset) in aspeed_sgpio_get() argument
179 const struct aspeed_sgpio_bank *bank = to_bank(offset); in aspeed_sgpio_get()
181 enum aspeed_sgpio_reg reg; in aspeed_sgpio_get() local
184 spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_get()
186 reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata; in aspeed_sgpio_get()
187 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); in aspeed_sgpio_get()
189 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_get()
194 static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val) in sgpio_set_value() argument
197 const struct aspeed_sgpio_bank *bank = to_bank(offset); in sgpio_set_value()
199 u32 reg = 0; in sgpio_set_value() local
201 if (aspeed_sgpio_is_input(offset)) in sgpio_set_value()
202 return -EINVAL; in sgpio_set_value()
209 reg = ioread32(addr_r); in sgpio_set_value()
212 reg |= GPIO_BIT(offset); in sgpio_set_value()
214 reg &= ~GPIO_BIT(offset); in sgpio_set_value()
216 iowrite32(reg, addr_w); in sgpio_set_value()
221 static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val) in aspeed_sgpio_set() argument
226 spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_set()
228 sgpio_set_value(gc, offset, val); in aspeed_sgpio_set()
230 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_set()
233 static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset) in aspeed_sgpio_dir_in() argument
235 return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL; in aspeed_sgpio_dir_in()
238 static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val) in aspeed_sgpio_dir_out() argument
245 * error-out in sgpio_set_value if this isn't an output GPIO */ in aspeed_sgpio_dir_out()
247 spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_dir_out()
248 rc = sgpio_set_value(gc, offset, val); in aspeed_sgpio_dir_out()
249 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_dir_out()
254 static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset) in aspeed_sgpio_get_direction() argument
256 return !!aspeed_sgpio_is_input(offset); in aspeed_sgpio_get_direction()
262 u32 *bit, int *offset) in irqd_to_aspeed_sgpio_data() argument
266 *offset = irqd_to_hwirq(d); in irqd_to_aspeed_sgpio_data()
271 *bank = to_bank(*offset); in irqd_to_aspeed_sgpio_data()
272 *bit = GPIO_BIT(*offset); in irqd_to_aspeed_sgpio_data()
281 int offset; in aspeed_sgpio_irq_ack() local
284 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_sgpio_irq_ack()
288 spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_irq_ack()
292 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_irq_ack()
300 u32 reg, bit; in aspeed_sgpio_irq_set_mask() local
302 int offset; in aspeed_sgpio_irq_set_mask() local
304 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_sgpio_irq_set_mask()
307 spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_irq_set_mask()
309 reg = ioread32(addr); in aspeed_sgpio_irq_set_mask()
311 reg |= bit; in aspeed_sgpio_irq_set_mask()
313 reg &= ~bit; in aspeed_sgpio_irq_set_mask()
315 iowrite32(reg, addr); in aspeed_sgpio_irq_set_mask()
317 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_irq_set_mask()
335 u32 bit, reg; in aspeed_sgpio_set_type() local
341 int offset; in aspeed_sgpio_set_type() local
343 irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_sgpio_set_type()
363 return -EINVAL; in aspeed_sgpio_set_type()
366 spin_lock_irqsave(&gpio->lock, flags); in aspeed_sgpio_set_type()
369 reg = ioread32(addr); in aspeed_sgpio_set_type()
370 reg = (reg & ~bit) | type0; in aspeed_sgpio_set_type()
371 iowrite32(reg, addr); in aspeed_sgpio_set_type()
374 reg = ioread32(addr); in aspeed_sgpio_set_type()
375 reg = (reg & ~bit) | type1; in aspeed_sgpio_set_type()
376 iowrite32(reg, addr); in aspeed_sgpio_set_type()
379 reg = ioread32(addr); in aspeed_sgpio_set_type()
380 reg = (reg & ~bit) | type2; in aspeed_sgpio_set_type()
381 iowrite32(reg, addr); in aspeed_sgpio_set_type()
383 spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_sgpio_set_type()
396 unsigned long reg; in aspeed_sgpio_irq_handler() local
403 reg = ioread32(bank_reg(data, bank, reg_irq_status)); in aspeed_sgpio_irq_handler()
405 for_each_set_bit(p, ®, 32) { in aspeed_sgpio_irq_handler()
406 girq = irq_find_mapping(gc->irq.domain, i * 32 + p); in aspeed_sgpio_irq_handler()
416 .name = "aspeed-sgpio",
434 gpio->irq = rc; in aspeed_sgpio_setup_irqs()
445 irq = &gpio->chip.irq; in aspeed_sgpio_setup_irqs()
446 irq->chip = &aspeed_sgpio_irqchip; in aspeed_sgpio_setup_irqs()
447 irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask; in aspeed_sgpio_setup_irqs()
448 irq->handler = handle_bad_irq; in aspeed_sgpio_setup_irqs()
449 irq->default_type = IRQ_TYPE_NONE; in aspeed_sgpio_setup_irqs()
450 irq->parent_handler = aspeed_sgpio_irq_handler; in aspeed_sgpio_setup_irqs()
451 irq->parent_handler_data = gpio; in aspeed_sgpio_setup_irqs()
452 irq->parents = &gpio->irq; in aspeed_sgpio_setup_irqs()
453 irq->num_parents = 1; in aspeed_sgpio_setup_irqs()
458 /* set falling or level-low irq */ in aspeed_sgpio_setup_irqs()
470 { .compatible = "aspeed,ast2400-sgpio" },
471 { .compatible = "aspeed,ast2500-sgpio" },
484 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in aspeed_sgpio_probe()
486 return -ENOMEM; in aspeed_sgpio_probe()
488 gpio->base = devm_platform_ioremap_resource(pdev, 0); in aspeed_sgpio_probe()
489 if (IS_ERR(gpio->base)) in aspeed_sgpio_probe()
490 return PTR_ERR(gpio->base); in aspeed_sgpio_probe()
492 rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios); in aspeed_sgpio_probe()
494 dev_err(&pdev->dev, "Could not read ngpios property\n"); in aspeed_sgpio_probe()
495 return -EINVAL; in aspeed_sgpio_probe()
497 dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n", in aspeed_sgpio_probe()
499 return -EINVAL; in aspeed_sgpio_probe()
501 gpio->n_sgpio = nr_gpios; in aspeed_sgpio_probe()
503 rc = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &sgpio_freq); in aspeed_sgpio_probe()
505 dev_err(&pdev->dev, "Could not read bus-frequency property\n"); in aspeed_sgpio_probe()
506 return -EINVAL; in aspeed_sgpio_probe()
509 gpio->pclk = devm_clk_get(&pdev->dev, NULL); in aspeed_sgpio_probe()
510 if (IS_ERR(gpio->pclk)) { in aspeed_sgpio_probe()
511 dev_err(&pdev->dev, "devm_clk_get failed\n"); in aspeed_sgpio_probe()
512 return PTR_ERR(gpio->pclk); in aspeed_sgpio_probe()
515 apb_freq = clk_get_rate(gpio->pclk); in aspeed_sgpio_probe()
524 * GPIO254[31:16] = PCLK / (frequency * 2) - 1 in aspeed_sgpio_probe()
527 return -EINVAL; in aspeed_sgpio_probe()
529 sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1; in aspeed_sgpio_probe()
531 if (sgpio_clk_div > (1 << 16) - 1) in aspeed_sgpio_probe()
532 return -EINVAL; in aspeed_sgpio_probe()
537 gpio->base + ASPEED_SGPIO_CTRL); in aspeed_sgpio_probe()
539 spin_lock_init(&gpio->lock); in aspeed_sgpio_probe()
541 gpio->chip.parent = &pdev->dev; in aspeed_sgpio_probe()
542 gpio->chip.ngpio = MAX_NR_HW_SGPIO * 2; in aspeed_sgpio_probe()
543 gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask; in aspeed_sgpio_probe()
544 gpio->chip.direction_input = aspeed_sgpio_dir_in; in aspeed_sgpio_probe()
545 gpio->chip.direction_output = aspeed_sgpio_dir_out; in aspeed_sgpio_probe()
546 gpio->chip.get_direction = aspeed_sgpio_get_direction; in aspeed_sgpio_probe()
547 gpio->chip.request = NULL; in aspeed_sgpio_probe()
548 gpio->chip.free = NULL; in aspeed_sgpio_probe()
549 gpio->chip.get = aspeed_sgpio_get; in aspeed_sgpio_probe()
550 gpio->chip.set = aspeed_sgpio_set; in aspeed_sgpio_probe()
551 gpio->chip.set_config = NULL; in aspeed_sgpio_probe()
552 gpio->chip.label = dev_name(&pdev->dev); in aspeed_sgpio_probe()
553 gpio->chip.base = -1; in aspeed_sgpio_probe()
557 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); in aspeed_sgpio_probe()