Lines Matching +full:gpio +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/gpio/driver.h>
25 #include <linux/platform_data/gpio-dwapb.h>
29 #include "gpiolib-acpi.h"
51 #define DWAPB_DRIVER_NAME "gpio-dwapb"
71 /* Store GPIO context across system-wide suspend/resume transitions */
94 struct dwapb_gpio *gpio; member
101 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
131 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset) in gpio_reg_convert() argument
133 if (gpio->flags & GPIO_REG_OFFSET_V2) in gpio_reg_convert()
139 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) in dwapb_read() argument
141 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_read()
142 void __iomem *reg_base = gpio->regs; in dwapb_read()
144 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); in dwapb_read()
147 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, in dwapb_write() argument
150 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_write()
151 void __iomem *reg_base = gpio->regs; in dwapb_write()
153 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); in dwapb_write()
156 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs) in dwapb_offs_to_port() argument
161 for (i = 0; i < gpio->nr_ports; i++) { in dwapb_offs_to_port()
162 port = &gpio->ports[i]; in dwapb_offs_to_port()
163 if (port->idx == offs / DWAPB_MAX_GPIOS) in dwapb_offs_to_port()
170 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs) in dwapb_toggle_trigger() argument
172 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs); in dwapb_toggle_trigger()
179 gc = &port->gc; in dwapb_toggle_trigger()
181 pol = dwapb_read(gpio, GPIO_INT_POLARITY); in dwapb_toggle_trigger()
183 val = gc->get(gc, offs % DWAPB_MAX_GPIOS); in dwapb_toggle_trigger()
189 dwapb_write(gpio, GPIO_INT_POLARITY, pol); in dwapb_toggle_trigger()
192 static u32 dwapb_do_irq(struct dwapb_gpio *gpio) in dwapb_do_irq() argument
194 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_do_irq()
198 irq_status = dwapb_read(gpio, GPIO_INTSTATUS); in dwapb_do_irq()
200 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq); in dwapb_do_irq()
206 dwapb_toggle_trigger(gpio, hwirq); in dwapb_do_irq()
214 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc); in dwapb_irq_handler() local
218 dwapb_do_irq(gpio); in dwapb_irq_handler()
230 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); in dwapb_irq_ack() local
234 spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_irq_ack()
235 dwapb_write(gpio, GPIO_PORTA_EOI, val); in dwapb_irq_ack()
236 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_irq_ack()
242 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); in dwapb_irq_mask() local
246 spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_irq_mask()
247 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d)); in dwapb_irq_mask()
248 dwapb_write(gpio, GPIO_INTMASK, val); in dwapb_irq_mask()
249 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_irq_mask()
255 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); in dwapb_irq_unmask() local
259 spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_irq_unmask()
260 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d)); in dwapb_irq_unmask()
261 dwapb_write(gpio, GPIO_INTMASK, val); in dwapb_irq_unmask()
262 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_irq_unmask()
268 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); in dwapb_irq_enable() local
272 spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_irq_enable()
273 val = dwapb_read(gpio, GPIO_INTEN); in dwapb_irq_enable()
275 dwapb_write(gpio, GPIO_INTEN, val); in dwapb_irq_enable()
276 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_irq_enable()
282 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); in dwapb_irq_disable() local
286 spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_irq_disable()
287 val = dwapb_read(gpio, GPIO_INTEN); in dwapb_irq_disable()
289 dwapb_write(gpio, GPIO_INTEN, val); in dwapb_irq_disable()
290 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_irq_disable()
296 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); in dwapb_irq_set_type() local
301 return -EINVAL; in dwapb_irq_set_type()
303 spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_irq_set_type()
304 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); in dwapb_irq_set_type()
305 polarity = dwapb_read(gpio, GPIO_INT_POLARITY); in dwapb_irq_set_type()
310 dwapb_toggle_trigger(gpio, bit); in dwapb_irq_set_type()
335 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); in dwapb_irq_set_type()
337 dwapb_write(gpio, GPIO_INT_POLARITY, polarity); in dwapb_irq_set_type()
338 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_irq_set_type()
347 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); in dwapb_irq_set_wake() local
348 struct dwapb_context *ctx = gpio->ports[0].ctx; in dwapb_irq_set_wake()
352 ctx->wake_en |= BIT(bit); in dwapb_irq_set_wake()
354 ctx->wake_en &= ~BIT(bit); in dwapb_irq_set_wake()
364 struct dwapb_gpio *gpio = port->gpio; in dwapb_gpio_set_debounce() local
368 spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_gpio_set_debounce()
370 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); in dwapb_gpio_set_debounce()
375 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb); in dwapb_gpio_set_debounce()
377 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_gpio_set_debounce()
388 return -ENOTSUPP; in dwapb_gpio_set_config()
400 for (i = 0; i < pp->ngpio; ++i) { in dwapb_convert_irqs()
401 if (!pp->irq[i]) in dwapb_convert_irqs()
404 pirq->irq[pirq->nr_irqs++] = pp->irq[i]; in dwapb_convert_irqs()
407 return pirq->nr_irqs ? 0 : -ENOENT; in dwapb_convert_irqs()
410 static void dwapb_configure_irqs(struct dwapb_gpio *gpio, in dwapb_configure_irqs() argument
415 struct gpio_chip *gc = &port->gc; in dwapb_configure_irqs()
419 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL); in dwapb_configure_irqs()
424 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx); in dwapb_configure_irqs()
428 girq = &gc->irq; in dwapb_configure_irqs()
429 girq->handler = handle_bad_irq; in dwapb_configure_irqs()
430 girq->default_type = IRQ_TYPE_NONE; in dwapb_configure_irqs()
432 port->pirq = pirq; in dwapb_configure_irqs()
433 pirq->irqchip.name = DWAPB_DRIVER_NAME; in dwapb_configure_irqs()
434 pirq->irqchip.irq_ack = dwapb_irq_ack; in dwapb_configure_irqs()
435 pirq->irqchip.irq_mask = dwapb_irq_mask; in dwapb_configure_irqs()
436 pirq->irqchip.irq_unmask = dwapb_irq_unmask; in dwapb_configure_irqs()
437 pirq->irqchip.irq_set_type = dwapb_irq_set_type; in dwapb_configure_irqs()
438 pirq->irqchip.irq_enable = dwapb_irq_enable; in dwapb_configure_irqs()
439 pirq->irqchip.irq_disable = dwapb_irq_disable; in dwapb_configure_irqs()
441 pirq->irqchip.irq_set_wake = dwapb_irq_set_wake; in dwapb_configure_irqs()
444 if (!pp->irq_shared) { in dwapb_configure_irqs()
445 girq->num_parents = pirq->nr_irqs; in dwapb_configure_irqs()
446 girq->parents = pirq->irq; in dwapb_configure_irqs()
447 girq->parent_handler_data = gpio; in dwapb_configure_irqs()
448 girq->parent_handler = dwapb_irq_handler; in dwapb_configure_irqs()
451 girq->num_parents = 0; in dwapb_configure_irqs()
452 girq->parents = NULL; in dwapb_configure_irqs()
453 girq->parent_handler = NULL; in dwapb_configure_irqs()
459 err = devm_request_irq(gpio->dev, pp->irq[0], in dwapb_configure_irqs()
461 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio); in dwapb_configure_irqs()
463 dev_err(gpio->dev, "error requesting IRQ\n"); in dwapb_configure_irqs()
468 girq->chip = &pirq->irqchip; in dwapb_configure_irqs()
473 devm_kfree(gpio->dev, pirq); in dwapb_configure_irqs()
476 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, in dwapb_gpio_add_port() argument
484 port = &gpio->ports[offs]; in dwapb_gpio_add_port()
485 port->gpio = gpio; in dwapb_gpio_add_port()
486 port->idx = pp->idx; in dwapb_gpio_add_port()
489 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); in dwapb_gpio_add_port()
490 if (!port->ctx) in dwapb_gpio_add_port()
491 return -ENOMEM; in dwapb_gpio_add_port()
494 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE; in dwapb_gpio_add_port()
495 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE; in dwapb_gpio_add_port()
496 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE; in dwapb_gpio_add_port()
498 /* This registers 32 GPIO lines per port */ in dwapb_gpio_add_port()
499 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, in dwapb_gpio_add_port()
502 dev_err(gpio->dev, "failed to init gpio chip for port%d\n", in dwapb_gpio_add_port()
503 port->idx); in dwapb_gpio_add_port()
508 port->gc.of_node = to_of_node(pp->fwnode); in dwapb_gpio_add_port()
510 port->gc.ngpio = pp->ngpio; in dwapb_gpio_add_port()
511 port->gc.base = pp->gpio_base; in dwapb_gpio_add_port()
514 if (pp->idx == 0) in dwapb_gpio_add_port()
515 port->gc.set_config = dwapb_gpio_set_config; in dwapb_gpio_add_port()
518 if (pp->idx == 0) in dwapb_gpio_add_port()
519 dwapb_configure_irqs(gpio, port, pp); in dwapb_gpio_add_port()
521 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port); in dwapb_gpio_add_port()
523 dev_err(gpio->dev, "failed to register gpiochip for port%d\n", in dwapb_gpio_add_port()
524 port->idx); in dwapb_gpio_add_port()
535 int irq = -ENXIO, j; in dwapb_get_irq()
537 if (fwnode_property_read_bool(fwnode, "interrupt-controller")) in dwapb_get_irq()
540 for (j = 0; j < pp->ngpio; j++) { in dwapb_get_irq()
546 pp->irq[j] = irq; in dwapb_get_irq()
560 return ERR_PTR(-ENODEV); in dwapb_gpio_get_pdata()
564 return ERR_PTR(-ENOMEM); in dwapb_gpio_get_pdata()
566 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL); in dwapb_gpio_get_pdata()
567 if (!pdata->properties) in dwapb_gpio_get_pdata()
568 return ERR_PTR(-ENOMEM); in dwapb_gpio_get_pdata()
570 pdata->nports = nports; in dwapb_gpio_get_pdata()
574 pp = &pdata->properties[i++]; in dwapb_gpio_get_pdata()
575 pp->fwnode = fwnode; in dwapb_gpio_get_pdata()
577 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) || in dwapb_gpio_get_pdata()
578 pp->idx >= DWAPB_MAX_PORTS) { in dwapb_gpio_get_pdata()
582 return ERR_PTR(-EINVAL); in dwapb_gpio_get_pdata()
585 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) && in dwapb_gpio_get_pdata()
586 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) { in dwapb_gpio_get_pdata()
590 pp->ngpio = DWAPB_MAX_GPIOS; in dwapb_gpio_get_pdata()
593 pp->irq_shared = false; in dwapb_gpio_get_pdata()
594 pp->gpio_base = -1; in dwapb_gpio_get_pdata()
600 if (pp->idx == 0) in dwapb_gpio_get_pdata()
609 struct dwapb_gpio *gpio = data; in dwapb_assert_reset() local
611 reset_control_assert(gpio->rst); in dwapb_assert_reset()
614 static int dwapb_get_reset(struct dwapb_gpio *gpio) in dwapb_get_reset() argument
618 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL); in dwapb_get_reset()
619 if (IS_ERR(gpio->rst)) { in dwapb_get_reset()
620 dev_err(gpio->dev, "Cannot get reset descriptor\n"); in dwapb_get_reset()
621 return PTR_ERR(gpio->rst); in dwapb_get_reset()
624 err = reset_control_deassert(gpio->rst); in dwapb_get_reset()
626 dev_err(gpio->dev, "Cannot deassert reset lane\n"); in dwapb_get_reset()
630 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio); in dwapb_get_reset()
635 struct dwapb_gpio *gpio = data; in dwapb_disable_clks() local
637 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); in dwapb_disable_clks()
640 static int dwapb_get_clks(struct dwapb_gpio *gpio) in dwapb_get_clks() argument
645 gpio->clks[0].id = "bus"; in dwapb_get_clks()
646 gpio->clks[1].id = "db"; in dwapb_get_clks()
647 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS, in dwapb_get_clks()
648 gpio->clks); in dwapb_get_clks()
650 dev_err(gpio->dev, "Cannot get APB/Debounce clocks\n"); in dwapb_get_clks()
654 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); in dwapb_get_clks()
656 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n"); in dwapb_get_clks()
660 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio); in dwapb_get_clks()
664 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
665 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
681 struct dwapb_gpio *gpio; in dwapb_gpio_probe() local
683 struct device *dev = &pdev->dev; in dwapb_gpio_probe()
692 if (!pdata->nports) in dwapb_gpio_probe()
693 return -ENODEV; in dwapb_gpio_probe()
695 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in dwapb_gpio_probe()
696 if (!gpio) in dwapb_gpio_probe()
697 return -ENOMEM; in dwapb_gpio_probe()
699 gpio->dev = &pdev->dev; in dwapb_gpio_probe()
700 gpio->nr_ports = pdata->nports; in dwapb_gpio_probe()
702 err = dwapb_get_reset(gpio); in dwapb_gpio_probe()
706 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, in dwapb_gpio_probe()
707 sizeof(*gpio->ports), GFP_KERNEL); in dwapb_gpio_probe()
708 if (!gpio->ports) in dwapb_gpio_probe()
709 return -ENOMEM; in dwapb_gpio_probe()
711 gpio->regs = devm_platform_ioremap_resource(pdev, 0); in dwapb_gpio_probe()
712 if (IS_ERR(gpio->regs)) in dwapb_gpio_probe()
713 return PTR_ERR(gpio->regs); in dwapb_gpio_probe()
715 err = dwapb_get_clks(gpio); in dwapb_gpio_probe()
719 gpio->flags = (uintptr_t)device_get_match_data(dev); in dwapb_gpio_probe()
721 for (i = 0; i < gpio->nr_ports; i++) { in dwapb_gpio_probe()
722 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); in dwapb_gpio_probe()
727 platform_set_drvdata(pdev, gpio); in dwapb_gpio_probe()
735 struct dwapb_gpio *gpio = dev_get_drvdata(dev); in dwapb_gpio_suspend() local
736 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_gpio_suspend()
740 spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_gpio_suspend()
741 for (i = 0; i < gpio->nr_ports; i++) { in dwapb_gpio_suspend()
743 unsigned int idx = gpio->ports[i].idx; in dwapb_gpio_suspend()
744 struct dwapb_context *ctx = gpio->ports[i].ctx; in dwapb_gpio_suspend()
747 ctx->dir = dwapb_read(gpio, offset); in dwapb_gpio_suspend()
750 ctx->data = dwapb_read(gpio, offset); in dwapb_gpio_suspend()
753 ctx->ext = dwapb_read(gpio, offset); in dwapb_gpio_suspend()
757 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); in dwapb_gpio_suspend()
758 ctx->int_en = dwapb_read(gpio, GPIO_INTEN); in dwapb_gpio_suspend()
759 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); in dwapb_gpio_suspend()
760 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); in dwapb_gpio_suspend()
761 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); in dwapb_gpio_suspend()
764 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); in dwapb_gpio_suspend()
767 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_gpio_suspend()
769 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); in dwapb_gpio_suspend()
776 struct dwapb_gpio *gpio = dev_get_drvdata(dev); in dwapb_gpio_resume() local
777 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_gpio_resume()
781 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); in dwapb_gpio_resume()
783 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n"); in dwapb_gpio_resume()
787 spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_gpio_resume()
788 for (i = 0; i < gpio->nr_ports; i++) { in dwapb_gpio_resume()
790 unsigned int idx = gpio->ports[i].idx; in dwapb_gpio_resume()
791 struct dwapb_context *ctx = gpio->ports[i].ctx; in dwapb_gpio_resume()
794 dwapb_write(gpio, offset, ctx->data); in dwapb_gpio_resume()
797 dwapb_write(gpio, offset, ctx->dir); in dwapb_gpio_resume()
800 dwapb_write(gpio, offset, ctx->ext); in dwapb_gpio_resume()
804 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); in dwapb_gpio_resume()
805 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); in dwapb_gpio_resume()
806 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); in dwapb_gpio_resume()
807 dwapb_write(gpio, GPIO_INTEN, ctx->int_en); in dwapb_gpio_resume()
808 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); in dwapb_gpio_resume()
811 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); in dwapb_gpio_resume()
814 spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_gpio_resume()
837 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");