Lines Matching +full:vref +full:- +full:source
1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
15 #include <linux/nvmem-consumer.h>
96 (8 + (((_chan) - 2) * 3))
153 * and u-boot source served as reference). These only seem to be relevant on
269 struct regulator *vref; member
306 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); in meson_sar_adc_get_fifo_count()
317 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias; in meson_sar_adc_calib_val()
319 return clamp(tmp, 0, (1 << priv->param->resolution) - 1); in meson_sar_adc_calib_val()
334 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); in meson_sar_adc_wait_busy_clear()
335 } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--); in meson_sar_adc_wait_busy_clear()
338 return -ETIMEDOUT; in meson_sar_adc_wait_busy_clear()
350 if(!wait_for_completion_timeout(&priv->done, in meson_sar_adc_read_raw_sample()
352 return -ETIMEDOUT; in meson_sar_adc_read_raw_sample()
356 dev_err(&indio_dev->dev, in meson_sar_adc_read_raw_sample()
358 return -EINVAL; in meson_sar_adc_read_raw_sample()
361 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val); in meson_sar_adc_read_raw_sample()
363 if (fifo_chan != chan->address) { in meson_sar_adc_read_raw_sample()
364 dev_err(&indio_dev->dev, in meson_sar_adc_read_raw_sample()
366 fifo_chan, chan->address); in meson_sar_adc_read_raw_sample()
367 return -EINVAL; in meson_sar_adc_read_raw_sample()
371 fifo_val &= GENMASK(priv->param->resolution - 1, 0); in meson_sar_adc_read_raw_sample()
383 int val, address = chan->address; in meson_sar_adc_set_averaging()
386 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, in meson_sar_adc_set_averaging()
391 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, in meson_sar_adc_set_averaging()
407 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, in meson_sar_adc_enable_channel()
412 chan->address); in meson_sar_adc_enable_channel()
413 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, in meson_sar_adc_enable_channel()
417 chan->address); in meson_sar_adc_enable_channel()
418 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, in meson_sar_adc_enable_channel()
423 chan->address); in meson_sar_adc_enable_channel()
424 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, in meson_sar_adc_enable_channel()
428 if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) { in meson_sar_adc_enable_channel()
429 if (chan->type == IIO_TEMP) in meson_sar_adc_enable_channel()
434 regmap_update_bits(priv->regmap, in meson_sar_adc_enable_channel()
447 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_set_chan7_mux()
457 reinit_completion(&priv->done); in meson_sar_adc_start_sample_engine()
459 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_start_sample_engine()
463 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_start_sample_engine()
467 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_start_sample_engine()
476 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_stop_sample_engine()
479 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_stop_sample_engine()
486 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_stop_sample_engine()
495 mutex_lock(&indio_dev->mlock); in meson_sar_adc_lock()
497 if (priv->param->has_bl30_integration) { in meson_sar_adc_lock()
499 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_lock()
509 regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val); in meson_sar_adc_lock()
510 } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--); in meson_sar_adc_lock()
513 mutex_unlock(&indio_dev->mlock); in meson_sar_adc_lock()
514 return -ETIMEDOUT; in meson_sar_adc_lock()
525 if (priv->param->has_bl30_integration) in meson_sar_adc_unlock()
527 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_unlock()
530 mutex_unlock(&indio_dev->mlock); in meson_sar_adc_unlock()
542 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp); in meson_sar_adc_clear_fifo()
555 if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated) in meson_sar_adc_get_sample()
556 return -ENOTSUPP; in meson_sar_adc_get_sample()
576 dev_warn(indio_dev->dev.parent, in meson_sar_adc_get_sample()
578 chan->address, ret); in meson_sar_adc_get_sample()
605 if (chan->type == IIO_VOLTAGE) { in meson_sar_adc_iio_info_read_raw()
606 ret = regulator_get_voltage(priv->vref); in meson_sar_adc_iio_info_read_raw()
608 dev_err(indio_dev->dev.parent, in meson_sar_adc_iio_info_read_raw()
609 "failed to get vref voltage: %d\n", in meson_sar_adc_iio_info_read_raw()
615 *val2 = priv->param->resolution; in meson_sar_adc_iio_info_read_raw()
617 } else if (chan->type == IIO_TEMP) { in meson_sar_adc_iio_info_read_raw()
619 *val = priv->param->temperature_multiplier; in meson_sar_adc_iio_info_read_raw()
620 *val2 = priv->param->temperature_divider; in meson_sar_adc_iio_info_read_raw()
627 return -EINVAL; in meson_sar_adc_iio_info_read_raw()
631 *val = priv->calibbias; in meson_sar_adc_iio_info_read_raw()
635 *val = priv->calibscale / MILLION; in meson_sar_adc_iio_info_read_raw()
636 *val2 = priv->calibscale % MILLION; in meson_sar_adc_iio_info_read_raw()
641 priv->param->temperature_divider, in meson_sar_adc_iio_info_read_raw()
642 priv->param->temperature_multiplier); in meson_sar_adc_iio_info_read_raw()
643 *val -= priv->temperature_sensor_adc_val; in meson_sar_adc_iio_info_read_raw()
647 return -EINVAL; in meson_sar_adc_iio_info_read_raw()
658 init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div", in meson_sar_adc_clk_init()
659 dev_name(indio_dev->dev.parent)); in meson_sar_adc_clk_init()
661 return -ENOMEM; in meson_sar_adc_clk_init()
665 clk_parents[0] = __clk_get_name(priv->clkin); in meson_sar_adc_clk_init()
669 priv->clk_div.reg = base + MESON_SAR_ADC_REG3; in meson_sar_adc_clk_init()
670 priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT; in meson_sar_adc_clk_init()
671 priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH; in meson_sar_adc_clk_init()
672 priv->clk_div.hw.init = &init; in meson_sar_adc_clk_init()
673 priv->clk_div.flags = 0; in meson_sar_adc_clk_init()
675 priv->adc_div_clk = devm_clk_register(&indio_dev->dev, in meson_sar_adc_clk_init()
676 &priv->clk_div.hw); in meson_sar_adc_clk_init()
677 if (WARN_ON(IS_ERR(priv->adc_div_clk))) in meson_sar_adc_clk_init()
678 return PTR_ERR(priv->adc_div_clk); in meson_sar_adc_clk_init()
680 init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en", in meson_sar_adc_clk_init()
681 dev_name(indio_dev->dev.parent)); in meson_sar_adc_clk_init()
683 return -ENOMEM; in meson_sar_adc_clk_init()
687 clk_parents[0] = __clk_get_name(priv->adc_div_clk); in meson_sar_adc_clk_init()
691 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3; in meson_sar_adc_clk_init()
692 priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN); in meson_sar_adc_clk_init()
693 priv->clk_gate.hw.init = &init; in meson_sar_adc_clk_init()
695 priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw); in meson_sar_adc_clk_init()
696 if (WARN_ON(IS_ERR(priv->adc_clk))) in meson_sar_adc_clk_init()
697 return PTR_ERR(priv->adc_clk); in meson_sar_adc_clk_init()
710 temperature_calib = devm_nvmem_cell_get(indio_dev->dev.parent, in meson_sar_adc_temp_sensor_init()
717 * was passed via nvmem-cells. in meson_sar_adc_temp_sensor_init()
719 if (ret == -ENODEV) in meson_sar_adc_temp_sensor_init()
722 return dev_err_probe(indio_dev->dev.parent, ret, in meson_sar_adc_temp_sensor_init()
726 priv->tsc_regmap = in meson_sar_adc_temp_sensor_init()
727 syscon_regmap_lookup_by_phandle(indio_dev->dev.parent->of_node, in meson_sar_adc_temp_sensor_init()
728 "amlogic,hhi-sysctrl"); in meson_sar_adc_temp_sensor_init()
729 if (IS_ERR(priv->tsc_regmap)) { in meson_sar_adc_temp_sensor_init()
730 dev_err(indio_dev->dev.parent, in meson_sar_adc_temp_sensor_init()
731 "failed to get amlogic,hhi-sysctrl regmap\n"); in meson_sar_adc_temp_sensor_init()
732 return PTR_ERR(priv->tsc_regmap); in meson_sar_adc_temp_sensor_init()
738 dev_err(indio_dev->dev.parent, in meson_sar_adc_temp_sensor_init()
743 dev_err(indio_dev->dev.parent, in meson_sar_adc_temp_sensor_init()
745 return -EINVAL; in meson_sar_adc_temp_sensor_init()
748 trimming_bits = priv->param->temperature_trimming_bits; in meson_sar_adc_temp_sensor_init()
749 trimming_mask = BIT(trimming_bits) - 1; in meson_sar_adc_temp_sensor_init()
751 priv->temperature_sensor_calibrated = in meson_sar_adc_temp_sensor_init()
753 priv->temperature_sensor_coefficient = buf[2] & trimming_mask; in meson_sar_adc_temp_sensor_init()
758 priv->temperature_sensor_adc_val = buf[2]; in meson_sar_adc_temp_sensor_init()
759 priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE; in meson_sar_adc_temp_sensor_init()
760 priv->temperature_sensor_adc_val >>= trimming_bits; in meson_sar_adc_temp_sensor_init()
778 if (priv->param->has_bl30_integration) { in meson_sar_adc_init()
784 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val); in meson_sar_adc_init()
795 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_init()
799 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0); in meson_sar_adc_init()
801 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_init()
803 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_init()
808 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
812 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
818 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
822 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
832 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
836 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
851 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval); in meson_sar_adc_init()
853 if (priv->temperature_sensor_calibrated) { in meson_sar_adc_init()
854 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
857 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
866 priv->temperature_sensor_coefficient); in meson_sar_adc_init()
867 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
870 if (priv->param->temperature_trimming_bits == 5) { in meson_sar_adc_init()
871 if (priv->temperature_sensor_coefficient & BIT(4)) in meson_sar_adc_init()
880 regmap_update_bits(priv->tsc_regmap, in meson_sar_adc_init()
886 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
888 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
892 ret = clk_set_parent(priv->adc_sel_clk, priv->clkin); in meson_sar_adc_init()
894 dev_err(indio_dev->dev.parent, in meson_sar_adc_init()
899 ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate); in meson_sar_adc_init()
901 dev_err(indio_dev->dev.parent, in meson_sar_adc_init()
912 const struct meson_sar_adc_param *param = priv->param; in meson_sar_adc_set_bandgap()
915 if (param->bandgap_reg == MESON_SAR_ADC_REG11) in meson_sar_adc_set_bandgap()
920 regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask, in meson_sar_adc_set_bandgap()
934 ret = regulator_enable(priv->vref); in meson_sar_adc_hw_enable()
936 dev_err(indio_dev->dev.parent, in meson_sar_adc_hw_enable()
937 "failed to enable vref regulator\n"); in meson_sar_adc_hw_enable()
941 ret = clk_prepare_enable(priv->core_clk); in meson_sar_adc_hw_enable()
943 dev_err(indio_dev->dev.parent, "failed to enable core clk\n"); in meson_sar_adc_hw_enable()
948 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_hw_enable()
953 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_hw_enable()
959 ret = clk_prepare_enable(priv->adc_clk); in meson_sar_adc_hw_enable()
961 dev_err(indio_dev->dev.parent, "failed to enable adc clk\n"); in meson_sar_adc_hw_enable()
970 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_hw_enable()
973 clk_disable_unprepare(priv->core_clk); in meson_sar_adc_hw_enable()
975 regulator_disable(priv->vref); in meson_sar_adc_hw_enable()
991 clk_disable_unprepare(priv->adc_clk); in meson_sar_adc_hw_disable()
993 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_hw_disable()
998 clk_disable_unprepare(priv->core_clk); in meson_sar_adc_hw_disable()
1000 regulator_disable(priv->vref); in meson_sar_adc_hw_disable()
1014 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); in meson_sar_adc_irq()
1021 complete(&priv->done); in meson_sar_adc_irq()
1032 nominal0 = (1 << priv->param->resolution) / 4; in meson_sar_adc_calib()
1033 nominal1 = (1 << priv->param->resolution) * 3 / 4; in meson_sar_adc_calib()
1038 &indio_dev->channels[7], in meson_sar_adc_calib()
1046 &indio_dev->channels[7], in meson_sar_adc_calib()
1052 ret = -EINVAL; in meson_sar_adc_calib()
1056 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION, in meson_sar_adc_calib()
1057 value1 - value0); in meson_sar_adc_calib()
1058 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale, in meson_sar_adc_calib()
1111 .name = "meson-meson8-saradc",
1116 .name = "meson-meson8b-saradc",
1121 .name = "meson-meson8m2-saradc",
1126 .name = "meson-gxbb-saradc",
1131 .name = "meson-gxl-saradc",
1136 .name = "meson-gxm-saradc",
1141 .name = "meson-axg-saradc",
1146 .name = "meson-g12a-saradc",
1151 .compatible = "amlogic,meson8-saradc",
1154 .compatible = "amlogic,meson8b-saradc",
1157 .compatible = "amlogic,meson8m2-saradc",
1160 .compatible = "amlogic,meson-gxbb-saradc",
1163 .compatible = "amlogic,meson-gxl-saradc",
1166 .compatible = "amlogic,meson-gxm-saradc",
1169 .compatible = "amlogic,meson-axg-saradc",
1172 .compatible = "amlogic,meson-g12a-saradc",
1187 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv)); in meson_sar_adc_probe()
1189 dev_err(&pdev->dev, "failed allocating iio device\n"); in meson_sar_adc_probe()
1190 return -ENOMEM; in meson_sar_adc_probe()
1194 init_completion(&priv->done); in meson_sar_adc_probe()
1196 match_data = of_device_get_match_data(&pdev->dev); in meson_sar_adc_probe()
1198 dev_err(&pdev->dev, "failed to get match data\n"); in meson_sar_adc_probe()
1199 return -ENODEV; in meson_sar_adc_probe()
1202 priv->param = match_data->param; in meson_sar_adc_probe()
1204 indio_dev->name = match_data->name; in meson_sar_adc_probe()
1205 indio_dev->modes = INDIO_DIRECT_MODE; in meson_sar_adc_probe()
1206 indio_dev->info = &meson_sar_adc_iio_info; in meson_sar_adc_probe()
1212 priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, in meson_sar_adc_probe()
1213 priv->param->regmap_config); in meson_sar_adc_probe()
1214 if (IS_ERR(priv->regmap)) in meson_sar_adc_probe()
1215 return PTR_ERR(priv->regmap); in meson_sar_adc_probe()
1217 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); in meson_sar_adc_probe()
1219 return -EINVAL; in meson_sar_adc_probe()
1221 ret = devm_request_irq(&pdev->dev, irq, meson_sar_adc_irq, IRQF_SHARED, in meson_sar_adc_probe()
1222 dev_name(&pdev->dev), indio_dev); in meson_sar_adc_probe()
1226 priv->clkin = devm_clk_get(&pdev->dev, "clkin"); in meson_sar_adc_probe()
1227 if (IS_ERR(priv->clkin)) { in meson_sar_adc_probe()
1228 dev_err(&pdev->dev, "failed to get clkin\n"); in meson_sar_adc_probe()
1229 return PTR_ERR(priv->clkin); in meson_sar_adc_probe()
1232 priv->core_clk = devm_clk_get(&pdev->dev, "core"); in meson_sar_adc_probe()
1233 if (IS_ERR(priv->core_clk)) { in meson_sar_adc_probe()
1234 dev_err(&pdev->dev, "failed to get core clk\n"); in meson_sar_adc_probe()
1235 return PTR_ERR(priv->core_clk); in meson_sar_adc_probe()
1238 priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk"); in meson_sar_adc_probe()
1239 if (IS_ERR(priv->adc_clk)) { in meson_sar_adc_probe()
1240 if (PTR_ERR(priv->adc_clk) == -ENOENT) { in meson_sar_adc_probe()
1241 priv->adc_clk = NULL; in meson_sar_adc_probe()
1243 dev_err(&pdev->dev, "failed to get adc clk\n"); in meson_sar_adc_probe()
1244 return PTR_ERR(priv->adc_clk); in meson_sar_adc_probe()
1248 priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel"); in meson_sar_adc_probe()
1249 if (IS_ERR(priv->adc_sel_clk)) { in meson_sar_adc_probe()
1250 if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) { in meson_sar_adc_probe()
1251 priv->adc_sel_clk = NULL; in meson_sar_adc_probe()
1253 dev_err(&pdev->dev, "failed to get adc_sel clk\n"); in meson_sar_adc_probe()
1254 return PTR_ERR(priv->adc_sel_clk); in meson_sar_adc_probe()
1258 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */ in meson_sar_adc_probe()
1259 if (!priv->adc_clk) { in meson_sar_adc_probe()
1265 priv->vref = devm_regulator_get(&pdev->dev, "vref"); in meson_sar_adc_probe()
1266 if (IS_ERR(priv->vref)) { in meson_sar_adc_probe()
1267 dev_err(&pdev->dev, "failed to get vref regulator\n"); in meson_sar_adc_probe()
1268 return PTR_ERR(priv->vref); in meson_sar_adc_probe()
1271 priv->calibscale = MILLION; in meson_sar_adc_probe()
1273 if (priv->param->temperature_trimming_bits) { in meson_sar_adc_probe()
1279 if (priv->temperature_sensor_calibrated) { in meson_sar_adc_probe()
1280 indio_dev->channels = meson_sar_adc_and_temp_iio_channels; in meson_sar_adc_probe()
1281 indio_dev->num_channels = in meson_sar_adc_probe()
1284 indio_dev->channels = meson_sar_adc_iio_channels; in meson_sar_adc_probe()
1285 indio_dev->num_channels = in meson_sar_adc_probe()
1299 dev_warn(&pdev->dev, "calibration failed\n"); in meson_sar_adc_probe()
1345 .name = "meson-saradc",