Lines Matching +full:secure +full:- +full:reg +full:- +full:access
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
32 #include "irq-gic-common.h"
70 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
74 * When security is enabled, non-secure priority values from the (re)distributor
78 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
84 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
86 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
104 * When the Non-secure world has access to group 0 interrupts (as a
109 * written by software is moved to the Non-secure range by the Distributor.
132 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
170 return __get_intid_range(d->hwirq); in get_intid_range()
175 return d->hwirq; in gic_irq()
196 /* SGI+PPI -> SGI_base for this CPU */ in gic_dist_base()
201 /* SPI -> dist_base */ in gic_dist_base()
214 count--; in gic_do_wait_for_rwp()
272 while (--count) { in gic_enable_redist()
293 *index = d->hwirq; in convert_offset_index()
301 *index = d->hwirq - EPPI_BASE_INTID + 32; in convert_offset_index()
304 *index = d->hwirq - ESPI_BASE_INTID; in convert_offset_index()
333 *index = d->hwirq; in convert_offset_index()
408 u32 reg; in gic_irq_set_irqchip_state() local
410 if (d->hwirq >= 8192) /* SGI/PPI/SPI only */ in gic_irq_set_irqchip_state()
411 return -EINVAL; in gic_irq_set_irqchip_state()
415 reg = val ? GICD_ISPENDR : GICD_ICPENDR; in gic_irq_set_irqchip_state()
419 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; in gic_irq_set_irqchip_state()
423 reg = val ? GICD_ICENABLER : GICD_ISENABLER; in gic_irq_set_irqchip_state()
427 return -EINVAL; in gic_irq_set_irqchip_state()
430 gic_poke_irq(d, reg); in gic_irq_set_irqchip_state()
437 if (d->hwirq >= 8192) /* PPI/SPI only */ in gic_irq_get_irqchip_state()
438 return -EINVAL; in gic_irq_get_irqchip_state()
454 return -EINVAL; in gic_irq_get_irqchip_state()
474 return d->hwirq - 16; in gic_get_ppi_index()
476 return d->hwirq - EPPI_BASE_INTID + 16; in gic_get_ppi_index()
484 struct irq_desc *desc = irq_to_desc(d->irq); in gic_irq_nmi_setup()
487 return -EINVAL; in gic_irq_nmi_setup()
490 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); in gic_irq_nmi_setup()
491 return -EINVAL; in gic_irq_nmi_setup()
499 return -EINVAL; in gic_irq_nmi_setup()
508 desc->handle_irq = handle_percpu_devid_fasteoi_nmi; in gic_irq_nmi_setup()
511 desc->handle_irq = handle_fasteoi_nmi; in gic_irq_nmi_setup()
521 struct irq_desc *desc = irq_to_desc(d->irq); in gic_irq_nmi_teardown()
527 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); in gic_irq_nmi_teardown()
544 desc->handle_irq = handle_percpu_devid_irq; in gic_irq_nmi_teardown()
546 desc->handle_irq = handle_fasteoi_irq; in gic_irq_nmi_teardown()
581 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; in gic_set_type()
586 return -EINVAL; in gic_set_type()
601 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); in gic_set_type()
611 return -EINVAL; in gic_irq_set_vcpu_affinity()
753 * setting the highest possible, non-zero priority in PMR. in gic_has_group0()
757 * actual priority in the non-secure range. In the process, it in gic_has_group0()
760 * we're don't have access to Group0. in gic_has_group0()
762 gic_write_pmr(BIT(8 - gic_get_pribits())); in gic_has_group0()
782 * Configure SPIs as non-secure Group-1. This will only matter in gic_dist_init()
784 * do the right thing if the kernel is running in secure mode, in gic_dist_init()
831 int ret = -ENODEV; in gic_iterate_rdists()
837 u32 reg; in gic_iterate_rdists() local
839 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; in gic_iterate_rdists()
840 if (reg != GIC_PIDR2_ARCH_GICv3 && in gic_iterate_rdists()
841 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ in gic_iterate_rdists()
865 return ret ? -ENODEV : 0; in gic_iterate_rdists()
885 u64 offset = ptr - region->redist_base; in __gic_populate_rdist()
886 raw_spin_lock_init(&gic_data_rdist()->rd_lock); in __gic_populate_rdist()
888 gic_data_rdist()->phys_base = region->phys_base + offset; in __gic_populate_rdist()
892 (int)(region - gic_data.redist_regions), in __gic_populate_rdist()
893 &gic_data_rdist()->phys_base); in __gic_populate_rdist()
907 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", in gic_populate_rdist()
910 return -ENODEV; in gic_populate_rdist()
918 /* Boot-time cleanip */ in __gic_update_rdist_properties()
936 /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */ in __gic_update_rdist_properties()
942 /* Detect non-sensical configurations */ in __gic_update_rdist_properties()
1018 * any pre-emptive interrupts from working at all). Writing a zero in gic_cpu_sys_reg_init()
1087 * - The write is ignored. in gic_cpu_sys_reg_init()
1088 * - The RS field is treated as 0. in gic_cpu_sys_reg_init()
1127 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
1170 cpu--; in gic_compute_target_list()
1202 if (WARN_ON(d->hwirq >= 16)) in gic_ipi_send_mask()
1216 gic_send_sgi(cluster_id, tlist, d->hwirq); in gic_ipi_send_mask()
1235 /* Register all 8 non-secure SGIs */ in gic_smp_init()
1236 base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8, in gic_smp_init()
1250 void __iomem *reg; in gic_set_affinity() local
1260 return -EINVAL; in gic_set_affinity()
1263 return -EINVAL; in gic_set_affinity()
1271 reg = gic_dist_base(d) + offset + (index * 8); in gic_set_affinity()
1274 gic_write_irouter(val, reg); in gic_set_affinity()
1377 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1385 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1391 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1399 return -EPERM; in gic_irq_domain_map()
1400 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1405 return -EPERM; in gic_irq_domain_map()
1418 if (fwspec->param_count == 1 && fwspec->param[0] < 16) { in gic_irq_domain_translate()
1419 *hwirq = fwspec->param[0]; in gic_irq_domain_translate()
1424 if (is_of_node(fwspec->fwnode)) { in gic_irq_domain_translate()
1425 if (fwspec->param_count < 3) in gic_irq_domain_translate()
1426 return -EINVAL; in gic_irq_domain_translate()
1428 switch (fwspec->param[0]) { in gic_irq_domain_translate()
1430 *hwirq = fwspec->param[1] + 32; in gic_irq_domain_translate()
1433 *hwirq = fwspec->param[1] + 16; in gic_irq_domain_translate()
1436 *hwirq = fwspec->param[1] + ESPI_BASE_INTID; in gic_irq_domain_translate()
1439 *hwirq = fwspec->param[1] + EPPI_BASE_INTID; in gic_irq_domain_translate()
1442 *hwirq = fwspec->param[1]; in gic_irq_domain_translate()
1445 *hwirq = fwspec->param[1]; in gic_irq_domain_translate()
1446 if (fwspec->param[1] >= 16) in gic_irq_domain_translate()
1447 *hwirq += EPPI_BASE_INTID - 16; in gic_irq_domain_translate()
1452 return -EINVAL; in gic_irq_domain_translate()
1455 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in gic_irq_domain_translate()
1462 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); in gic_irq_domain_translate()
1466 if (is_fwnode_irqchip(fwspec->fwnode)) { in gic_irq_domain_translate()
1467 if(fwspec->param_count != 2) in gic_irq_domain_translate()
1468 return -EINVAL; in gic_irq_domain_translate()
1470 *hwirq = fwspec->param[0]; in gic_irq_domain_translate()
1471 *type = fwspec->param[1]; in gic_irq_domain_translate()
1477 return -EINVAL; in gic_irq_domain_translate()
1518 if (fwspec->fwnode != d->fwnode) in gic_irq_domain_select()
1522 if (!is_of_node(fwspec->fwnode)) in gic_irq_domain_select()
1526 * If this is a PPI and we have a 4th (non-null) parameter, in gic_irq_domain_select()
1529 if (fwspec->param_count >= 4 && in gic_irq_domain_select()
1530 fwspec->param[0] == 1 && fwspec->param[3] != 0 && in gic_irq_domain_select()
1532 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); in gic_irq_domain_select()
1553 return -ENOMEM; in partition_domain_translate()
1555 np = of_find_node_by_phandle(fwspec->param[3]); in partition_domain_translate()
1557 return -EINVAL; in partition_domain_translate()
1559 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], in partition_domain_translate()
1565 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in partition_domain_translate()
1579 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; in gic_enable_quirk_msm8996()
1588 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539; in gic_enable_quirk_cavium_38539()
1598 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite in gic_enable_quirk_hip06_07()
1600 * that GIC-600 doesn't have ESPI, so nothing to do in that case. in gic_enable_quirk_hip06_07()
1604 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) { in gic_enable_quirk_hip06_07()
1606 d->rdists.gicd_typer &= ~GENMASK(9, 8); in gic_enable_quirk_hip06_07()
1616 .compatible = "qcom,msm8996-gic-v3",
1635 * - ThunderX: CN88xx
1636 * - OCTEON TX: CN83xx, CN81xx
1637 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1670 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n", in gic_enable_nmi_support()
1676 * and if Group 0 interrupts can be delivered to Linux in the non-secure in gic_enable_nmi_support()
1682 * ----------------------------------------------------------- in gic_enable_nmi_support()
1683 * 1 | - | unchanged | unchanged in gic_enable_nmi_support()
1684 * ----------------------------------------------------------- in gic_enable_nmi_support()
1685 * 0 | 1 | non-secure | non-secure in gic_enable_nmi_support()
1686 * ----------------------------------------------------------- in gic_enable_nmi_support()
1687 * 0 | 0 | unchanged | non-secure in gic_enable_nmi_support()
1689 * where non-secure means that the value is right-shifted by one and the in gic_enable_nmi_support()
1690 * MSB bit set, to make it fit in the non-secure priority range. in gic_enable_nmi_support()
1697 * be in the non-secure range, we use a different PMR value to mask IRQs in gic_enable_nmi_support()
1741 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); in gic_init_bases()
1760 err = -ENOMEM; in gic_init_bases()
1806 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; in gic_validate_dist_version() local
1808 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) in gic_validate_dist_version()
1809 return -ENODEV; in gic_validate_dist_version()
1822 parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); in gic_populate_ppi_partitions()
1845 part->partition_id = of_node_to_fwnode(child_part); in gic_populate_ppi_partitions()
1874 cpumask_set_cpu(cpu, &part->mask); in gic_populate_ppi_partitions()
1921 if (of_property_read_u32(node, "#redistributor-regions", in gic_of_setup_kvm_info()
1946 return -ENXIO; in gic_of_init()
1955 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) in gic_of_init()
1961 err = -ENOMEM; in gic_of_init()
1973 err = -ENODEV; in gic_of_init()
1979 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) in gic_of_init()
1985 redist_stride, &node->fwnode); in gic_of_init()
2005 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
2039 redist_base = ioremap(redist->base_address, redist->length); in gic_acpi_parse_madt_redist()
2041 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); in gic_acpi_parse_madt_redist()
2042 return -ENOMEM; in gic_acpi_parse_madt_redist()
2045 gic_acpi_register_redist(redist->base_address, redist_base); in gic_acpi_parse_madt_redist()
2055 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; in gic_acpi_parse_madt_gicc() local
2056 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; in gic_acpi_parse_madt_gicc()
2060 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_parse_madt_gicc()
2063 redist_base = ioremap(gicc->gicr_base_address, size); in gic_acpi_parse_madt_gicc()
2065 return -ENOMEM; in gic_acpi_parse_madt_gicc()
2067 gic_acpi_register_redist(gicc->gicr_base_address, redist_base); in gic_acpi_parse_madt_gicc()
2089 return -ENODEV; in gic_acpi_collect_gicr_base()
2109 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) { in gic_acpi_match_gicc()
2118 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_match_gicc()
2121 return -ENODEV; in gic_acpi_match_gicc()
2157 if (dist->version != ape->driver_data) in acpi_validate_gic_table()
2178 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_parse_virt_madt_gicc()
2181 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? in gic_acpi_parse_virt_madt_gicc()
2187 acpi_data.maint_irq = gicc->vgic_interrupt; in gic_acpi_parse_virt_madt_gicc()
2189 acpi_data.vcpu_base = gicc->gicv_base_address; in gic_acpi_parse_virt_madt_gicc()
2197 if ((acpi_data.maint_irq != gicc->vgic_interrupt) || in gic_acpi_parse_virt_madt_gicc()
2199 (acpi_data.vcpu_base != gicc->gicv_base_address)) in gic_acpi_parse_virt_madt_gicc()
2200 return -EINVAL; in gic_acpi_parse_virt_madt_gicc()
2241 vcpu->flags = IORESOURCE_MEM; in gic_acpi_setup_kvm_info()
2242 vcpu->start = acpi_data.vcpu_base; in gic_acpi_setup_kvm_info()
2243 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; in gic_acpi_setup_kvm_info()
2261 acpi_data.dist_base = ioremap(dist->base_address, in gic_acpi_init()
2265 return -ENOMEM; in gic_acpi_init()
2278 err = -ENOMEM; in gic_acpi_init()
2286 domain_handle = irq_domain_alloc_fwnode(&dist->base_address); in gic_acpi_init()
2288 err = -ENOMEM; in gic_acpi_init()