1 // SPDX-License-Identifier: GPL-2.0-or-later
4  * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9  * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-pltfm.h"
47 /* Default settings for ZynqMP Clock Phases */
55  * On some SoCs the syscon area has a feature where the upper 16-bits of
56  * each 32-bit register act as a write mask for the lower 16-bits.  This allows
64  * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
68  * @shift:	Bit offset within @reg of this field (or -1 if not avail)
77  * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
96  * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
99  * @sampleclk_ops:	The sample clock related operations
107  * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
113  * @clk_phase_in:	Array of Input Clock Phase Delays for all speed modes
114  * @clk_phase_out:	Array of Output Clock Phase Delays for all speed modes
130  * struct sdhci_arasan_data - Arasan Controller Data
164  * met at 25MHz for Default Speed mode, those controllers work at
184 	.clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
190 	.clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
202  * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
221 	struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;  in sdhci_arasan_syscon_write()
222 	u32 reg = fld->reg;  in sdhci_arasan_syscon_write()
223 	u16 width = fld->width;  in sdhci_arasan_syscon_write()
224 	s16 shift = fld->shift;  in sdhci_arasan_syscon_write()
234 		return -EINVAL;  in sdhci_arasan_syscon_write()
236 	if (sdhci_arasan->soc_ctl_map->hiword_update)  in sdhci_arasan_syscon_write()
248 			 mmc_hostname(host->mmc), ret);  in sdhci_arasan_syscon_write()
257 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;  in sdhci_arasan_set_clock()
260 	if (!IS_ERR(sdhci_arasan->phy)) {  in sdhci_arasan_set_clock()
261 		if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {  in sdhci_arasan_set_clock()
275 			sdhci_set_clock(host, host->max_clk);  in sdhci_arasan_set_clock()
276 			if (phy_power_on(sdhci_arasan->phy)) {  in sdhci_arasan_set_clock()
278 				       mmc_hostname(host->mmc));  in sdhci_arasan_set_clock()
282 			sdhci_arasan->is_phy_on = true;  in sdhci_arasan_set_clock()
299 	if (ctrl_phy && sdhci_arasan->is_phy_on) {  in sdhci_arasan_set_clock()
300 		phy_power_off(sdhci_arasan->phy);  in sdhci_arasan_set_clock()
301 		sdhci_arasan->is_phy_on = false;  in sdhci_arasan_set_clock()
304 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) {  in sdhci_arasan_set_clock()
307 		 * requirements met at 25MHz for Default Speed mode,  in sdhci_arasan_set_clock()
314 	/* Set the Input and Output Clock Phase Delays */  in sdhci_arasan_set_clock()
315 	if (clk_data->set_clk_delays)  in sdhci_arasan_set_clock()
316 		clk_data->set_clk_delays(host);  in sdhci_arasan_set_clock()
320 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)  in sdhci_arasan_set_clock()
331 		if (phy_power_on(sdhci_arasan->phy)) {  in sdhci_arasan_set_clock()
333 			       mmc_hostname(host->mmc));  in sdhci_arasan_set_clock()
337 		sdhci_arasan->is_phy_on = true;  in sdhci_arasan_set_clock()
348 	if (ios->enhanced_strobe)  in sdhci_arasan_hs400_enhanced_strobe()
364 	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {  in sdhci_arasan_reset()
374 	switch (ios->signal_voltage) {  in sdhci_arasan_voltage_switch()
390 	return -EINVAL;  in sdhci_arasan_voltage_switch()
411 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);  in sdhci_arasan_cqhci_irq()
461  * sdhci_arasan_suspend - Suspend method for the driver
475 	if (host->tuning_mode != SDHCI_TUNING_MODE_3)  in sdhci_arasan_suspend()
476 		mmc_retune_needed(host->mmc);  in sdhci_arasan_suspend()
478 	if (sdhci_arasan->has_cqe) {  in sdhci_arasan_suspend()
479 		ret = cqhci_suspend(host->mmc);  in sdhci_arasan_suspend()
488 	if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {  in sdhci_arasan_suspend()
489 		ret = phy_power_off(sdhci_arasan->phy);  in sdhci_arasan_suspend()
497 		sdhci_arasan->is_phy_on = false;  in sdhci_arasan_suspend()
500 	clk_disable(pltfm_host->clk);  in sdhci_arasan_suspend()
501 	clk_disable(sdhci_arasan->clk_ahb);  in sdhci_arasan_suspend()
507  * sdhci_arasan_resume - Resume method for the driver
521 	ret = clk_enable(sdhci_arasan->clk_ahb);  in sdhci_arasan_resume()
527 	ret = clk_enable(pltfm_host->clk);  in sdhci_arasan_resume()
533 	if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {  in sdhci_arasan_resume()
534 		ret = phy_power_on(sdhci_arasan->phy);  in sdhci_arasan_resume()
539 		sdhci_arasan->is_phy_on = true;  in sdhci_arasan_resume()
548 	if (sdhci_arasan->has_cqe)  in sdhci_arasan_resume()
549 		return cqhci_resume(host->mmc);  in sdhci_arasan_resume()
559  * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
576 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_arasan_sdcardclk_recalc_rate()
578 	return host->mmc->actual_clock;  in sdhci_arasan_sdcardclk_recalc_rate()
586  * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
594  * Return: The sample clock rate.
603 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_arasan_sampleclk_recalc_rate()
605 	return host->mmc->actual_clock;  in sdhci_arasan_sampleclk_recalc_rate()
613  * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
616  * @degrees:		The clock phase shift between 0 - 359.
628 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_zynqmp_sdcardclk_set_phase()
635 	if (host->version < SDHCI_SPEC_300)  in sdhci_zynqmp_sdcardclk_set_phase()
638 	switch (host->timing) {  in sdhci_zynqmp_sdcardclk_set_phase()
655 	default:  in sdhci_zynqmp_sdcardclk_set_phase()
661 	/* Set the Clock Phase */  in sdhci_zynqmp_sdcardclk_set_phase()
678  * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
681  * @degrees:		The clock phase shift between 0 - 359.
693 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_zynqmp_sampleclk_set_phase()
700 	if (host->version < SDHCI_SPEC_300)  in sdhci_zynqmp_sampleclk_set_phase()
706 	switch (host->timing) {  in sdhci_zynqmp_sampleclk_set_phase()
723 	default:  in sdhci_zynqmp_sampleclk_set_phase()
729 	/* Set the Clock Phase */  in sdhci_zynqmp_sampleclk_set_phase()
743  * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
746  * @degrees:		The clock phase shift between 0 - 359.
758 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_versal_sdcardclk_set_phase()
762 	if (host->version < SDHCI_SPEC_300)  in sdhci_versal_sdcardclk_set_phase()
765 	switch (host->timing) {  in sdhci_versal_sdcardclk_set_phase()
782 	default:  in sdhci_versal_sdcardclk_set_phase()
788 	/* Set the Clock Phase */  in sdhci_versal_sdcardclk_set_phase()
809  * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
812  * @degrees:		The clock phase shift between 0 - 359.
824 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_versal_sampleclk_set_phase()
828 	if (host->version < SDHCI_SPEC_300)  in sdhci_versal_sampleclk_set_phase()
831 	switch (host->timing) {  in sdhci_versal_sampleclk_set_phase()
848 	default:  in sdhci_versal_sampleclk_set_phase()
854 	/* Set the Clock Phase */  in sdhci_versal_sampleclk_set_phase()
899 	struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;  in arasan_zynqmp_execute_tuning()
917  * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
926  * - Many existing devices don't seem to do this and work fine.  To keep
930  * - The value of corecfg_clockmultiplier should sync with that of corresponding
940 		sdhci_arasan->soc_ctl_map;  in sdhci_arasan_update_clockmultiplier()
947 	if (!sdhci_arasan->soc_ctl_base) {  in sdhci_arasan_update_clockmultiplier()
948 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",  in sdhci_arasan_update_clockmultiplier()
949 			mmc_hostname(host->mmc));  in sdhci_arasan_update_clockmultiplier()
953 	sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);  in sdhci_arasan_update_clockmultiplier()
957  * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
965  * - Many existing devices don't seem to do this and work fine.  To keep
969  * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
978 		sdhci_arasan->soc_ctl_map;  in sdhci_arasan_update_baseclkfreq()
979 	u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);  in sdhci_arasan_update_baseclkfreq()
986 	if (!sdhci_arasan->soc_ctl_base) {  in sdhci_arasan_update_baseclkfreq()
987 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",  in sdhci_arasan_update_baseclkfreq()
988 			mmc_hostname(host->mmc));  in sdhci_arasan_update_baseclkfreq()
992 	sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);  in sdhci_arasan_update_baseclkfreq()
999 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;  in sdhci_arasan_set_clk_delays()
1001 	clk_set_phase(clk_data->sampleclk,  in sdhci_arasan_set_clk_delays()
1002 		      clk_data->clk_phase_in[host->timing]);  in sdhci_arasan_set_clk_delays()
1003 	clk_set_phase(clk_data->sdcardclk,  in sdhci_arasan_set_clk_delays()
1004 		      clk_data->clk_phase_out[host->timing]);  in sdhci_arasan_set_clk_delays()
1011 	struct device_node *np = dev->of_node;  in arasan_dt_read_clk_phase()
1017 	 * Tap Values then use the pre-defined values.  in arasan_dt_read_clk_phase()
1021 		dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",  in arasan_dt_read_clk_phase()
1022 			prop, clk_data->clk_phase_in[timing],  in arasan_dt_read_clk_phase()
1023 			clk_data->clk_phase_out[timing]);  in arasan_dt_read_clk_phase()
1028 	clk_data->clk_phase_in[timing] = clk_phase[0];  in arasan_dt_read_clk_phase()
1029 	clk_data->clk_phase_out[timing] = clk_phase[1];  in arasan_dt_read_clk_phase()
1033  * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1051 	clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;  in arasan_dt_parse_clk_phases()
1053 	if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {  in arasan_dt_parse_clk_phases()
1059 		of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);  in arasan_dt_parse_clk_phases()
1066 			clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];  in arasan_dt_parse_clk_phases()
1067 			clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];  in arasan_dt_parse_clk_phases()
1071 	if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {  in arasan_dt_parse_clk_phases()
1078 			clk_data->clk_phase_in[i] = versal_iclk_phase[i];  in arasan_dt_parse_clk_phases()
1079 			clk_data->clk_phase_out[i] = versal_oclk_phase[i];  in arasan_dt_parse_clk_phases()
1084 				 "clk-phase-legacy");  in arasan_dt_parse_clk_phases()
1086 				 "clk-phase-mmc-hs");  in arasan_dt_parse_clk_phases()
1088 				 "clk-phase-sd-hs");  in arasan_dt_parse_clk_phases()
1090 				 "clk-phase-uhs-sdr12");  in arasan_dt_parse_clk_phases()
1092 				 "clk-phase-uhs-sdr25");  in arasan_dt_parse_clk_phases()
1094 				 "clk-phase-uhs-sdr50");  in arasan_dt_parse_clk_phases()
1096 				 "clk-phase-uhs-sdr104");  in arasan_dt_parse_clk_phases()
1098 				 "clk-phase-uhs-ddr50");  in arasan_dt_parse_clk_phases()
1100 				 "clk-phase-mmc-ddr52");  in arasan_dt_parse_clk_phases()
1102 				 "clk-phase-mmc-hs200");  in arasan_dt_parse_clk_phases()
1104 				 "clk-phase-mmc-hs400");  in arasan_dt_parse_clk_phases()
1233 	/* SoC-specific compatible strings w/ soc_ctl_map */
1235 		.compatible = "rockchip,rk3399-sdhci-5.1",
1239 		.compatible = "intel,lgm-sdhci-5.1-emmc",
1243 		.compatible = "intel,lgm-sdhci-5.1-sdxc",
1247 		.compatible = "intel,keembay-sdhci-5.1-emmc",
1251 		.compatible = "intel,keembay-sdhci-5.1-sd",
1255 		.compatible = "intel,keembay-sdhci-5.1-sdio",
1260 		.compatible = "arasan,sdhci-8.9a",
1264 		.compatible = "arasan,sdhci-5.1",
1268 		.compatible = "arasan,sdhci-4.9a",
1272 		.compatible = "xlnx,zynqmp-8.9a",
1276 		.compatible = "xlnx,versal-8.9a",
1284  * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1301 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;  in sdhci_arasan_register_sdcardclk()
1302 	struct device_node *np = dev->of_node;  in sdhci_arasan_register_sdcardclk()
1307 	ret = of_property_read_string_index(np, "clock-output-names", 0,  in sdhci_arasan_register_sdcardclk()
1310 		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");  in sdhci_arasan_register_sdcardclk()
1318 	sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops;  in sdhci_arasan_register_sdcardclk()
1320 	clk_data->sdcardclk_hw.init = &sdcardclk_init;  in sdhci_arasan_register_sdcardclk()
1321 	clk_data->sdcardclk =  in sdhci_arasan_register_sdcardclk()
1322 		devm_clk_register(dev, &clk_data->sdcardclk_hw);  in sdhci_arasan_register_sdcardclk()
1323 	if (IS_ERR(clk_data->sdcardclk))  in sdhci_arasan_register_sdcardclk()
1324 		return PTR_ERR(clk_data->sdcardclk);  in sdhci_arasan_register_sdcardclk()
1325 	clk_data->sdcardclk_hw.init = NULL;  in sdhci_arasan_register_sdcardclk()
1328 				  clk_data->sdcardclk);  in sdhci_arasan_register_sdcardclk()
1336  * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1353 	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;  in sdhci_arasan_register_sampleclk()
1354 	struct device_node *np = dev->of_node;  in sdhci_arasan_register_sampleclk()
1359 	ret = of_property_read_string_index(np, "clock-output-names", 1,  in sdhci_arasan_register_sampleclk()
1362 		dev_err(dev, "DT has #clock-cells but no clock-output-names\n");  in sdhci_arasan_register_sampleclk()
1370 	sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops;  in sdhci_arasan_register_sampleclk()
1372 	clk_data->sampleclk_hw.init = &sampleclk_init;  in sdhci_arasan_register_sampleclk()
1373 	clk_data->sampleclk =  in sdhci_arasan_register_sampleclk()
1374 		devm_clk_register(dev, &clk_data->sampleclk_hw);  in sdhci_arasan_register_sampleclk()
1375 	if (IS_ERR(clk_data->sampleclk))  in sdhci_arasan_register_sampleclk()
1376 		return PTR_ERR(clk_data->sampleclk);  in sdhci_arasan_register_sampleclk()
1377 	clk_data->sampleclk_hw.init = NULL;  in sdhci_arasan_register_sampleclk()
1380 				  clk_data->sampleclk);  in sdhci_arasan_register_sampleclk()
1382 		dev_err(dev, "Failed to add sample clock provider\n");  in sdhci_arasan_register_sampleclk()
1388  * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1397 	struct device_node *np = dev->of_node;  in sdhci_arasan_unregister_sdclk()
1399 	if (!of_find_property(np, "#clock-cells", NULL))  in sdhci_arasan_unregister_sdclk()
1402 	of_clk_del_provider(dev->of_node);  in sdhci_arasan_unregister_sdclk()
1406  * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1409  * 0: the Core supports only 32-bit System Address Bus.
1410  * 1: the Core supports 64-bit System Address Bus.
1413  * - For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
1414  *   Keem Bay does not support 64-bit access.
1424 		sdhci_arasan->soc_ctl_map;  in sdhci_arasan_update_support64b()
1431 	if (!sdhci_arasan->soc_ctl_base) {  in sdhci_arasan_update_support64b()
1432 		pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",  in sdhci_arasan_update_support64b()
1433 			mmc_hostname(host->mmc));  in sdhci_arasan_update_support64b()
1437 	sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);  in sdhci_arasan_update_support64b()
1441  * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1451  * Note: without seriously re-architecting SDHCI's clock code and testing on
1457  * re-architecting SDHCI if we see some benefit to it.
1465 	struct device_node *np = dev->of_node;  in sdhci_arasan_register_sdclk()
1470 	if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)  in sdhci_arasan_register_sdclk()
1491 	struct sdhci_host *host = sdhci_arasan->host;  in sdhci_arasan_add_host()
1496 	if (!sdhci_arasan->has_cqe)  in sdhci_arasan_add_host()
1503 	cq_host = devm_kzalloc(host->mmc->parent,  in sdhci_arasan_add_host()
1506 		ret = -ENOMEM;  in sdhci_arasan_add_host()
1510 	cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;  in sdhci_arasan_add_host()
1511 	cq_host->ops = &sdhci_arasan_cqhci_ops;  in sdhci_arasan_add_host()
1513 	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;  in sdhci_arasan_add_host()
1515 		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;  in sdhci_arasan_add_host()
1517 	ret = cqhci_init(cq_host, host->mmc, dma64);  in sdhci_arasan_add_host()
1541 	struct device_node *np = pdev->dev.of_node;  in sdhci_arasan_probe()
1544 	match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);  in sdhci_arasan_probe()
1545 	data = match->data;  in sdhci_arasan_probe()
1546 	host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));  in sdhci_arasan_probe()
1553 	sdhci_arasan->host = host;  in sdhci_arasan_probe()
1555 	sdhci_arasan->soc_ctl_map = data->soc_ctl_map;  in sdhci_arasan_probe()
1556 	sdhci_arasan->clk_ops = data->clk_ops;  in sdhci_arasan_probe()
1558 	node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);  in sdhci_arasan_probe()
1560 		sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);  in sdhci_arasan_probe()
1563 		if (IS_ERR(sdhci_arasan->soc_ctl_base)) {  in sdhci_arasan_probe()
1564 			ret = dev_err_probe(&pdev->dev,  in sdhci_arasan_probe()
1565 					    PTR_ERR(sdhci_arasan->soc_ctl_base),  in sdhci_arasan_probe()
1571 	sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");  in sdhci_arasan_probe()
1572 	if (IS_ERR(sdhci_arasan->clk_ahb)) {  in sdhci_arasan_probe()
1573 		dev_err(&pdev->dev, "clk_ahb clock not found.\n");  in sdhci_arasan_probe()
1574 		ret = PTR_ERR(sdhci_arasan->clk_ahb);  in sdhci_arasan_probe()
1578 	clk_xin = devm_clk_get(&pdev->dev, "clk_xin");  in sdhci_arasan_probe()
1580 		dev_err(&pdev->dev, "clk_xin clock not found.\n");  in sdhci_arasan_probe()
1585 	ret = clk_prepare_enable(sdhci_arasan->clk_ahb);  in sdhci_arasan_probe()
1587 		dev_err(&pdev->dev, "Unable to enable AHB clock.\n");  in sdhci_arasan_probe()
1593 		dev_err(&pdev->dev, "Unable to enable SD clock.\n");  in sdhci_arasan_probe()
1599 	if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))  in sdhci_arasan_probe()
1600 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;  in sdhci_arasan_probe()
1602 	if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))  in sdhci_arasan_probe()
1603 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;  in sdhci_arasan_probe()
1605 	pltfm_host->clk = clk_xin;  in sdhci_arasan_probe()
1607 	if (of_device_is_compatible(pdev->dev.of_node,  in sdhci_arasan_probe()
1608 				    "rockchip,rk3399-sdhci-5.1"))  in sdhci_arasan_probe()
1611 	if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||  in sdhci_arasan_probe()
1612 	    of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||  in sdhci_arasan_probe()
1613 	    of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {  in sdhci_arasan_probe()
1617 		host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;  in sdhci_arasan_probe()
1622 	ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);  in sdhci_arasan_probe()
1626 	if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {  in sdhci_arasan_probe()
1627 		host->mmc_host_ops.execute_tuning =  in sdhci_arasan_probe()
1630 		sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN;  in sdhci_arasan_probe()
1633 	arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data);  in sdhci_arasan_probe()
1635 	ret = mmc_of_parse(host->mmc);  in sdhci_arasan_probe()
1637 		if (ret != -EPROBE_DEFER)  in sdhci_arasan_probe()
1638 			dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret);  in sdhci_arasan_probe()
1642 	sdhci_arasan->phy = ERR_PTR(-ENODEV);  in sdhci_arasan_probe()
1643 	if (of_device_is_compatible(pdev->dev.of_node,  in sdhci_arasan_probe()
1644 				    "arasan,sdhci-5.1")) {  in sdhci_arasan_probe()
1645 		sdhci_arasan->phy = devm_phy_get(&pdev->dev,  in sdhci_arasan_probe()
1647 		if (IS_ERR(sdhci_arasan->phy)) {  in sdhci_arasan_probe()
1648 			ret = PTR_ERR(sdhci_arasan->phy);  in sdhci_arasan_probe()
1649 			dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");  in sdhci_arasan_probe()
1653 		ret = phy_init(sdhci_arasan->phy);  in sdhci_arasan_probe()
1655 			dev_err(&pdev->dev, "phy_init err.\n");  in sdhci_arasan_probe()
1659 		host->mmc_host_ops.hs400_enhanced_strobe =  in sdhci_arasan_probe()
1661 		host->mmc_host_ops.start_signal_voltage_switch =  in sdhci_arasan_probe()
1663 		sdhci_arasan->has_cqe = true;  in sdhci_arasan_probe()
1664 		host->mmc->caps2 |= MMC_CAP2_CQE;  in sdhci_arasan_probe()
1666 		if (!of_property_read_bool(np, "disable-cqe-dcmd"))  in sdhci_arasan_probe()
1667 			host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;  in sdhci_arasan_probe()
1677 	if (!IS_ERR(sdhci_arasan->phy))  in sdhci_arasan_probe()
1678 		phy_exit(sdhci_arasan->phy);  in sdhci_arasan_probe()
1680 	sdhci_arasan_unregister_sdclk(&pdev->dev);  in sdhci_arasan_probe()
1684 	clk_disable_unprepare(sdhci_arasan->clk_ahb);  in sdhci_arasan_probe()
1696 	struct clk *clk_ahb = sdhci_arasan->clk_ahb;  in sdhci_arasan_remove()
1698 	if (!IS_ERR(sdhci_arasan->phy)) {  in sdhci_arasan_remove()
1699 		if (sdhci_arasan->is_phy_on)  in sdhci_arasan_remove()
1700 			phy_power_off(sdhci_arasan->phy);  in sdhci_arasan_remove()
1701 		phy_exit(sdhci_arasan->phy);  in sdhci_arasan_remove()
1704 	sdhci_arasan_unregister_sdclk(&pdev->dev);  in sdhci_arasan_remove()
1715 		.name = "sdhci-arasan",