Lines Matching +full:enable +full:- +full:ssc
1 // SPDX-License-Identifier: GPL-2.0+
7 * Version: v0.9.0 (2019-08-08)
16 #include "sdhci-pci.h"
218 /* enable tuning parameters control */ in gli_set_9750()
275 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
288 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
290 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
291 return -ETIMEDOUT; in __sdhci_execute_tuning_9750()
295 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
298 return -EAGAIN; in __sdhci_execute_tuning_9750()
303 host->mmc->retune_period = 0; in gl9750_execute_tuning()
304 if (host->tuning_mode == SDHCI_TUNING_MODE_1) in gl9750_execute_tuning()
305 host->mmc->retune_period = host->tuning_count; in gl9750_execute_tuning()
308 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); in gl9750_execute_tuning()
344 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) in gl9750_set_ssc() argument
347 u32 ssc; in gl9750_set_ssc() local
351 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
354 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; in gl9750_set_ssc()
356 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); in gl9750_set_ssc()
357 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); in gl9750_set_ssc()
358 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
365 /* set pll to 205MHz and enable ssc */ in gl9750_set_ssc_pll_205mhz()
372 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9750_set_clock()
375 host->mmc->actual_clock = 0; in sdhci_gl9750_set_clock()
383 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9750_set_clock()
384 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9750_set_clock()
385 host->mmc->actual_clock = 205000000; in sdhci_gl9750_set_clock()
396 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, in gli_pcie_enable_msi()
399 pr_warn("%s: enable PCI MSI failed, error=%d\n", in gli_pcie_enable_msi()
400 mmc_hostname(slot->host->mmc), ret); in gli_pcie_enable_msi()
404 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); in gli_pcie_enable_msi()
471 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) in gl9755_set_ssc() argument
474 u32 ssc; in gl9755_set_ssc() local
478 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); in gl9755_set_ssc()
481 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; in gl9755_set_ssc()
483 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); in gl9755_set_ssc()
484 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); in gl9755_set_ssc()
485 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); in gl9755_set_ssc()
492 /* set pll to 205MHz and enable ssc */ in gl9755_set_ssc_pll_205mhz()
500 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9755_set_clock()
504 pdev = slot->chip->pdev; in sdhci_gl9755_set_clock()
505 host->mmc->actual_clock = 0; in sdhci_gl9755_set_clock()
513 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9755_set_clock()
514 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9755_set_clock()
515 host->mmc->actual_clock = 205000000; in sdhci_gl9755_set_clock()
524 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9750()
527 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9750()
535 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9755()
538 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9755()
550 * (6) Set 1.8V Signal Enable in the Host Control 2 register. in sdhci_gli_voltage_switch()
553 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to in sdhci_gli_voltage_switch()
556 * Wait 5ms after set 1.8V signal enable in Host Control 2 register in sdhci_gli_voltage_switch()
557 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. in sdhci_gli_voltage_switch()
577 value = readl(host->ioaddr + reg); in sdhci_gl9750_readl()
587 struct sdhci_pci_slot *slot = chip->slots[0]; in sdhci_pci_gli_resume()
589 pci_free_irq_vectors(slot->chip->pdev); in sdhci_pci_gli_resume()
597 struct sdhci_pci_slot *slot = chip->slots[0]; in sdhci_cqhci_gli_resume()
604 return cqhci_resume(slot->host->mmc); in sdhci_cqhci_gli_resume()
609 struct sdhci_pci_slot *slot = chip->slots[0]; in sdhci_cqhci_gli_suspend()
612 ret = cqhci_suspend(slot->host->mmc); in sdhci_cqhci_gli_suspend()
616 return sdhci_suspend_host(slot->host); in sdhci_cqhci_gli_suspend()
627 if (ios->enhanced_strobe) in gl9763e_hs400_enhanced_strobe()
661 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_gl9763e_cqe_pre_enable()
685 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_gl9763e_cqhci_irq()
693 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_gl9763e_cqe_post_disable()
703 .enable = sdhci_gl9763e_cqe_enable,
712 struct device *dev = &slot->chip->pdev->dev; in gl9763e_add_host()
713 struct sdhci_host *host = slot->host; in gl9763e_add_host()
724 ret = -ENOMEM; in gl9763e_add_host()
728 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; in gl9763e_add_host()
729 cq_host->ops = &sdhci_gl9763e_cqhci_ops; in gl9763e_add_host()
731 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in gl9763e_add_host()
733 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in gl9763e_add_host()
735 ret = cqhci_init(cq_host, host->mmc, dma64); in gl9763e_add_host()
752 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && in sdhci_gl9763e_reset()
753 host->mmc->cqe_private) in sdhci_gl9763e_reset()
754 cqhci_deactivate(host->mmc); in sdhci_gl9763e_reset()
760 struct pci_dev *pdev = slot->chip->pdev; in gli_set_gl9763e()
780 struct pci_dev *pdev = slot->chip->pdev; in gli_probe_slot_gl9763e()
781 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9763e()
784 host->mmc->caps |= MMC_CAP_8_BIT_DATA | in gli_probe_slot_gl9763e()
787 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | in gli_probe_slot_gl9763e()
795 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in gli_probe_slot_gl9763e()
798 host->mmc_host_ops.hs400_enhanced_strobe = in gli_probe_slot_gl9763e()