Lines Matching +full:tuning +full:- +full:start +full:- +full:tap
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
23 #include <linux/mmc/slot-gpio.h>
27 #include "sdhci-pltfm.h"
180 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_readw()
182 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && in tegra_sdhci_readw()
188 return readw(host->ioaddr + reg); in tegra_sdhci_readw()
201 pltfm_host->xfer_mode_shadow = val; in tegra_sdhci_writew()
204 writel((val << 16) | pltfm_host->xfer_mode_shadow, in tegra_sdhci_writew()
205 host->ioaddr + SDHCI_TRANSFER_MODE); in tegra_sdhci_writew()
209 writew(val, host->ioaddr + reg); in tegra_sdhci_writew()
216 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_writel()
225 writel(val, host->ioaddr + reg); in tegra_sdhci_writel()
227 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && in tegra_sdhci_writel()
230 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); in tegra_sdhci_writel()
235 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); in tegra_sdhci_writel()
275 writew(val, host->ioaddr + reg); in tegra210_sdhci_writew()
287 * Write-enable shall be assumed if GPIO is missing in a board's in tegra_sdhci_get_ro()
288 * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on in tegra_sdhci_get_ro()
291 return mmc_gpio_get_ro(host->mmc); in tegra_sdhci_get_ro()
308 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) in tegra_sdhci_is_pad_and_regulator_valid()
311 if (IS_ERR(host->mmc->supply.vqmmc)) in tegra_sdhci_is_pad_and_regulator_valid()
314 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, in tegra_sdhci_is_pad_and_regulator_valid()
317 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, in tegra_sdhci_is_pad_and_regulator_valid()
321 return tegra_host->pad_control_available; in tegra_sdhci_is_pad_and_regulator_valid()
327 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) in tegra_sdhci_set_tap() argument
331 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_set_tap()
336 * Touching the tap values is a bit tricky on some SoC generations. in tegra_sdhci_set_tap()
338 * the tap values are changed. in tegra_sdhci_set_tap()
341 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) in tegra_sdhci_set_tap()
346 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; in tegra_sdhci_set_tap()
349 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && in tegra_sdhci_set_tap()
361 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_reset()
369 tegra_sdhci_set_tap(host, tegra_host->default_tap); in tegra_sdhci_reset()
384 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) in tegra_sdhci_reset()
387 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) in tegra_sdhci_reset()
389 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) in tegra_sdhci_reset()
391 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) in tegra_sdhci_reset()
393 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) in tegra_sdhci_reset()
397 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; in tegra_sdhci_reset()
402 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { in tegra_sdhci_reset()
408 tegra_host->pad_calib_required = true; in tegra_sdhci_reset()
411 tegra_host->ddr_signaling = false; in tegra_sdhci_reset()
452 &tegra_host->autocal_offsets; in tegra_sdhci_set_padctrl()
461 if (tegra_host->pinctrl_state_1v8_drv) { in tegra_sdhci_set_padctrl()
463 tegra_host->pinctrl_state_1v8_drv; in tegra_sdhci_set_padctrl()
465 drvup = offsets->pull_up_1v8_timeout; in tegra_sdhci_set_padctrl()
466 drvdn = offsets->pull_down_1v8_timeout; in tegra_sdhci_set_padctrl()
469 if (tegra_host->pinctrl_state_3v3_drv) { in tegra_sdhci_set_padctrl()
471 tegra_host->pinctrl_state_3v3_drv; in tegra_sdhci_set_padctrl()
473 drvup = offsets->pull_up_3v3_timeout; in tegra_sdhci_set_padctrl()
474 drvdn = offsets->pull_down_3v3_timeout; in tegra_sdhci_set_padctrl()
479 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
482 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
495 if (!tegra_host->pad_control_available) in tegra_sdhci_set_padctrl()
499 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
500 tegra_host->pinctrl_state_1v8); in tegra_sdhci_set_padctrl()
502 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
505 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
506 tegra_host->pinctrl_state_3v3); in tegra_sdhci_set_padctrl()
508 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
521 tegra_host->autocal_offsets; in tegra_sdhci_pad_autocalib()
522 struct mmc_ios *ios = &host->mmc->ios; in tegra_sdhci_pad_autocalib()
528 switch (ios->timing) { in tegra_sdhci_pad_autocalib()
536 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) in tegra_sdhci_pad_autocalib()
542 /* Set initial offset before auto-calibration */ in tegra_sdhci_pad_autocalib()
555 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, in tegra_sdhci_pad_autocalib()
564 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); in tegra_sdhci_pad_autocalib()
571 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); in tegra_sdhci_pad_autocalib()
573 dev_err(mmc_dev(host->mmc), in tegra_sdhci_pad_autocalib()
583 &tegra_host->autocal_offsets; in tegra_sdhci_parse_pad_autocal_dt()
586 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
587 "nvidia,pad-autocal-pull-up-offset-3v3", in tegra_sdhci_parse_pad_autocal_dt()
588 &autocal->pull_up_3v3); in tegra_sdhci_parse_pad_autocal_dt()
590 autocal->pull_up_3v3 = 0; in tegra_sdhci_parse_pad_autocal_dt()
592 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
593 "nvidia,pad-autocal-pull-down-offset-3v3", in tegra_sdhci_parse_pad_autocal_dt()
594 &autocal->pull_down_3v3); in tegra_sdhci_parse_pad_autocal_dt()
596 autocal->pull_down_3v3 = 0; in tegra_sdhci_parse_pad_autocal_dt()
598 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
599 "nvidia,pad-autocal-pull-up-offset-1v8", in tegra_sdhci_parse_pad_autocal_dt()
600 &autocal->pull_up_1v8); in tegra_sdhci_parse_pad_autocal_dt()
602 autocal->pull_up_1v8 = 0; in tegra_sdhci_parse_pad_autocal_dt()
604 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
605 "nvidia,pad-autocal-pull-down-offset-1v8", in tegra_sdhci_parse_pad_autocal_dt()
606 &autocal->pull_down_1v8); in tegra_sdhci_parse_pad_autocal_dt()
608 autocal->pull_down_1v8 = 0; in tegra_sdhci_parse_pad_autocal_dt()
610 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
611 "nvidia,pad-autocal-pull-up-offset-sdr104", in tegra_sdhci_parse_pad_autocal_dt()
612 &autocal->pull_up_sdr104); in tegra_sdhci_parse_pad_autocal_dt()
614 autocal->pull_up_sdr104 = autocal->pull_up_1v8; in tegra_sdhci_parse_pad_autocal_dt()
616 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
617 "nvidia,pad-autocal-pull-down-offset-sdr104", in tegra_sdhci_parse_pad_autocal_dt()
618 &autocal->pull_down_sdr104); in tegra_sdhci_parse_pad_autocal_dt()
620 autocal->pull_down_sdr104 = autocal->pull_down_1v8; in tegra_sdhci_parse_pad_autocal_dt()
622 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
623 "nvidia,pad-autocal-pull-up-offset-hs400", in tegra_sdhci_parse_pad_autocal_dt()
624 &autocal->pull_up_hs400); in tegra_sdhci_parse_pad_autocal_dt()
626 autocal->pull_up_hs400 = autocal->pull_up_1v8; in tegra_sdhci_parse_pad_autocal_dt()
628 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
629 "nvidia,pad-autocal-pull-down-offset-hs400", in tegra_sdhci_parse_pad_autocal_dt()
630 &autocal->pull_down_hs400); in tegra_sdhci_parse_pad_autocal_dt()
632 autocal->pull_down_hs400 = autocal->pull_down_1v8; in tegra_sdhci_parse_pad_autocal_dt()
635 * Different fail-safe drive strength values based on the signaling in tegra_sdhci_parse_pad_autocal_dt()
640 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) in tegra_sdhci_parse_pad_autocal_dt()
643 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
644 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", in tegra_sdhci_parse_pad_autocal_dt()
645 &autocal->pull_up_3v3_timeout); in tegra_sdhci_parse_pad_autocal_dt()
647 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && in tegra_sdhci_parse_pad_autocal_dt()
648 (tegra_host->pinctrl_state_3v3_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
649 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
650 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
651 autocal->pull_up_3v3_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
654 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
655 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", in tegra_sdhci_parse_pad_autocal_dt()
656 &autocal->pull_down_3v3_timeout); in tegra_sdhci_parse_pad_autocal_dt()
658 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && in tegra_sdhci_parse_pad_autocal_dt()
659 (tegra_host->pinctrl_state_3v3_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
660 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
661 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
662 autocal->pull_down_3v3_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
665 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
666 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", in tegra_sdhci_parse_pad_autocal_dt()
667 &autocal->pull_up_1v8_timeout); in tegra_sdhci_parse_pad_autocal_dt()
669 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && in tegra_sdhci_parse_pad_autocal_dt()
670 (tegra_host->pinctrl_state_1v8_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
671 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
672 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
673 autocal->pull_up_1v8_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
676 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
677 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", in tegra_sdhci_parse_pad_autocal_dt()
678 &autocal->pull_down_1v8_timeout); in tegra_sdhci_parse_pad_autocal_dt()
680 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && in tegra_sdhci_parse_pad_autocal_dt()
681 (tegra_host->pinctrl_state_1v8_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
682 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
683 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
684 autocal->pull_down_1v8_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
693 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); in tegra_sdhci_request()
698 tegra_host->last_calib = ktime_get(); in tegra_sdhci_request()
710 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", in tegra_sdhci_parse_tap_and_trim()
711 &tegra_host->default_tap); in tegra_sdhci_parse_tap_and_trim()
713 tegra_host->default_tap = 0; in tegra_sdhci_parse_tap_and_trim()
715 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", in tegra_sdhci_parse_tap_and_trim()
716 &tegra_host->default_trim); in tegra_sdhci_parse_tap_and_trim()
718 tegra_host->default_trim = 0; in tegra_sdhci_parse_tap_and_trim()
720 err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim", in tegra_sdhci_parse_tap_and_trim()
721 &tegra_host->dqs_trim); in tegra_sdhci_parse_tap_and_trim()
723 tegra_host->dqs_trim = 0x11; in tegra_sdhci_parse_tap_and_trim()
731 if (device_property_read_bool(host->mmc->parent, "supports-cqe")) in tegra_sdhci_parse_dt()
732 tegra_host->enable_hwcq = true; in tegra_sdhci_parse_dt()
734 tegra_host->enable_hwcq = false; in tegra_sdhci_parse_dt()
753 * sdhci_calc_clk(). The divider is calculated from host->max_clk and in tegra_sdhci_set_clock()
756 * By setting the host->max_clk to clock * 2 the divider calculation in tegra_sdhci_set_clock()
761 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; in tegra_sdhci_set_clock()
762 clk_set_rate(pltfm_host->clk, host_clk); in tegra_sdhci_set_clock()
763 tegra_host->curr_clk_rate = host_clk; in tegra_sdhci_set_clock()
764 if (tegra_host->ddr_signaling) in tegra_sdhci_set_clock()
765 host->max_clk = host_clk; in tegra_sdhci_set_clock()
767 host->max_clk = clk_get_rate(pltfm_host->clk); in tegra_sdhci_set_clock()
771 if (tegra_host->pad_calib_required) { in tegra_sdhci_set_clock()
773 tegra_host->pad_calib_required = false; in tegra_sdhci_set_clock()
785 if (ios->enhanced_strobe) { in tegra_sdhci_hs400_enhanced_strobe()
807 return clk_round_rate(pltfm_host->clk, UINT_MAX); in tegra_sdhci_get_max_clock()
830 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, in tegra_sdhci_hs400_dll_cal()
834 dev_err(mmc_dev(host->mmc), in tegra_sdhci_hs400_dll_cal()
844 u8 word, bit, edge1, tap, window; in tegra_sdhci_tap_correction() local
855 u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE; in tegra_sdhci_tap_correction()
858 * Read auto-tuned results and extract good valid passing window by in tegra_sdhci_tap_correction()
859 * filtering out un-wanted bubble/partial/merged windows. in tegra_sdhci_tap_correction()
869 tap = word * TUNING_WORD_BIT_SIZE + bit; in tegra_sdhci_tap_correction()
874 first_fail_tap = tap; in tegra_sdhci_tap_correction()
879 start_pass_tap = tap; in tegra_sdhci_tap_correction()
882 first_pass_tap = tap; in tegra_sdhci_tap_correction()
888 end_pass_tap = tap - 1; in tegra_sdhci_tap_correction()
892 window = end_pass_tap - start_pass_tap; in tegra_sdhci_tap_correction()
895 start_pass_tap = tap; in tegra_sdhci_tap_correction()
898 /* set tap at middle of valid window */ in tegra_sdhci_tap_correction()
899 tap = start_pass_tap + window / 2; in tegra_sdhci_tap_correction()
900 tegra_host->tuned_tap_delay = tap; in tegra_sdhci_tap_correction()
912 /* set tap location at fixed tap relative to the first edge */ in tegra_sdhci_tap_correction()
913 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2; in tegra_sdhci_tap_correction()
914 if (edge1 - 1 > fixed_tap) in tegra_sdhci_tap_correction()
915 tegra_host->tuned_tap_delay = edge1 - fixed_tap; in tegra_sdhci_tap_correction()
917 tegra_host->tuned_tap_delay = edge1 + fixed_tap; in tegra_sdhci_tap_correction()
925 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_post_tuning()
932 /* retain HW tuned tap to use incase if no correction is needed */ in tegra_sdhci_post_tuning()
934 tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >> in tegra_sdhci_post_tuning()
936 if (soc_data->min_tap_delay && soc_data->max_tap_delay) { in tegra_sdhci_post_tuning()
937 min_tap_dly = soc_data->min_tap_delay; in tegra_sdhci_post_tuning()
938 max_tap_dly = soc_data->max_tap_delay; in tegra_sdhci_post_tuning()
939 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC; in tegra_sdhci_post_tuning()
950 * fixed tap is used when HW tuning result contains single edge in tegra_sdhci_post_tuning()
951 * and tap is set at fixed tap delay relative to the first edge in tegra_sdhci_post_tuning()
960 window_width = end_tap - start_tap; in tegra_sdhci_post_tuning()
961 num_iter = host->tuning_loop_count; in tegra_sdhci_post_tuning()
963 * partial window includes edges of the tuning range. in tegra_sdhci_post_tuning()
967 if (start_tap == 0 || (end_tap == (num_iter - 1)) || in tegra_sdhci_post_tuning()
968 (end_tap == num_iter - 2) || window_width >= thdupper) { in tegra_sdhci_post_tuning()
969 pr_debug("%s: Apply tuning correction\n", in tegra_sdhci_post_tuning()
970 mmc_hostname(host->mmc)); in tegra_sdhci_post_tuning()
976 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); in tegra_sdhci_post_tuning()
985 if (!err && !host->tuning_err) in tegra_sdhci_execute_hw_tuning()
1002 tegra_host->ddr_signaling = false; in tegra_sdhci_set_uhs_signaling()
1008 /* Don't set default tap on tunable modes. */ in tegra_sdhci_set_uhs_signaling()
1018 tegra_host->ddr_signaling = true; in tegra_sdhci_set_uhs_signaling()
1036 host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256; in tegra_sdhci_set_uhs_signaling()
1042 if (tegra_host->tuned_tap_delay && !set_default_tap) in tegra_sdhci_set_uhs_signaling()
1043 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); in tegra_sdhci_set_uhs_signaling()
1045 tegra_sdhci_set_tap(host, tegra_host->default_tap); in tegra_sdhci_set_uhs_signaling()
1048 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); in tegra_sdhci_set_uhs_signaling()
1059 * Start search for minimum tap value at 10, as smaller values are in tegra_sdhci_execute_tuning()
1066 if (!mmc_send_tuning(host->mmc, opcode, NULL)) in tegra_sdhci_execute_tuning()
1071 /* Find the maximum tap value that still passes. */ in tegra_sdhci_execute_tuning()
1075 if (mmc_send_tuning(host->mmc, opcode, NULL)) { in tegra_sdhci_execute_tuning()
1076 max--; in tegra_sdhci_execute_tuning()
1082 /* The TRM states the ideal tap value is at 75% in the passing range. */ in tegra_sdhci_execute_tuning()
1083 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); in tegra_sdhci_execute_tuning()
1085 return mmc_send_tuning(host->mmc, opcode, NULL); in tegra_sdhci_execute_tuning()
1096 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { in sdhci_tegra_start_signal_voltage_switch()
1097 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); in sdhci_tegra_start_signal_voltage_switch()
1101 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { in sdhci_tegra_start_signal_voltage_switch()
1105 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); in sdhci_tegra_start_signal_voltage_switch()
1108 if (tegra_host->pad_calib_required) in sdhci_tegra_start_signal_voltage_switch()
1117 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); in tegra_sdhci_init_pinctrl_info()
1118 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { in tegra_sdhci_init_pinctrl_info()
1120 PTR_ERR(tegra_host->pinctrl_sdmmc)); in tegra_sdhci_init_pinctrl_info()
1121 return -1; in tegra_sdhci_init_pinctrl_info()
1124 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( in tegra_sdhci_init_pinctrl_info()
1125 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); in tegra_sdhci_init_pinctrl_info()
1126 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { in tegra_sdhci_init_pinctrl_info()
1127 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) in tegra_sdhci_init_pinctrl_info()
1128 tegra_host->pinctrl_state_1v8_drv = NULL; in tegra_sdhci_init_pinctrl_info()
1131 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( in tegra_sdhci_init_pinctrl_info()
1132 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); in tegra_sdhci_init_pinctrl_info()
1133 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { in tegra_sdhci_init_pinctrl_info()
1134 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) in tegra_sdhci_init_pinctrl_info()
1135 tegra_host->pinctrl_state_3v3_drv = NULL; in tegra_sdhci_init_pinctrl_info()
1138 tegra_host->pinctrl_state_3v3 = in tegra_sdhci_init_pinctrl_info()
1139 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); in tegra_sdhci_init_pinctrl_info()
1140 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { in tegra_sdhci_init_pinctrl_info()
1142 PTR_ERR(tegra_host->pinctrl_state_3v3)); in tegra_sdhci_init_pinctrl_info()
1143 return -1; in tegra_sdhci_init_pinctrl_info()
1146 tegra_host->pinctrl_state_1v8 = in tegra_sdhci_init_pinctrl_info()
1147 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); in tegra_sdhci_init_pinctrl_info()
1148 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { in tegra_sdhci_init_pinctrl_info()
1150 PTR_ERR(tegra_host->pinctrl_state_1v8)); in tegra_sdhci_init_pinctrl_info()
1151 return -1; in tegra_sdhci_init_pinctrl_info()
1154 tegra_host->pad_control_available = true; in tegra_sdhci_init_pinctrl_info()
1163 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_voltage_switch()
1165 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) in tegra_sdhci_voltage_switch()
1166 tegra_host->pad_calib_required = true; in tegra_sdhci_voltage_switch()
1171 struct mmc_host *mmc = cq_host->mmc; in tegra_cqhci_writel()
1180 * to be re-configured. in tegra_cqhci_writel()
1189 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1202 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1204 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1213 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in sdhci_tegra_update_dcmd_desc()
1215 if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING && in sdhci_tegra_update_dcmd_desc()
1216 mrq->cmd->flags & MMC_RSP_R1B) in sdhci_tegra_update_dcmd_desc()
1222 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_enable()
1232 if (!cq_host->activated) { in sdhci_tegra_cqe_enable()
1268 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_tegra_cqhci_irq()
1292 if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC) in tegra_sdhci_set_timeout()
1303 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_pre_enable()
1313 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_post_disable()
1337 const struct sdhci_tegra_soc_data *soc = tegra->soc_data; in tegra_sdhci_set_dma_mask()
1338 struct device *dev = mmc_dev(host->mmc); in tegra_sdhci_set_dma_mask()
1340 if (soc->dma_mask) in tegra_sdhci_set_dma_mask()
1341 return dma_set_mask_and_coherent(dev, soc->dma_mask); in tegra_sdhci_set_dma_mask()
1386 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even
1543 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
1544 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
1545 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
1546 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
1547 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
1548 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1549 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1562 if (!tegra_host->enable_hwcq) in sdhci_tegra_add_host()
1571 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_tegra_add_host()
1573 cq_host = devm_kzalloc(host->mmc->parent, in sdhci_tegra_add_host()
1576 ret = -ENOMEM; in sdhci_tegra_add_host()
1580 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; in sdhci_tegra_add_host()
1581 cq_host->ops = &sdhci_tegra_cqhci_ops; in sdhci_tegra_add_host()
1583 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_tegra_add_host()
1585 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_tegra_add_host()
1587 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_tegra_add_host()
1612 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); in sdhci_tegra_probe()
1614 return -EINVAL; in sdhci_tegra_probe()
1615 soc_data = match->data; in sdhci_tegra_probe()
1617 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); in sdhci_tegra_probe()
1623 tegra_host->ddr_signaling = false; in sdhci_tegra_probe()
1624 tegra_host->pad_calib_required = false; in sdhci_tegra_probe()
1625 tegra_host->pad_control_available = false; in sdhci_tegra_probe()
1626 tegra_host->soc_data = soc_data; in sdhci_tegra_probe()
1628 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { in sdhci_tegra_probe()
1629 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); in sdhci_tegra_probe()
1631 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_tegra_probe()
1636 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) in sdhci_tegra_probe()
1637 host->mmc_host_ops.request = tegra_sdhci_request; in sdhci_tegra_probe()
1639 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_tegra_probe()
1642 if (!host->ops->platform_execute_tuning) in sdhci_tegra_probe()
1643 host->mmc_host_ops.execute_tuning = in sdhci_tegra_probe()
1646 rc = mmc_of_parse(host->mmc); in sdhci_tegra_probe()
1650 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) in sdhci_tegra_probe()
1651 host->mmc->caps |= MMC_CAP_1_8V_DDR; in sdhci_tegra_probe()
1654 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; in sdhci_tegra_probe()
1658 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", in sdhci_tegra_probe()
1660 if (IS_ERR(tegra_host->power_gpio)) { in sdhci_tegra_probe()
1661 rc = PTR_ERR(tegra_host->power_gpio); in sdhci_tegra_probe()
1680 if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) { in sdhci_tegra_probe()
1681 clk = devm_clk_get(&pdev->dev, "tmclk"); in sdhci_tegra_probe()
1684 if (rc == -EPROBE_DEFER) in sdhci_tegra_probe()
1687 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc); in sdhci_tegra_probe()
1694 dev_err(&pdev->dev, in sdhci_tegra_probe()
1699 tegra_host->tmclk = clk; in sdhci_tegra_probe()
1702 clk = devm_clk_get(mmc_dev(host->mmc), NULL); in sdhci_tegra_probe()
1704 rc = dev_err_probe(&pdev->dev, PTR_ERR(clk), in sdhci_tegra_probe()
1709 pltfm_host->clk = clk; in sdhci_tegra_probe()
1711 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, in sdhci_tegra_probe()
1713 if (IS_ERR(tegra_host->rst)) { in sdhci_tegra_probe()
1714 rc = PTR_ERR(tegra_host->rst); in sdhci_tegra_probe()
1715 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); in sdhci_tegra_probe()
1719 rc = reset_control_assert(tegra_host->rst); in sdhci_tegra_probe()
1725 rc = reset_control_deassert(tegra_host->rst); in sdhci_tegra_probe()
1738 reset_control_assert(tegra_host->rst); in sdhci_tegra_probe()
1740 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_probe()
1742 clk_disable_unprepare(tegra_host->tmclk); in sdhci_tegra_probe()
1757 reset_control_assert(tegra_host->rst); in sdhci_tegra_remove()
1759 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_remove()
1760 clk_disable_unprepare(tegra_host->tmclk); in sdhci_tegra_remove()
1774 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_tegra_suspend()
1775 ret = cqhci_suspend(host->mmc); in sdhci_tegra_suspend()
1782 cqhci_resume(host->mmc); in sdhci_tegra_suspend()
1786 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_suspend()
1796 ret = clk_prepare_enable(pltfm_host->clk); in sdhci_tegra_resume()
1804 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_tegra_resume()
1805 ret = cqhci_resume(host->mmc); in sdhci_tegra_resume()
1815 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_resume()
1825 .name = "sdhci-tegra",