Lines Matching full:ecc
163 * the NAND controller performs reads/writes with ECC in 516 byte chunks.
177 /* ECC modes supported by the controller */
416 * of a page, consisting of all data, ecc, spare
419 * by ECC
420 * @use_ecc: request the controller to use ECC for the
422 * @bch_enabled: flag to tell whether BCH ECC mode is used
423 * @ecc_bytes_hw: ECC bytes used by controller hardware for this
431 * ecc/non-ecc mode for the current nand flash
460 * @ecc_modes - ecc mode for NAND
1392 struct nand_ecc_ctrl *ecc = &chip->ecc; in parse_erase_write_errors() local
1396 num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1; in parse_erase_write_errors()
1442 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_command() local
1477 update_rw_regs(host, ecc->steps, true); in qcom_nandc_command()
1513 * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
1516 * when using RS ECC, the HW reports the same erros when reading an erased CW,
1520 * verify if the page is erased or not, and fix up the page for RS ECC by
1592 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_cw_raw() local
1604 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_read_cw_raw()
1607 if (cw == (ecc->steps - 1)) { in qcom_nandc_read_cw_raw()
1608 data_size2 = ecc->size - data_size1 - in qcom_nandc_read_cw_raw()
1609 ((ecc->steps - 1) * 4); in qcom_nandc_read_cw_raw()
1610 oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + in qcom_nandc_read_cw_raw()
1655 * number of 0 in each CW for which ECC engine returns the uncorrectable
1657 * equal to the ecc->strength for each CW.
1665 * The BBM and spare bytes bit flip won’t affect the ECC so don’t check
1675 struct nand_ecc_ctrl *ecc = &chip->ecc; in check_for_erased_page() local
1687 for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { in check_for_erased_page()
1688 if (cw == (ecc->steps - 1)) { in check_for_erased_page()
1689 data_size = ecc->size - ((ecc->steps - 1) * 4); in check_for_erased_page()
1690 oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; in check_for_erased_page()
1698 cw_oob_buf = oob_buf + (cw * ecc->bytes); in check_for_erased_page()
1712 0, ecc->strength); in check_for_erased_page()
1726 * errors. this is equivalent to what 'ecc->correct()' would do.
1734 struct nand_ecc_ctrl *ecc = &chip->ecc; in parse_read_errors() local
1744 for (i = 0; i < ecc->steps; i++, buf++) { in parse_read_errors()
1748 if (i == (ecc->steps - 1)) { in parse_read_errors()
1749 data_len = ecc->size - ((ecc->steps - 1) << 2); in parse_read_errors()
1750 oob_len = ecc->steps << 2; in parse_read_errors()
1761 * Check ECC failure for each codeword. ECC failure can in parse_read_errors()
1763 * 1. If number of bitflips are greater than ECC engine in parse_read_errors()
1770 * For BCH ECC, ignore erased codeword errors, if in parse_read_errors()
1777 * For RS ECC, HW reports the erased CW by placing in parse_read_errors()
1800 * No ECC or operational errors happened. Check the number of in parse_read_errors()
1814 oob_buf += oob_len + ecc->bytes; in parse_read_errors()
1829 * helper to perform the actual page read operation, used by ecc->read_page(),
1830 * ecc->read_oob()
1837 struct nand_ecc_ctrl *ecc = &chip->ecc; in read_page_ecc() local
1844 for (i = 0; i < ecc->steps; i++) { in read_page_ecc()
1847 if (i == (ecc->steps - 1)) { in read_page_ecc()
1848 data_size = ecc->size - ((ecc->steps - 1) << 2); in read_page_ecc()
1849 oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + in read_page_ecc()
1876 * when ecc is enabled, the controller doesn't read the real in read_page_ecc()
1878 * consistent layout across RAW and ECC reads, we just in read_page_ecc()
1917 struct nand_ecc_ctrl *ecc = &chip->ecc; in copy_last_cw() local
1928 set_address(host, host->cw_size * (ecc->steps - 1), page); in copy_last_cw()
1944 /* implements ecc->read_page() */
1961 /* implements ecc->read_page_raw() */
1967 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_page_raw() local
1971 for (cw = 0; cw < ecc->steps; cw++) { in qcom_nandc_read_page_raw()
1978 oob_buf += ecc->bytes; in qcom_nandc_read_page_raw()
1984 /* implements ecc->read_oob() */
1989 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_oob() local
1996 update_rw_regs(host, ecc->steps, true); in qcom_nandc_read_oob()
2001 /* implements ecc->write_page() */
2007 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_page() local
2020 update_rw_regs(host, ecc->steps, false); in qcom_nandc_write_page()
2023 for (i = 0; i < ecc->steps; i++) { in qcom_nandc_write_page()
2026 if (i == (ecc->steps - 1)) { in qcom_nandc_write_page()
2027 data_size = ecc->size - ((ecc->steps - 1) << 2); in qcom_nandc_write_page()
2028 oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + in qcom_nandc_write_page()
2032 oob_size = ecc->bytes; in qcom_nandc_write_page()
2037 i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0); in qcom_nandc_write_page()
2040 * when ECC is enabled, we don't really need to write anything in qcom_nandc_write_page()
2042 * just contain ECC bytes that's written by the controller in qcom_nandc_write_page()
2046 if (i == (ecc->steps - 1)) { in qcom_nandc_write_page()
2071 /* implements ecc->write_page_raw() */
2079 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_page_raw() local
2091 update_rw_regs(host, ecc->steps, false); in qcom_nandc_write_page_raw()
2094 for (i = 0; i < ecc->steps; i++) { in qcom_nandc_write_page_raw()
2098 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_write_page_raw()
2101 if (i == (ecc->steps - 1)) { in qcom_nandc_write_page_raw()
2102 data_size2 = ecc->size - data_size1 - in qcom_nandc_write_page_raw()
2103 ((ecc->steps - 1) << 2); in qcom_nandc_write_page_raw()
2104 oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + in qcom_nandc_write_page_raw()
2145 * implements ecc->write_oob()
2148 * since ECC is calculated for the combined codeword. So update the OOB from
2156 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_write_oob() local
2165 data_size = ecc->size - ((ecc->steps - 1) << 2); in qcom_nandc_write_oob()
2173 set_address(host, host->cw_size * (ecc->steps - 1), page); in qcom_nandc_write_oob()
2198 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_block_bad() local
2205 * the beginning of the last codeword, we don't care about reading ecc in qcom_nandc_block_bad()
2221 bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_block_bad()
2235 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_block_markbad() local
2252 set_address(host, host->cw_size * (ecc->steps - 1), page); in qcom_nandc_block_markbad()
2333 * Layout with ECC enabled:
2337 * | DATA xx..ECC..yy| | DATA **SPARE**xx..ECC..yy|
2345 * . = ECC bytes
2355 * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
2356 * the number of ECC bytes vary based on the ECC strength and the bus width.
2359 * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
2362 * When we access a page with ECC enabled, the reserved bytes(s) are not
2367 * Layout with ECC disabled:
2371 * | DATA1 yy DATA2 xx..ECC..| | DATA1 bb DATA2 **SPARE**xx..ECC..|
2379 * . = ECC bytes
2386 * when the ECC block is disabled, one reserved byte (or two for 16 bit bus
2390 * In order to have a consistent layout between RAW and ECC modes, we assume
2395 * |yyxx..ECC..| |bb*FREEOOB*xx..ECC..|
2403 * . = ECC bytes
2405 * y = Dummy bad block byte(s) (inaccessible when ECC enabled)
2407 * b = Real bad block byte(s) (inaccessible when ECC enabled)
2409 * This layout is read as is when ECC is disabled. When ECC is enabled, the
2411 * and assumed as 0xffs when we read a page/oob. The ECC, unused and
2412 * dummy/real bad block bytes are grouped as ecc bytes (i.e, ecc->bytes is
2420 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_ooblayout_ecc() local
2426 oobregion->length = (ecc->bytes * (ecc->steps - 1)) + in qcom_nand_ooblayout_ecc()
2442 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_ooblayout_free() local
2447 oobregion->length = ecc->steps * 4; in qcom_nand_ooblayout_free()
2448 oobregion->offset = ((ecc->steps - 1) * ecc->bytes) + host->bbm_size; in qcom_nand_ooblayout_free()
2454 .ecc = qcom_nand_ooblayout_ecc,
2470 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nand_attach_chip() local
2477 ecc->size = NANDC_STEP_SIZE; in qcom_nand_attach_chip()
2482 * Each CW has 4 available OOB bytes which will be protected with ECC in qcom_nand_attach_chip()
2483 * so remaining bytes can be used for ECC. in qcom_nand_attach_chip()
2488 dev_err(nandc->dev, "No valid ECC settings possible\n"); in qcom_nand_attach_chip()
2492 if (ecc->strength >= 8) { in qcom_nand_attach_chip()
2493 /* 8 bit ECC defaults to BCH ECC on all platforms */ in qcom_nand_attach_chip()
2508 * if the controller supports BCH for 4 bit ECC, the controller in qcom_nand_attach_chip()
2509 * uses lesser bytes for ECC. If RS is used, the ECC bytes is in qcom_nand_attach_chip()
2541 * we consider ecc->bytes as the sum of all the non-data content in a in qcom_nand_attach_chip()
2543 * all the bytes aren't used for ECC).It is always 16 bytes for 8 bit in qcom_nand_attach_chip()
2544 * ECC and 12 bytes for 4 bit ECC in qcom_nand_attach_chip()
2546 ecc->bytes = host->ecc_bytes_hw + host->spare_bytes + host->bbm_size; in qcom_nand_attach_chip()
2548 ecc->read_page = qcom_nandc_read_page; in qcom_nand_attach_chip()
2549 ecc->read_page_raw = qcom_nandc_read_page_raw; in qcom_nand_attach_chip()
2550 ecc->read_oob = qcom_nandc_read_oob; in qcom_nand_attach_chip()
2551 ecc->write_page = qcom_nandc_write_page; in qcom_nand_attach_chip()
2552 ecc->write_page_raw = qcom_nandc_write_page_raw; in qcom_nand_attach_chip()
2553 ecc->write_oob = qcom_nandc_write_oob; in qcom_nand_attach_chip()
2555 ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in qcom_nand_attach_chip()
2564 * spare data with ECC too. We protect spare data by default, so we set in qcom_nand_attach_chip()
2570 * total bytes in a step, either 528 bytes for 4 bit ECC, or 532 bytes in qcom_nand_attach_chip()
2571 * for 8 bit ECC in qcom_nand_attach_chip()
2573 host->cw_size = host->cw_data + ecc->bytes; in qcom_nand_attach_chip()
2625 host->cw_size, host->cw_data, ecc->strength, ecc->bytes, in qcom_nand_attach_chip()
2835 * of a page with ECC disabled. currently, the nand_base and nand_bbt in qcom_nand_host_init_and_register()
2836 * helpers don't allow us to read BB from a nand chip with ECC in qcom_nand_host_init_and_register()