Lines Matching +full:0 +full:- +full:indexed
1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define SFDP_JESD216_MINOR 0
20 * They are indexed from 1 but C arrays are indexed from 0.
22 #define BFPT_DWORD(i) ((i) - 1)
36 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
37 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
38 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
45 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
57 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
60 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
63 * Writing only one byte to the status register has the side-effect of
67 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
70 * - 011b: QE is bit 7 of status register 2. It is set via Write status
74 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
79 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
86 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
87 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
88 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
89 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
90 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
91 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */