Lines Matching +full:ar9331 +full:- +full:switch
1 // SPDX-License-Identifier: GPL-2.0-only
4 * +----------------------+
5 * GMAC1----RGMII----|--MAC0 |
6 * \---MDIO1----|--REGs |----MDIO3----\
7 * | | | +------+
8 * | | +--| |
9 * | MAC1-|----RMII--M-----| PHY0 |-o P0
10 * | | | | +------+
11 * | | | +--| |
12 * | MAC2-|----RMII--------| PHY1 |-o P1
13 * | | | | +------+
14 * | | | +--| |
15 * | MAC3-|----RMII--------| PHY2 |-o P2
16 * | | | | +------+
17 * | | | +--| |
18 * | MAC4-|----RMII--------| PHY3 |-o P3
19 * | | | | +------+
20 * | | | +--| |
21 * | MAC5-|--+-RMII--M-----|-PHY4-|-o P4
22 * | | | | +------+
23 * +----------------------+ | \--CFG_SW_PHY_SWAP
24 * GMAC0---------------RMII--------------------/ \-CFG_SW_PHY_ADDR_SWAP
25 * \---MDIO0--NC
31 * CFG_SW_PHY_SWAP - swap connections of PHY0 and PHY4. If this bit is not set
36 * CFG_SW_PHY_ADDR_SWAP - swap addresses of PHY0 and PHY4
39 * set and not related to switch internal registers.
77 /* FLOW_LINK_EN - enable mac flow control config auto-neg with phy.
82 /* LINK_EN - If set, MAC is configured from PHY link status.
105 * ------------------------------------------------------------------------
116 * ------------------------------------------------------------------------
118 * ------------------------------------------------------------------------
132 /* ------------------------------------------------------------------------
134 * ------------------------------------------------------------------------
142 * ------------------------------------------------------------------------
170 /* Warning: switch reset will reset last AR9331_SW_MDIO_PHY_MODE_PAGE request
177 ret = reset_control_assert(priv->sw_reset); in ar9331_sw_reset()
181 /* AR9331 doc do not provide any information about proper reset in ar9331_sw_reset()
182 * sequence. The AR8136 (the closes switch to the AR9331) doc says: in ar9331_sw_reset()
187 ret = reset_control_deassert(priv->sw_reset); in ar9331_sw_reset()
192 * status. AR9331 has no EEPROM support. in ar9331_sw_reset()
199 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); in ar9331_sw_reset()
206 struct ar9331_sw_priv *priv = mbus->priv; in ar9331_sw_mbus_write()
207 struct regmap *regmap = priv->regmap; in ar9331_sw_mbus_write()
229 dev_err_ratelimited(priv->dev, "PHY write error: %i\n", ret); in ar9331_sw_mbus_write()
235 struct ar9331_sw_priv *priv = mbus->priv; in ar9331_sw_mbus_read()
236 struct regmap *regmap = priv->regmap; in ar9331_sw_mbus_read()
263 dev_err_ratelimited(priv->dev, "PHY read error: %i\n", ret); in ar9331_sw_mbus_read()
269 struct device *dev = priv->dev; in ar9331_sw_mbus_init()
274 np = dev->of_node; in ar9331_sw_mbus_init()
278 return -ENOMEM; in ar9331_sw_mbus_init()
280 mbus->name = np->full_name; in ar9331_sw_mbus_init()
281 snprintf(mbus->id, MII_BUS_ID_SIZE, "%pOF", np); in ar9331_sw_mbus_init()
283 mbus->read = ar9331_sw_mbus_read; in ar9331_sw_mbus_init()
284 mbus->write = ar9331_sw_mbus_write; in ar9331_sw_mbus_init()
285 mbus->priv = priv; in ar9331_sw_mbus_init()
286 mbus->parent = dev; in ar9331_sw_mbus_init()
290 return -ENODEV; in ar9331_sw_mbus_init()
297 priv->mbus = mbus; in ar9331_sw_mbus_init()
304 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; in ar9331_sw_setup()
305 struct regmap *regmap = priv->regmap; in ar9331_sw_setup()
312 /* Reset will set proper defaults. CPU - Port0 will be enabled and in ar9331_sw_setup()
313 * configured. All other ports (ports 1 - 5) are disabled in ar9331_sw_setup()
335 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); in ar9331_sw_setup()
341 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; in ar9331_sw_port_disable()
342 struct regmap *regmap = priv->regmap; in ar9331_sw_port_disable()
347 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); in ar9331_sw_port_disable()
363 switch (port) { in ar9331_sw_phylink_validate()
365 if (state->interface != PHY_INTERFACE_MODE_GMII) in ar9331_sw_phylink_validate()
376 if (state->interface != PHY_INTERFACE_MODE_INTERNAL) in ar9331_sw_phylink_validate()
381 dev_err(ds->dev, "Unsupported port: %i\n", port); in ar9331_sw_phylink_validate()
396 bitmap_and(state->advertising, state->advertising, mask, in ar9331_sw_phylink_validate()
403 dev_err(ds->dev, "Unsupported interface: %d, port: %d\n", in ar9331_sw_phylink_validate()
404 state->interface, port); in ar9331_sw_phylink_validate()
411 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; in ar9331_sw_phylink_mac_config()
412 struct regmap *regmap = priv->regmap; in ar9331_sw_phylink_mac_config()
419 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); in ar9331_sw_phylink_mac_config()
426 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; in ar9331_sw_phylink_mac_link_down()
427 struct regmap *regmap = priv->regmap; in ar9331_sw_phylink_mac_link_down()
433 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); in ar9331_sw_phylink_mac_link_down()
443 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; in ar9331_sw_phylink_mac_link_up()
444 struct regmap *regmap = priv->regmap; in ar9331_sw_phylink_mac_link_up()
449 switch (speed) { in ar9331_sw_phylink_mac_link_up()
477 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); in ar9331_sw_phylink_mac_link_up()
493 struct regmap *regmap = priv->regmap; in ar9331_sw_irq()
499 dev_err(priv->dev, "can't read interrupt status\n"); in ar9331_sw_irq()
509 child_irq = irq_find_mapping(priv->irqdomain, 0); in ar9331_sw_irq()
515 dev_err(priv->dev, "can't write interrupt status\n"); in ar9331_sw_irq()
526 priv->irq_mask = 0; in ar9331_sw_mask_irq()
533 priv->irq_mask = AR9331_SW_GINT_PHY_INT; in ar9331_sw_unmask_irq()
540 mutex_lock(&priv->lock_irq); in ar9331_sw_irq_bus_lock()
546 struct regmap *regmap = priv->regmap; in ar9331_sw_irq_bus_sync_unlock()
550 AR9331_SW_GINT_PHY_INT, priv->irq_mask); in ar9331_sw_irq_bus_sync_unlock()
552 dev_err(priv->dev, "failed to change IRQ mask\n"); in ar9331_sw_irq_bus_sync_unlock()
554 mutex_unlock(&priv->lock_irq); in ar9331_sw_irq_bus_sync_unlock()
568 irq_set_chip_data(irq, domain->host_data); in ar9331_sw_irq_map()
591 struct device_node *np = priv->dev->of_node; in ar9331_sw_irq_init()
592 struct device *dev = priv->dev; in ar9331_sw_irq_init()
598 return irq ? irq : -EINVAL; in ar9331_sw_irq_init()
601 mutex_init(&priv->lock_irq); in ar9331_sw_irq_init()
609 priv->irqdomain = irq_domain_add_linear(np, 1, &ar9331_sw_irqdomain_ops, in ar9331_sw_irq_init()
611 if (!priv->irqdomain) { in ar9331_sw_irq_init()
613 return -EINVAL; in ar9331_sw_irq_init()
616 irq_set_parent(irq_create_mapping(priv->irqdomain, 0), irq); in ar9331_sw_irq_init()
647 struct mii_bus *sbus = priv->sbus; in ar9331_mdio_read()
673 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to read register.\n"); in ar9331_mdio_read()
680 struct mii_bus *sbus = priv->sbus; in ar9331_mdio_write()
692 /* In case of this switch we work with 32bit registers on top of 16bit in ar9331_mdio_write()
711 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to write register.\n"); in ar9331_mdio_write()
764 .range_max = AR9331_SW_REG_PAGE - 4,
809 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); in ar9331_sw_probe()
811 return -ENOMEM; in ar9331_sw_probe()
813 priv->regmap = devm_regmap_init(&mdiodev->dev, &ar9331_sw_bus, priv, in ar9331_sw_probe()
815 if (IS_ERR(priv->regmap)) { in ar9331_sw_probe()
816 ret = PTR_ERR(priv->regmap); in ar9331_sw_probe()
817 dev_err(&mdiodev->dev, "regmap init failed: %d\n", ret); in ar9331_sw_probe()
821 priv->sw_reset = devm_reset_control_get(&mdiodev->dev, "switch"); in ar9331_sw_probe()
822 if (IS_ERR(priv->sw_reset)) { in ar9331_sw_probe()
823 dev_err(&mdiodev->dev, "missing switch reset\n"); in ar9331_sw_probe()
824 return PTR_ERR(priv->sw_reset); in ar9331_sw_probe()
827 priv->sbus = mdiodev->bus; in ar9331_sw_probe()
828 priv->dev = &mdiodev->dev; in ar9331_sw_probe()
834 ds = &priv->ds; in ar9331_sw_probe()
835 ds->dev = &mdiodev->dev; in ar9331_sw_probe()
836 ds->num_ports = AR9331_SW_PORTS; in ar9331_sw_probe()
837 ds->priv = priv; in ar9331_sw_probe()
838 priv->ops = ar9331_sw_ops; in ar9331_sw_probe()
839 ds->ops = &priv->ops; in ar9331_sw_probe()
840 dev_set_drvdata(&mdiodev->dev, priv); in ar9331_sw_probe()
849 irq_domain_remove(priv->irqdomain); in ar9331_sw_probe()
856 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev); in ar9331_sw_remove()
858 irq_domain_remove(priv->irqdomain); in ar9331_sw_remove()
859 mdiobus_unregister(priv->mbus); in ar9331_sw_remove()
860 dsa_unregister_switch(&priv->ds); in ar9331_sw_remove()
862 reset_control_assert(priv->sw_reset); in ar9331_sw_remove()
866 { .compatible = "qca,ar9331-switch" },
882 MODULE_DESCRIPTION("Driver for Atheros AR9331 switch");