127 #define XGBE_PHY_PORT_SPEED_100		BIT(0)
132 #define XGBE_MUTEX_RELEASE		0x80000000
137 #define XGBE_SFP_SERIAL_ID_ADDRESS	0x50
138 #define XGBE_SFP_DIAG_INFO_ADDRESS	0x51
139 #define XGBE_SFP_PHY_ADDRESS		0x56
140 #define XGBE_GPIO_ADDRESS_PCA9555	0x20
143 #define XGBE_GPIO_NO_TX_FAULT		BIT(0)
160 	XGBE_PORT_MODE_RSVD = 0,
174 	XGBE_CONN_TYPE_NONE = 0,
184 	XGBE_SFP_COMM_DIRECT = 0,
189 	XGBE_SFP_CABLE_UNKNOWN = 0,
195 	XGBE_SFP_BASE_UNKNOWN = 0,
208 	XGBE_SFP_SPEED_UNKNOWN = 0,
214 /* SFP Serial ID Base ID values relative to an offset of 0 */
215 #define XGBE_SFP_BASE_ID			0
216 #define XGBE_SFP_ID_SFP				0x03
219 #define XGBE_SFP_EXT_ID_SFP			0x04
228 #define XGBE_SFP_BASE_1GBE_CC_SX		BIT(0)
238 #define XGBE_SFP_BASE_BR_1GBE_MIN		0x0a
239 #define XGBE_SFP_BASE_BR_1GBE_MAX		0x0d
240 #define XGBE_SFP_BASE_BR_10GBE_MIN		0x64
241 #define XGBE_SFP_BASE_BR_10GBE_MAX		0x68
298 	XGBE_MDIO_RESET_NONE = 0,
306 	XGBE_PHY_REDRV_IF_MDIO = 0,
312 	XGBE_PHY_REDRV_MODEL_4223 = 0,
322 #define XGBE_PHY_REDRV_MODE_REG	0x12b0
407 	redrv_data[0] = ((reg >> 8) & 0xff) << 1;  in xgbe_phy_redrv_write()
408 	redrv_data[1] = reg & 0xff;  in xgbe_phy_redrv_write()
413 	csum = 0;  in xgbe_phy_redrv_write()
414 	for (i = 0; i < 4; i++) {  in xgbe_phy_redrv_write()
449 	if (redrv_data[0] != 0xff) {  in xgbe_phy_redrv_write()
521 		return 0;  in xgbe_phy_sfp_put_mux()
524 	mux_channel = 0;  in xgbe_phy_sfp_put_mux()
540 		return 0;  in xgbe_phy_sfp_get_mux()
574 	mutex_id = 0;  in xgbe_phy_get_comm_ownership()
591 		return 0;  in xgbe_phy_get_comm_ownership()
627 	mii_data[0] = reg & 0xff;  in xgbe_phy_i2c_mii_write()
861 	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };  in xgbe_phy_finisar_phy_quirks()
868 	if ((phy_id & 0xfffffff0) != 0x01ff0cc0)  in xgbe_phy_finisar_phy_quirks()
872 	phy_write(phy_data->phydev, 0x16, 0x0001);  in xgbe_phy_finisar_phy_quirks()
873 	phy_write(phy_data->phydev, 0x00, 0x9140);  in xgbe_phy_finisar_phy_quirks()
874 	phy_write(phy_data->phydev, 0x16, 0x0000);  in xgbe_phy_finisar_phy_quirks()
877 	phy_write(phy_data->phydev, 0x1b, 0x9084);  in xgbe_phy_finisar_phy_quirks()
878 	phy_write(phy_data->phydev, 0x09, 0x0e00);  in xgbe_phy_finisar_phy_quirks()
879 	phy_write(phy_data->phydev, 0x00, 0x8140);  in xgbe_phy_finisar_phy_quirks()
880 	phy_write(phy_data->phydev, 0x04, 0x0d01);  in xgbe_phy_finisar_phy_quirks()
881 	phy_write(phy_data->phydev, 0x00, 0x9140);  in xgbe_phy_finisar_phy_quirks()
902 	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };  in xgbe_phy_belfuse_phy_quirks()
922 	if ((phy_id & 0xfffffff0) != 0x03625d10)  in xgbe_phy_belfuse_phy_quirks()
929 	phy_write(phy_data->phydev, 0x18, 0x7007);  in xgbe_phy_belfuse_phy_quirks()
930 	reg = phy_read(phy_data->phydev, 0x18);  in xgbe_phy_belfuse_phy_quirks()
931 	phy_write(phy_data->phydev, 0x18, reg & ~0x0080);  in xgbe_phy_belfuse_phy_quirks()
934 	phy_write(phy_data->phydev, 0x1c, 0x7c00);  in xgbe_phy_belfuse_phy_quirks()
935 	reg = phy_read(phy_data->phydev, 0x1c);  in xgbe_phy_belfuse_phy_quirks()
936 	reg &= 0x03ff;  in xgbe_phy_belfuse_phy_quirks()
937 	reg &= ~0x0001;  in xgbe_phy_belfuse_phy_quirks()
938 	phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001);  in xgbe_phy_belfuse_phy_quirks()
941 	reg = phy_read(phy_data->phydev, 0x00);  in xgbe_phy_belfuse_phy_quirks()
942 	phy_write(phy_data->phydev, 0x00, reg | 0x00800);  in xgbe_phy_belfuse_phy_quirks()
945 	phy_write(phy_data->phydev, 0x1c, 0x7c00);  in xgbe_phy_belfuse_phy_quirks()
946 	reg = phy_read(phy_data->phydev, 0x1c);  in xgbe_phy_belfuse_phy_quirks()
947 	reg &= 0x03ff;  in xgbe_phy_belfuse_phy_quirks()
948 	reg &= ~0x0006;  in xgbe_phy_belfuse_phy_quirks()
949 	phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004);  in xgbe_phy_belfuse_phy_quirks()
952 	reg = phy_read(phy_data->phydev, 0x00);  in xgbe_phy_belfuse_phy_quirks()
953 	phy_write(phy_data->phydev, 0x00, reg & ~0x00800);  in xgbe_phy_belfuse_phy_quirks()
956 	phy_write(phy_data->phydev, 0x1c, 0x7c00);  in xgbe_phy_belfuse_phy_quirks()
957 	reg = phy_read(phy_data->phydev, 0x1c);  in xgbe_phy_belfuse_phy_quirks()
958 	reg &= 0x03ff;  in xgbe_phy_belfuse_phy_quirks()
959 	reg &= ~0x0001;  in xgbe_phy_belfuse_phy_quirks()
960 	phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg);  in xgbe_phy_belfuse_phy_quirks()
963 	reg = phy_read(phy_data->phydev, 0x00);  in xgbe_phy_belfuse_phy_quirks()
964 	phy_write(phy_data->phydev, 0x00, reg & ~0x00800);  in xgbe_phy_belfuse_phy_quirks()
999 		return 0;  in xgbe_phy_find_phy_device()
1002 	pdata->an_again = 0;  in xgbe_phy_find_phy_device()
1006 		return 0;  in xgbe_phy_find_phy_device()
1011 		return 0;  in xgbe_phy_find_phy_device()
1059 	return 0;  in xgbe_phy_find_phy_device()
1070 	phy_data->sfp_phy_avail = 0;  in xgbe_phy_sfp_external_phy()
1077 	if (ret < 0)  in xgbe_phy_sfp_external_phy()
1204 	sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';  in xgbe_phy_sfp_eeprom_info()
1210 	sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';  in xgbe_phy_sfp_eeprom_info()
1216 	sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';  in xgbe_phy_sfp_eeprom_info()
1222 	sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';  in xgbe_phy_sfp_eeprom_info()
1231 	for (cc = 0; len; buf++, len--)  in xgbe_phy_sfp_verify_eeprom()
1252 	eeprom_addr = 0;  in xgbe_phy_sfp_read_eeprom()
1288 		phy_data->sfp_changed = 0;  in xgbe_phy_sfp_read_eeprom()
1304 	gpio_reg = 0;  in xgbe_phy_sfp_signals()
1314 	phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];  in xgbe_phy_sfp_signals()
1326 	phy_data->sfp_phy_avail = 0;  in xgbe_phy_sfp_mod_absent()
1327 	memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));  in xgbe_phy_sfp_mod_absent()
1332 	phy_data->sfp_rx_los = 0;  in xgbe_phy_sfp_reset()
1333 	phy_data->sfp_tx_fault = 0;  in xgbe_phy_sfp_reset()
1427 	eeprom_addr = 0;  in xgbe_phy_module_eeprom()
1442 		eeprom_addr = 0;  in xgbe_phy_module_eeprom()
1455 	for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) {  in xgbe_phy_module_eeprom()
1498 	return 0;  in xgbe_phy_module_info()
1505 	u16 lcl_adv = 0, rmt_adv = 0;  in xgbe_phy_phydev_flowctrl()
1508 	pdata->phy.tx_pause = 0;  in xgbe_phy_phydev_flowctrl()
1509 	pdata->phy.rx_pause = 0;  in xgbe_phy_phydev_flowctrl()
1584 	if (lp_reg & 0x100)  in xgbe_phy_an37_outcome()
1586 	if (lp_reg & 0x80)  in xgbe_phy_an37_outcome()
1591 		pdata->phy.tx_pause = 0;  in xgbe_phy_an37_outcome()
1592 		pdata->phy.rx_pause = 0;  in xgbe_phy_an37_outcome()
1594 		if (ad_reg & lp_reg & 0x100) {  in xgbe_phy_an37_outcome()
1597 		} else if (ad_reg & lp_reg & 0x80) {  in xgbe_phy_an37_outcome()
1598 			if (ad_reg & 0x100)  in xgbe_phy_an37_outcome()
1600 			else if (lp_reg & 0x100)  in xgbe_phy_an37_outcome()
1605 	if (lp_reg & 0x20)  in xgbe_phy_an37_outcome()
1610 	mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;  in xgbe_phy_an37_outcome()
1632 	if (lp_reg & 0x80)  in xgbe_phy_an73_redrv_outcome()
1634 	if (lp_reg & 0x20)  in xgbe_phy_an73_redrv_outcome()
1638 	if (ad_reg & 0x80) {  in xgbe_phy_an73_redrv_outcome()
1648 	} else if (ad_reg & 0x20) {  in xgbe_phy_an73_redrv_outcome()
1689 	if (lp_reg & 0xc000)  in xgbe_phy_an73_redrv_outcome()
1707 	if (lp_reg & 0x400)  in xgbe_phy_an73_outcome()
1709 	if (lp_reg & 0x800)  in xgbe_phy_an73_outcome()
1714 		pdata->phy.tx_pause = 0;  in xgbe_phy_an73_outcome()
1715 		pdata->phy.rx_pause = 0;  in xgbe_phy_an73_outcome()
1717 		if (ad_reg & lp_reg & 0x400) {  in xgbe_phy_an73_outcome()
1720 		} else if (ad_reg & lp_reg & 0x800) {  in xgbe_phy_an73_outcome()
1721 			if (ad_reg & 0x400)  in xgbe_phy_an73_outcome()
1723 			else if (lp_reg & 0x400)  in xgbe_phy_an73_outcome()
1731 	if (lp_reg & 0x80)  in xgbe_phy_an73_outcome()
1733 	if (lp_reg & 0x20)  in xgbe_phy_an73_outcome()
1737 	if (ad_reg & 0x80)  in xgbe_phy_an73_outcome()
1739 	else if (ad_reg & 0x20)  in xgbe_phy_an73_outcome()
1747 	if (lp_reg & 0xc000)  in xgbe_phy_an73_outcome()
1842 		return 0;  in xgbe_phy_an_config()
1910 	redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);  in xgbe_phy_set_redrv_mode_mdio()
1925 	redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);  in xgbe_phy_set_redrv_mode_i2c()
1994 	unsigned int s0 = 0;  in xgbe_phy_perform_ratechange()
2013 	XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);  in xgbe_phy_perform_ratechange()
2039 	xgbe_phy_perform_ratechange(pdata, 5, 0);  in xgbe_phy_rrc()
2049 	xgbe_phy_perform_ratechange(pdata, 0, 0);  in xgbe_phy_power_off()
2064 		xgbe_phy_perform_ratechange(pdata, 3, 0);  in xgbe_phy_sfi_mode()
2128 	xgbe_phy_perform_ratechange(pdata, 4, 0);  in xgbe_phy_kr_mode()
2142 	xgbe_phy_perform_ratechange(pdata, 2, 0);  in xgbe_phy_kx_2500_mode()
2597 	*an_restart = 0;  in xgbe_phy_link_status()
2605 			return 0;  in xgbe_phy_link_status()
2609 			return 0;  in xgbe_phy_link_status()
2615 		if (ret < 0)  in xgbe_phy_link_status()
2616 			return 0;  in xgbe_phy_link_status()
2620 			return 0;  in xgbe_phy_link_status()
2623 			return 0;  in xgbe_phy_link_status()
2644 		phy_data->rrc_count = 0;  in xgbe_phy_link_status()
2648 	return 0;  in xgbe_phy_link_status()
2745 	gpio_data[0] = 2;  in xgbe_phy_i2c_mdio_reset()
2746 	gpio_data[1] = gpio_ports[0];  in xgbe_phy_i2c_mdio_reset()
2780 		return 0;  in xgbe_phy_mdio_reset()
2825 		return 0;  in xgbe_phy_mdio_reset_setup()
2850 	return 0;  in xgbe_phy_mdio_reset_setup()
2963 	phy_data->phy_cdr_notrack = 0;  in xgbe_phy_cdr_track()
3106 	return 0;  in xgbe_phy_start()
3126 		return 0;  in xgbe_phy_reset()
3371 		dev_dbg(pdata->dev, "phy supported=0x%*pb\n",  in xgbe_phy_init()
3412 	mii->phy_mask = ~0;  in xgbe_phy_init()
3421 	return 0;  in xgbe_phy_init()