Lines Matching +full:0 +full:x209c
28 #define MVPP2_XDP_PASS 0
29 #define MVPP2_XDP_DROPPED BIT(0)
34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
36 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
37 #define MVPP2_RX_FIFO_INIT_REG 0x64
38 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port))
39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))
42 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
43 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
45 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
47 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
48 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
51 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
52 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
54 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
55 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
57 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
61 #define MVPP2_MH_REG(port) (0x5040 + 4 * (port))
65 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
66 #define MVPP2_PRS_PORT_LU_MAX 0xf
67 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
69 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
70 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
72 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
73 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
75 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
76 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
78 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
79 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
80 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
81 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
82 #define MVPP2_PRS_TCAM_HIT_IDX_REG 0x1240
83 #define MVPP2_PRS_TCAM_HIT_CNT_REG 0x1244
84 #define MVPP2_PRS_TCAM_HIT_CNT_MASK GENMASK(15, 0)
87 #define MVPP22_RSS_INDEX 0x1500
91 #define MVPP22_RXQ2RSS_TABLE 0x1504
93 #define MVPP22_RSS_TABLE_ENTRY 0x1508
94 #define MVPP22_RSS_WIDTH 0x150c
97 #define MVPP2_CLS_MODE_REG 0x1800
98 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
99 #define MVPP2_CLS_PORT_WAY_REG 0x1810
101 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
103 #define MVPP2_CLS_LKP_TBL_REG 0x1818
104 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
107 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
108 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
109 #define MVPP2_CLS_FLOW_TBL0_LAST BIT(0)
110 #define MVPP2_CLS_FLOW_TBL0_ENG_MASK 0x7
113 #define MVPP2_CLS_FLOW_TBL0_PORT_ID_MASK 0xff
116 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
117 #define MVPP2_CLS_FLOW_TBL1_N_FIELDS_MASK 0x7
119 #define MVPP2_CLS_FLOW_TBL1_LU_TYPE(lu) (((lu) & 0x3f) << 3)
120 #define MVPP2_CLS_FLOW_TBL1_PRIO_MASK 0x3f
122 #define MVPP2_CLS_FLOW_TBL1_SEQ_MASK 0x7
124 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
125 #define MVPP2_CLS_FLOW_TBL2_FLD_MASK 0x3f
128 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
130 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
131 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
132 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
136 #define MVPP22_CLS_C2_TCAM_IDX 0x1b00
137 #define MVPP22_CLS_C2_TCAM_DATA0 0x1b10
138 #define MVPP22_CLS_C2_TCAM_DATA1 0x1b14
139 #define MVPP22_CLS_C2_TCAM_DATA2 0x1b18
140 #define MVPP22_CLS_C2_TCAM_DATA3 0x1b1c
141 #define MVPP22_CLS_C2_TCAM_DATA4 0x1b20
142 #define MVPP22_CLS_C2_LU_TYPE(lu) ((lu) & 0x3f)
144 #define MVPP22_CLS_C2_PORT_MASK (0xff << 8)
145 #define MVPP22_CLS_C2_TCAM_INV 0x1b24
147 #define MVPP22_CLS_C2_HIT_CTR 0x1b50
148 #define MVPP22_CLS_C2_ACT 0x1b60
149 #define MVPP22_CLS_C2_ACT_RSS_EN(act) (((act) & 0x3) << 19)
150 #define MVPP22_CLS_C2_ACT_FWD(act) (((act) & 0x7) << 13)
151 #define MVPP22_CLS_C2_ACT_QHIGH(act) (((act) & 0x3) << 11)
152 #define MVPP22_CLS_C2_ACT_QLOW(act) (((act) & 0x3) << 9)
153 #define MVPP22_CLS_C2_ACT_COLOR(act) ((act) & 0x7)
154 #define MVPP22_CLS_C2_ATTR0 0x1b64
155 #define MVPP22_CLS_C2_ATTR0_QHIGH(qh) (((qh) & 0x1f) << 24)
156 #define MVPP22_CLS_C2_ATTR0_QHIGH_MASK 0x1f
158 #define MVPP22_CLS_C2_ATTR0_QLOW(ql) (((ql) & 0x7) << 21)
159 #define MVPP22_CLS_C2_ATTR0_QLOW_MASK 0x7
161 #define MVPP22_CLS_C2_ATTR1 0x1b68
162 #define MVPP22_CLS_C2_ATTR2 0x1b6c
164 #define MVPP22_CLS_C2_ATTR3 0x1b70
165 #define MVPP22_CLS_C2_TCAM_CTRL 0x1b90
166 #define MVPP22_CLS_C2_TCAM_BYPASS_FIFO BIT(0)
169 #define MVPP2_RXQ_NUM_REG 0x2040
170 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
172 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
173 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
174 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
175 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
177 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
178 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
180 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
181 #define MVPP2_RXQ_THRESH_REG 0x204c
182 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
183 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
184 #define MVPP2_RXQ_INDEX_REG 0x2050
185 #define MVPP2_TXQ_NUM_REG 0x2080
186 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
187 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
188 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
189 #define MVPP2_TXQ_THRESH_REG 0x2094
191 #define MVPP2_TXQ_THRESH_MASK 0x3fff
192 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
193 #define MVPP2_TXQ_INDEX_REG 0x2098
194 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
195 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
200 #define MVPP2_TXQ_PENDING_REG 0x20a0
201 #define MVPP2_TXQ_PENDING_MASK 0x3fff
202 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
203 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
205 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
206 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
208 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
209 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
210 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
212 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
214 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
215 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
216 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
217 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
218 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
221 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
222 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
223 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
224 #define MVPP2_BASE_ADDR_ENABLE 0x4060
227 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
228 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
229 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
230 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
231 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
232 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
233 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
234 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
235 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
236 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
237 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
238 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
241 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
244 #define MVPP22_AXI_CODE_CACHE_OFFS 0
247 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
248 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
249 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
255 #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port))
256 #define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0
258 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
259 #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0
260 #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port))
262 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
263 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
264 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
267 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
268 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
270 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
271 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
272 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
275 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
276 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
277 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
278 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
280 ((version) == MVPP21 ? 0xffff : 0xff)
281 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
289 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
290 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
291 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
292 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
294 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
297 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
298 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
299 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
300 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
301 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
302 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
303 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
304 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
305 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
306 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
307 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
308 #define MVPP22_BM_POOL_PTRS_NUM_MASK 0xfff8
310 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
311 #define MVPP2_BM_START_MASK BIT(0)
315 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
319 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
322 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
323 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
328 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
329 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
330 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
331 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
332 #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444
333 #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff
334 #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00
336 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
337 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
340 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
341 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
342 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
343 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
347 #define MVPP2_OVERRUN_ETH_DROP 0x7000
348 #define MVPP2_CLS_ETH_DROP 0x7020
351 #define MVPP2_CTRS_IDX 0x7040
353 #define MVPP2_TX_DESC_ENQ_CTR 0x7100
354 #define MVPP2_TX_DESC_ENQ_TO_DDR_CTR 0x7104
355 #define MVPP2_TX_BUFF_ENQ_TO_DDR_CTR 0x7108
356 #define MVPP2_TX_DESC_ENQ_HW_FWD_CTR 0x710c
357 #define MVPP2_RX_DESC_ENQ_CTR 0x7120
358 #define MVPP2_TX_PKTS_DEQ_CTR 0x7130
359 #define MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR 0x7200
360 #define MVPP2_TX_PKTS_EARLY_DROP_CTR 0x7204
361 #define MVPP2_TX_PKTS_BM_DROP_CTR 0x7208
362 #define MVPP2_TX_PKTS_BM_MC_DROP_CTR 0x720c
363 #define MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR 0x7220
364 #define MVPP2_RX_PKTS_EARLY_DROP_CTR 0x7224
365 #define MVPP2_RX_PKTS_BM_DROP_CTR 0x7228
366 #define MVPP2_CLS_DEC_TBL_HIT_CTR 0x7700
367 #define MVPP2_CLS_FLOW_TBL_HIT_CTR 0x7704
370 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
371 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
372 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
374 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
375 #define MVPP2_TXP_SCHED_FIXED_PRIO_REG 0x8014
376 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
377 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
378 #define MVPP2_TXP_MTU_MAX 0x7FFFF
379 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
380 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
381 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
383 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
384 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
385 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
386 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
387 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
389 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
390 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
391 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
392 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
395 #define MVPP2_TX_SNOOP_REG 0x8800
396 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
400 #define MVPP2_SRC_ADDR_MIDDLE 0x24
401 #define MVPP2_SRC_ADDR_HIGH 0x28
402 #define MVPP2_PHY_AN_CFG0_REG 0x34
404 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
405 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
408 #define MVPP2_GMAC_CTRL_0_REG 0x0
409 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
412 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
414 #define MVPP2_GMAC_CTRL_1_REG 0x4
420 #define MVPP2_GMAC_CTRL_2_REG 0x8
421 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
427 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
428 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
441 #define MVPP2_GMAC_STATUS0 0x10
442 #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0)
449 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
451 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
454 #define MVPP22_GMAC_INT_STAT 0x20
456 #define MVPP22_GMAC_INT_MASK 0x24
458 #define MVPP22_GMAC_CTRL_4_REG 0x90
459 #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0)
465 #define MVPP22_GMAC_INT_SUM_STAT 0xa0
468 #define MVPP22_GMAC_INT_SUM_MASK 0xa4
472 /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
475 #define MVPP22_XLG_CTRL0_REG 0x100
476 #define MVPP22_XLG_CTRL0_PORT_EN BIT(0)
483 #define MVPP22_XLG_CTRL1_REG 0x104
484 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0
485 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff
486 #define MVPP22_XLG_STATUS 0x10c
487 #define MVPP22_XLG_STATUS_LINK_UP BIT(0)
488 #define MVPP22_XLG_INT_STAT 0x114
490 #define MVPP22_XLG_INT_MASK 0x118
492 #define MVPP22_XLG_CTRL3_REG 0x11c
494 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
496 #define MVPP22_XLG_EXT_INT_STAT 0x158
499 #define MVPP22_XLG_EXT_INT_MASK 0x15c
503 #define MVPP22_XLG_CTRL4_REG 0x184
510 #define MVPP22_SMI_MISC_CFG_REG 0x1204
514 #define MVPP22_TAI_INT_CAUSE 0x1400
515 #define MVPP22_TAI_INT_MASK 0x1404
516 #define MVPP22_TAI_CR0 0x1408
517 #define MVPP22_TAI_CR1 0x140c
518 #define MVPP22_TAI_TCFCR0 0x1410
519 #define MVPP22_TAI_TCFCR1 0x1414
520 #define MVPP22_TAI_TCFCR2 0x1418
521 #define MVPP22_TAI_FATWR 0x141c
522 #define MVPP22_TAI_TOD_STEP_NANO_CR 0x1420
523 #define MVPP22_TAI_TOD_STEP_FRAC_HIGH 0x1424
524 #define MVPP22_TAI_TOD_STEP_FRAC_LOW 0x1428
525 #define MVPP22_TAI_TAPDC_HIGH 0x142c
526 #define MVPP22_TAI_TAPDC_LOW 0x1430
527 #define MVPP22_TAI_TGTOD_SEC_HIGH 0x1434
528 #define MVPP22_TAI_TGTOD_SEC_MED 0x1438
529 #define MVPP22_TAI_TGTOD_SEC_LOW 0x143c
530 #define MVPP22_TAI_TGTOD_NANO_HIGH 0x1440
531 #define MVPP22_TAI_TGTOD_NANO_LOW 0x1444
532 #define MVPP22_TAI_TGTOD_FRAC_HIGH 0x1448
533 #define MVPP22_TAI_TGTOD_FRAC_LOW 0x144c
534 #define MVPP22_TAI_TLV_SEC_HIGH 0x1450
535 #define MVPP22_TAI_TLV_SEC_MED 0x1454
536 #define MVPP22_TAI_TLV_SEC_LOW 0x1458
537 #define MVPP22_TAI_TLV_NANO_HIGH 0x145c
538 #define MVPP22_TAI_TLV_NANO_LOW 0x1460
539 #define MVPP22_TAI_TLV_FRAC_HIGH 0x1464
540 #define MVPP22_TAI_TLV_FRAC_LOW 0x1468
541 #define MVPP22_TAI_TCV0_SEC_HIGH 0x146c
542 #define MVPP22_TAI_TCV0_SEC_MED 0x1470
543 #define MVPP22_TAI_TCV0_SEC_LOW 0x1474
544 #define MVPP22_TAI_TCV0_NANO_HIGH 0x1478
545 #define MVPP22_TAI_TCV0_NANO_LOW 0x147c
546 #define MVPP22_TAI_TCV0_FRAC_HIGH 0x1480
547 #define MVPP22_TAI_TCV0_FRAC_LOW 0x1484
548 #define MVPP22_TAI_TCV1_SEC_HIGH 0x1488
549 #define MVPP22_TAI_TCV1_SEC_MED 0x148c
550 #define MVPP22_TAI_TCV1_SEC_LOW 0x1490
551 #define MVPP22_TAI_TCV1_NANO_HIGH 0x1494
552 #define MVPP22_TAI_TCV1_NANO_LOW 0x1498
553 #define MVPP22_TAI_TCV1_FRAC_HIGH 0x149c
554 #define MVPP22_TAI_TCV1_FRAC_LOW 0x14a0
555 #define MVPP22_TAI_TCSR 0x14a4
556 #define MVPP22_TAI_TUC_LSB 0x14a8
557 #define MVPP22_TAI_GFM_SEC_HIGH 0x14ac
558 #define MVPP22_TAI_GFM_SEC_MED 0x14b0
559 #define MVPP22_TAI_GFM_SEC_LOW 0x14b4
560 #define MVPP22_TAI_GFM_NANO_HIGH 0x14b8
561 #define MVPP22_TAI_GFM_NANO_LOW 0x14bc
562 #define MVPP22_TAI_GFM_FRAC_HIGH 0x14c0
563 #define MVPP22_TAI_GFM_FRAC_LOW 0x14c4
564 #define MVPP22_TAI_PCLK_DA_HIGH 0x14c8
565 #define MVPP22_TAI_PCLK_DA_LOW 0x14cc
566 #define MVPP22_TAI_CTCR 0x14d0
567 #define MVPP22_TAI_PCLK_CCC_HIGH 0x14d4
568 #define MVPP22_TAI_PCLK_CCC_LOW 0x14d8
569 #define MVPP22_TAI_DTC_HIGH 0x14dc
570 #define MVPP22_TAI_DTC_LOW 0x14e0
571 #define MVPP22_TAI_CCC_HIGH 0x14e4
572 #define MVPP22_TAI_CCC_LOW 0x14e8
573 #define MVPP22_TAI_ICICE 0x14f4
574 #define MVPP22_TAI_ICICC_LOW 0x14f8
575 #define MVPP22_TAI_TUC_MSB 0x14fc
577 #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00)
579 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
583 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
586 #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000)
587 #define MVPP22_MPCS_CTRL 0x14
589 #define MVPP22_MPCS_CLK_RESET 0x14c
590 #define MAC_CLK_RESET_SD_TX BIT(0)
597 #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)
598 #define MVPP22_XPCS_CFG0 0x0
599 #define MVPP22_XPCS_CFG0_RESET_DIS BIT(0)
604 #define MVPP22_PTP_BASE(port) (0x7800 + (port * 0x1000))
605 #define MVPP22_PTP_INT_CAUSE 0x00
608 #define MVPP22_PTP_INT_MASK 0x04
611 #define MVPP22_PTP_GCR 0x08
614 #define MVPP22_PTP_GCR_TSU_ENABLE BIT(0)
615 #define MVPP22_PTP_TX_Q0_R0 0x0c
616 #define MVPP22_PTP_TX_Q0_R1 0x10
617 #define MVPP22_PTP_TX_Q0_R2 0x14
618 #define MVPP22_PTP_TX_Q1_R0 0x18
619 #define MVPP22_PTP_TX_Q1_R1 0x1c
620 #define MVPP22_PTP_TX_Q1_R2 0x20
621 #define MVPP22_PTP_TPCR 0x24
622 #define MVPP22_PTP_V1PCR 0x28
623 #define MVPP22_PTP_V2PCR 0x2c
624 #define MVPP22_PTP_Y1731PCR 0x30
625 #define MVPP22_PTP_NTPTSPCR 0x34
626 #define MVPP22_PTP_NTPRXPCR 0x38
627 #define MVPP22_PTP_NTPTXPCR 0x3c
628 #define MVPP22_PTP_WAMPPCR 0x40
629 #define MVPP22_PTP_NAPCR 0x44
630 #define MVPP22_PTP_FAPCR 0x48
631 #define MVPP22_PTP_CAPCR 0x50
632 #define MVPP22_PTP_ATAPCR 0x54
633 #define MVPP22_PTP_ACTAPCR 0x58
634 #define MVPP22_PTP_CATAPCR 0x5c
635 #define MVPP22_PTP_CACTAPCR 0x60
636 #define MVPP22_PTP_AITAPCR 0x64
637 #define MVPP22_PTP_CAITAPCR 0x68
638 #define MVPP22_PTP_CITAPCR 0x6c
639 #define MVPP22_PTP_NTP_OFF_HIGH 0x70
640 #define MVPP22_PTP_NTP_OFF_LOW 0x74
641 #define MVPP22_PTP_TX_PIPE_STATUS_DELAY 0x78
644 #define GENCONF_SOFT_RESET1 0x1108
646 #define GENCONF_PORT_CTRL0 0x1110
650 #define GENCONF_PORT_CTRL1 0x1114
653 #define GENCONF_CTRL0 0x1120
654 #define GENCONF_CTRL0_PORT0_RGMII BIT(0)
682 #define MVPP2_IP_LBDT_TYPE 0xfffa
690 #define MVPP2_TX_MTU_MAX 0x7ffff
732 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000
733 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000
734 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000
735 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200
736 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80
737 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40
738 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
741 #define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa
742 #define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3
782 #define MVPP2_F_LOOPBACK BIT(0)
787 MVPP2_TAG_TYPE_NONE = 0,
811 #define MVPP22_PTP_DESC_MASK_LOW 0xfff
815 MVPP22_PTP_ACTION_NONE = 0,
830 MVPP22_PTP_PKT_FMT_PTPV2 = 0,
839 #define MVPP22_PTP_ACTION(x) (((x) & 15) << 0)
868 #define MVPP21_ADDR_SPACE_SZ 0
875 #define MVPP21_MIB_COUNTERS_OFFSET 0x1000
876 #define MVPP21_MIB_COUNTERS_PORT_SZ 0x400
877 #define MVPP22_MIB_COUNTERS_OFFSET 0x0
878 #define MVPP22_MIB_COUNTERS_PORT_SZ 0x100
880 #define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0
881 #define MVPP2_MIB_BAD_OCTETS_RCVD 0x8
882 #define MVPP2_MIB_CRC_ERRORS_SENT 0xc
883 #define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10
884 #define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18
885 #define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c
886 #define MVPP2_MIB_FRAMES_64_OCTETS 0x20
887 #define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24
888 #define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28
889 #define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c
890 #define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30
891 #define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
892 #define MVPP2_MIB_GOOD_OCTETS_SENT 0x38
893 #define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40
894 #define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48
895 #define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c
896 #define MVPP2_MIB_FC_SENT 0x54
897 #define MVPP2_MIB_FC_RCVD 0x58
898 #define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c
899 #define MVPP2_MIB_UNDERSIZE_RCVD 0x60
900 #define MVPP2_MIB_FRAGMENTS_RCVD 0x64
901 #define MVPP2_MIB_OVERSIZE_RCVD 0x68
902 #define MVPP2_MIB_JABBER_RCVD 0x6c
903 #define MVPP2_MIB_MAC_RCV_ERROR 0x70
904 #define MVPP2_MIB_BAD_CRC_EVENT 0x74
905 #define MVPP2_MIB_COLLISION 0x78
906 #define MVPP2_MIB_LATE_COLLISION 0x7c
913 #define MVPP2_B_HDR_INFO_MC_ID_MASK 0xfff
1170 * them from 0
1185 #define MVPP2_TXD_L3_OFF_SHIFT 0
1198 #define MVPP2_RXD_ERR_CRC 0x0
1366 /* RX queue number, in the range 0-31 for physical RXQs */
1399 /* Pool number in the range 0-7 */
1449 return 0; in mvpp22_tai_probe()