Lines Matching full:dram
87 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
88 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
89 * from going into a power-savings mode that would cause higher DRAM latency,
95 * be sufficient to maintain fast DRAM response.
106 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
109 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
157 * In case of DRAM read address which is not aligned to 128B, the TFH will
158 * enable transfer size which doesn't cross 64B DRAM address boundary.
166 * Tx CMD which will be updated in DRAM.
169 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID
179 * Note that the sram2dram may be enabled only after configuring the DRAM and
193 /* Defines the 64bits DRAM start address to read the DMA data block from */
197 * Defines the number of bytes to transfer from DRAM to SRAM.
209 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
213 * Driver must allocate host DRAM memory for the following, and set the
254 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
256 * read this "read" index from DRAM after receiving an Rx interrupt from device
422 * DRAM.
424 * RBD read response from DRAM), this flag is immediately turned off.
428 * SRAM to DRAM.
429 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off.
433 * RXF to DRAM.
434 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off.
503 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
697 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
707 * in host DRAM. These buffers collectively contain the (one) frame described
709 * itself, but buffers may be scattered in host DRAM. Each buffer has max size