Lines Matching +full:ecam +full:- +full:based
1 // SPDX-License-Identifier: GPL-2.0+
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
32 /* Egress - Bridge translation registers */
42 /* Ingress - address translations */
50 /* Rxed msg fifo - Interrupt status registers */
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
202 struct device *dev = pcie->dev; in nwl_wait_for_link()
213 return -ETIMEDOUT; in nwl_wait_for_link()
218 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_valid_device()
232 * nwl_pcie_map_bus - Get configuration base
244 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_map_bus()
250 relbus = (bus->number << ECAM_BUS_LOC_SHIFT) | in nwl_pcie_map_bus()
253 return pcie->ecam_base + relbus + where; in nwl_pcie_map_bus()
266 struct device *dev = pcie->dev; in nwl_pcie_misc_handler()
294 dev_err(dev, "Non-Fatal Error in AER Capability\n"); in nwl_pcie_misc_handler()
303 dev_err(dev, "Non-Fatal Error Detected\n"); in nwl_pcie_misc_handler()
334 virq = irq_find_mapping(pcie->legacy_irq_domain, bit); in nwl_pcie_leg_handler()
350 msi = &pcie->msi; in nwl_pcie_handle_msi_irq()
355 virq = irq_find_mapping(msi->dev_domain, bit); in nwl_pcie_handle_msi_irq()
384 struct irq_desc *desc = irq_to_desc(data->irq); in nwl_mask_leg_irq()
391 mask = 1 << (data->hwirq - 1); in nwl_mask_leg_irq()
392 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_mask_leg_irq()
395 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_mask_leg_irq()
400 struct irq_desc *desc = irq_to_desc(data->irq); in nwl_unmask_leg_irq()
407 mask = 1 << (data->hwirq - 1); in nwl_unmask_leg_irq()
408 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_unmask_leg_irq()
411 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_unmask_leg_irq()
426 irq_set_chip_data(irq, domain->host_data); in nwl_legacy_map()
456 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; in nwl_compose_msi_msg()
458 msg->address_lo = lower_32_bits(msi_addr); in nwl_compose_msi_msg()
459 msg->address_hi = upper_32_bits(msi_addr); in nwl_compose_msi_msg()
460 msg->data = data->hwirq; in nwl_compose_msi_msg()
466 return -EINVAL; in nwl_msi_set_affinity()
478 struct nwl_pcie *pcie = domain->host_data; in nwl_irq_domain_alloc()
479 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_alloc()
483 mutex_lock(&msi->lock); in nwl_irq_domain_alloc()
484 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR, in nwl_irq_domain_alloc()
487 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
488 return -ENOSPC; in nwl_irq_domain_alloc()
493 domain->host_data, handle_simple_irq, in nwl_irq_domain_alloc()
496 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
505 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_free()
507 mutex_lock(&msi->lock); in nwl_irq_domain_free()
508 bitmap_release_region(msi->bitmap, data->hwirq, in nwl_irq_domain_free()
510 mutex_unlock(&msi->lock); in nwl_irq_domain_free()
521 struct device *dev = pcie->dev; in nwl_pcie_init_msi_irq_domain()
522 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); in nwl_pcie_init_msi_irq_domain()
523 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_init_msi_irq_domain()
525 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR, in nwl_pcie_init_msi_irq_domain()
527 if (!msi->dev_domain) { in nwl_pcie_init_msi_irq_domain()
529 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
531 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in nwl_pcie_init_msi_irq_domain()
533 msi->dev_domain); in nwl_pcie_init_msi_irq_domain()
534 if (!msi->msi_domain) { in nwl_pcie_init_msi_irq_domain()
536 irq_domain_remove(msi->dev_domain); in nwl_pcie_init_msi_irq_domain()
537 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
545 struct device *dev = pcie->dev; in nwl_pcie_init_irq_domain()
546 struct device_node *node = dev->of_node; in nwl_pcie_init_irq_domain()
552 return -EINVAL; in nwl_pcie_init_irq_domain()
555 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node, in nwl_pcie_init_irq_domain()
560 if (!pcie->legacy_irq_domain) { in nwl_pcie_init_irq_domain()
562 return -ENOMEM; in nwl_pcie_init_irq_domain()
565 raw_spin_lock_init(&pcie->leg_mask_lock); in nwl_pcie_init_irq_domain()
572 struct device *dev = pcie->dev; in nwl_pcie_enable_msi()
574 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_enable_msi()
579 mutex_init(&msi->lock); in nwl_pcie_enable_msi()
581 msi->bitmap = kzalloc(size, GFP_KERNEL); in nwl_pcie_enable_msi()
582 if (!msi->bitmap) in nwl_pcie_enable_msi()
583 return -ENOMEM; in nwl_pcie_enable_msi()
586 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1"); in nwl_pcie_enable_msi()
587 if (msi->irq_msi1 < 0) { in nwl_pcie_enable_msi()
588 ret = -EINVAL; in nwl_pcie_enable_msi()
592 irq_set_chained_handler_and_data(msi->irq_msi1, in nwl_pcie_enable_msi()
596 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0"); in nwl_pcie_enable_msi()
597 if (msi->irq_msi0 < 0) { in nwl_pcie_enable_msi()
598 ret = -EINVAL; in nwl_pcie_enable_msi()
602 irq_set_chained_handler_and_data(msi->irq_msi0, in nwl_pcie_enable_msi()
609 ret = -EIO; in nwl_pcie_enable_msi()
622 base = pcie->phys_pcie_reg_base; in nwl_pcie_enable_msi()
650 kfree(msi->bitmap); in nwl_pcie_enable_msi()
651 msi->bitmap = NULL; in nwl_pcie_enable_msi()
657 struct device *dev = pcie->dev; in nwl_pcie_bridge_init()
669 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
671 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
695 dev_err(dev, "ECAM is not present\n"); in nwl_pcie_bridge_init()
699 /* Enable ECAM */ in nwl_pcie_bridge_init()
704 (pcie->ecam_value << E_ECAM_SIZE_SHIFT), in nwl_pcie_bridge_init()
707 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
709 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
714 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; in nwl_pcie_bridge_init()
718 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); in nwl_pcie_bridge_init()
719 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); in nwl_pcie_bridge_init()
727 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); in nwl_pcie_bridge_init()
728 if (pcie->irq_misc < 0) in nwl_pcie_bridge_init()
729 return -EINVAL; in nwl_pcie_bridge_init()
731 err = devm_request_irq(dev, pcie->irq_misc, in nwl_pcie_bridge_init()
736 pcie->irq_misc); in nwl_pcie_bridge_init()
771 struct device *dev = pcie->dev; in nwl_pcie_parse_dt()
775 pcie->breg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
776 if (IS_ERR(pcie->breg_base)) in nwl_pcie_parse_dt()
777 return PTR_ERR(pcie->breg_base); in nwl_pcie_parse_dt()
778 pcie->phys_breg_base = res->start; in nwl_pcie_parse_dt()
781 pcie->pcireg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
782 if (IS_ERR(pcie->pcireg_base)) in nwl_pcie_parse_dt()
783 return PTR_ERR(pcie->pcireg_base); in nwl_pcie_parse_dt()
784 pcie->phys_pcie_reg_base = res->start; in nwl_pcie_parse_dt()
787 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); in nwl_pcie_parse_dt()
788 if (IS_ERR(pcie->ecam_base)) in nwl_pcie_parse_dt()
789 return PTR_ERR(pcie->ecam_base); in nwl_pcie_parse_dt()
790 pcie->phys_ecam_base = res->start; in nwl_pcie_parse_dt()
793 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); in nwl_pcie_parse_dt()
794 if (pcie->irq_intx < 0) in nwl_pcie_parse_dt()
795 return pcie->irq_intx; in nwl_pcie_parse_dt()
797 irq_set_chained_handler_and_data(pcie->irq_intx, in nwl_pcie_parse_dt()
804 { .compatible = "xlnx,nwl-pcie-2.11", },
810 struct device *dev = &pdev->dev; in nwl_pcie_probe()
817 return -ENODEV; in nwl_pcie_probe()
821 pcie->dev = dev; in nwl_pcie_probe()
822 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; in nwl_pcie_probe()
830 pcie->clk = devm_clk_get(dev, NULL); in nwl_pcie_probe()
831 if (IS_ERR(pcie->clk)) in nwl_pcie_probe()
832 return PTR_ERR(pcie->clk); in nwl_pcie_probe()
834 err = clk_prepare_enable(pcie->clk); in nwl_pcie_probe()
852 bridge->sysdata = pcie; in nwl_pcie_probe()
853 bridge->ops = &nwl_pcie_ops; in nwl_pcie_probe()
868 .name = "nwl-pcie",