Lines Matching +full:broken +full:- +full:prefetch +full:- +full:cmd
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
66 unsigned int delay = dev->d3hot_delay; in pci_dev_d3_sleep()
91 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
102 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
119 * measured in 32-bit words, not bytes.
164 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
175 max = bus->busn_res.end; in pci_bus_max_busnr()
176 list_for_each_entry(tmp, &bus->children, node) { in pci_bus_max_busnr()
186 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
198 return -EIO; in pci_status_get_and_clear_errors()
211 struct resource *res = &pdev->resource[bar]; in pci_ioremap_bar()
216 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { in pci_ioremap_bar()
220 return ioremap(res->start, resource_size(res)); in pci_ioremap_bar()
240 * pci_dev_str_match_path - test if a path string matches a device
251 * A path for a device can be obtained using 'lspci -t'. Using a path
268 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC); in pci_dev_str_match_path()
270 return -ENOMEM; in pci_dev_str_match_path()
278 ret = -EINVAL; in pci_dev_str_match_path()
282 if (dev->devfn != PCI_DEVFN(slot, func)) { in pci_dev_str_match_path()
308 ret = -EINVAL; in pci_dev_str_match_path()
313 ret = (seg == pci_domain_nr(dev->bus) && in pci_dev_str_match_path()
314 bus == dev->bus->number && in pci_dev_str_match_path()
315 dev->devfn == PCI_DEVFN(slot, func)); in pci_dev_str_match_path()
323 * pci_dev_str_match - test if a string matches a device
340 * through the use of 'lspci -t'.
345 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
367 return -EINVAL; in pci_dev_str_match()
375 if ((!vendor || vendor == dev->vendor) && in pci_dev_str_match()
376 (!device || device == dev->device) && in pci_dev_str_match()
378 subsystem_vendor == dev->subsystem_vendor) && in pci_dev_str_match()
380 subsystem_device == dev->subsystem_device)) in pci_dev_str_match()
410 while ((*ttl)--) { in __pci_find_next_cap_ttl()
436 return __pci_find_next_cap(dev->bus, dev->devfn, in pci_find_next_capability()
462 * pci_find_capability - query for devices' capabilities
477 * %PCI_CAP_ID_PCIX PCI-X
484 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_capability()
486 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); in pci_find_capability()
493 * pci_bus_find_capability - query for devices' capabilities
521 * pci_find_next_ext_capability - Find an extended capability
529 * vendor-specific capability, and this provides a way to find them all.
538 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; in pci_find_next_ext_capability()
540 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) in pci_find_next_ext_capability()
556 while (ttl-- > 0) { in pci_find_next_ext_capability()
573 * pci_find_ext_capability - Find an extended capability
593 * pci_get_dsn - Read and return the 8-byte Device Serial Number
636 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, in __pci_find_next_ht_cap()
646 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, in __pci_find_next_ht_cap()
654 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
663 * NB. To be 100% safe against broken PCI devices, the caller should take
673 * pci_find_ht_capability - query a device's Hypertransport capabilities
687 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_ht_capability()
696 * pci_find_parent_resource - return resource region of parent bus of given
707 const struct pci_bus *bus = dev->bus; in pci_find_parent_resource()
720 if (r->flags & IORESOURCE_PREFETCH && in pci_find_parent_resource()
721 !(res->flags & IORESOURCE_PREFETCH)) in pci_find_parent_resource()
726 * be both a positively-decoded aperture and a in pci_find_parent_resource()
727 * subtractively-decoded region that contain the BAR. in pci_find_parent_resource()
728 * We want the positively-decoded one, so this depends in pci_find_parent_resource()
740 * pci_find_resource - Return matching PCI device resource
753 struct resource *r = &dev->resource[i]; in pci_find_resource()
755 if (r->start && resource_contains(r, res)) in pci_find_resource()
764 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
779 msleep((1 << (i - 1)) * 100); in pci_wait_for_pending()
792 * pci_request_acs - ask for ACS to be enabled if supported
802 * pci_disable_acs_redir - disable ACS redirect capabilities
843 pos = dev->acs_cap; in pci_disable_acs_redir()
860 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
869 pos = dev->acs_cap; in pci_std_enable_acs()
889 if (dev->external_facing || dev->untrusted) in pci_std_enable_acs()
896 * pci_enable_acs - enable ACS if hardware support it
921 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
939 if (!ops->is_manageable || !ops->set_state || !ops->get_state || in pci_set_platform_pm()
940 !ops->choose_state || !ops->set_wakeup || !ops->need_resume) in pci_set_platform_pm()
941 return -EINVAL; in pci_set_platform_pm()
948 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; in platform_pci_power_manageable()
954 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; in platform_pci_set_power_state()
959 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN; in platform_pci_get_power_state()
964 if (pci_platform_pm && pci_platform_pm->refresh_state) in platform_pci_refresh_power_state()
965 pci_platform_pm->refresh_state(dev); in platform_pci_refresh_power_state()
971 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; in platform_pci_choose_state()
977 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV; in platform_pci_set_wakeup()
982 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; in platform_pci_need_resume()
987 if (pci_platform_pm && pci_platform_pm->bridge_d3) in platform_pci_bridge_d3()
988 return pci_platform_pm->bridge_d3(dev); in platform_pci_bridge_d3()
993 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
999 * -EINVAL if the requested state is invalid.
1000 * -EIO if device does not support PCI PM or its PM capabilities register has a
1011 if (dev->current_state == state) in pci_raw_set_power_state()
1014 if (!dev->pm_cap) in pci_raw_set_power_state()
1015 return -EIO; in pci_raw_set_power_state()
1018 return -EINVAL; in pci_raw_set_power_state()
1022 * we're already in a low-power state, we can only go deeper. E.g., in pci_raw_set_power_state()
1026 if (state != PCI_D0 && dev->current_state <= PCI_D3cold in pci_raw_set_power_state()
1027 && dev->current_state > state) { in pci_raw_set_power_state()
1029 pci_power_name(dev->current_state), in pci_raw_set_power_state()
1031 return -EINVAL; in pci_raw_set_power_state()
1035 if ((state == PCI_D1 && !dev->d1_support) in pci_raw_set_power_state()
1036 || (state == PCI_D2 && !dev->d2_support)) in pci_raw_set_power_state()
1037 return -EIO; in pci_raw_set_power_state()
1039 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_raw_set_power_state()
1042 pci_power_name(dev->current_state), in pci_raw_set_power_state()
1044 return -EIO; in pci_raw_set_power_state()
1052 switch (dev->current_state) { in pci_raw_set_power_state()
1061 case PCI_UNKNOWN: /* Boot-up */ in pci_raw_set_power_state()
1072 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_raw_set_power_state()
1078 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) in pci_raw_set_power_state()
1080 else if (state == PCI_D2 || dev->current_state == PCI_D2) in pci_raw_set_power_state()
1083 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_raw_set_power_state()
1084 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); in pci_raw_set_power_state()
1085 if (dev->current_state != state) in pci_raw_set_power_state()
1087 pci_power_name(dev->current_state), in pci_raw_set_power_state()
1106 if (dev->bus->self) in pci_raw_set_power_state()
1107 pcie_aspm_pm_state_change(dev->bus->self); in pci_raw_set_power_state()
1113 * pci_update_current_state - Read power state of given device and cache it
1128 dev->current_state = PCI_D3cold; in pci_update_current_state()
1129 } else if (dev->pm_cap) { in pci_update_current_state()
1132 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_update_current_state()
1133 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); in pci_update_current_state()
1135 dev->current_state = state; in pci_update_current_state()
1140 * pci_refresh_power_state - Refresh the given device's power state data
1151 pci_update_current_state(dev, dev->current_state); in pci_refresh_power_state()
1155 * pci_platform_power_transition - Use platform to change device power state
1168 error = -ENODEV; in pci_platform_power_transition()
1170 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ in pci_platform_power_transition()
1171 dev->current_state = PCI_D0; in pci_platform_power_transition()
1178 * pci_wakeup - Wake up a PCI device
1185 pm_request_resume(&pci_dev->dev); in pci_wakeup()
1190 * pci_wakeup_bus - Walk given bus and wake up devices on it
1212 * Wait for the device to return a non-CRS completion. Read the in pci_dev_wait()
1220 delay - 1, reset_type); in pci_dev_wait()
1221 return -ENOTTY; in pci_dev_wait()
1226 delay - 1, reset_type); in pci_dev_wait()
1234 pci_info(dev, "ready %dms after %s\n", delay - 1, in pci_dev_wait()
1241 * pci_power_up - Put the given device into D0
1253 if (dev->runtime_d3cold) { in pci_power_up()
1259 pci_wakeup_bus(dev->subordinate); in pci_power_up()
1266 * __pci_dev_set_current_state - Set current state of a PCI device
1274 dev->current_state = state; in __pci_dev_set_current_state()
1279 * pci_bus_set_current_state - Walk given bus and set current state of devices
1290 * pci_set_power_state - Set the power state of a PCI device
1298 * -EINVAL if the requested state is invalid.
1299 * -EIO if device does not support PCI PM or its PM capabilities register has a
1326 if (dev->current_state == state) in pci_set_power_state()
1336 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) in pci_set_power_state()
1351 pci_bus_set_current_state(dev->subordinate, PCI_D3cold); in pci_set_power_state()
1358 * pci_choose_state - Choose the power state of a PCI device
1370 if (!dev->pm_cap) in pci_choose_state()
1382 /* REVISIT both freeze and pre-thaw "should" use D0 */ in pci_choose_state()
1402 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { in _pci_find_saved_cap()
1403 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) in _pci_find_saved_cap()
1431 return -ENOMEM; in pci_save_pcie_state()
1434 cap = (u16 *)&save_state->cap.data[0]; in pci_save_pcie_state()
1456 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcie_state()
1478 return -ENOMEM; in pci_save_pcix_state()
1482 (u16 *)save_state->cap.data); in pci_save_pcix_state()
1497 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcix_state()
1521 cap = (u16 *)&save_state->cap.data[0]; in pci_save_ltr_state()
1537 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_ltr_state()
1543 * pci_save_state - save the PCI configuration space of a device before
1552 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); in pci_save_state()
1554 i * 4, dev->saved_config_space[i]); in pci_save_state()
1556 dev->state_saved = true; in pci_save_state()
1586 if (retry-- <= 0) in pci_restore_config_dword()
1603 for (index = end; index >= start; index--) in pci_restore_config_space_range()
1605 pdev->saved_config_space[index], in pci_restore_config_space_range()
1611 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { in pci_restore_config_space()
1616 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_restore_config_space()
1620 * Force rewriting of prefetch registers to avoid S3 resume in pci_restore_config_space()
1650 res = pdev->resource + bar_idx; in pci_restore_rebar_state()
1651 size = ilog2(resource_size(res)) - 20; in pci_restore_rebar_state()
1659 * pci_restore_state - Restore the saved state of a PCI device
1664 if (!dev->state_saved) in pci_restore_state()
1693 dev->state_saved = false; in pci_restore_state()
1703 * pci_store_saved_state - Allocate and return an opaque struct containing
1716 if (!dev->state_saved) in pci_store_saved_state()
1721 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) in pci_store_saved_state()
1722 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1728 memcpy(state->config_space, dev->saved_config_space, in pci_store_saved_state()
1729 sizeof(state->config_space)); in pci_store_saved_state()
1731 cap = state->cap; in pci_store_saved_state()
1732 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { in pci_store_saved_state()
1733 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1734 memcpy(cap, &tmp->cap, len); in pci_store_saved_state()
1744 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1753 dev->state_saved = false; in pci_load_saved_state()
1758 memcpy(dev->saved_config_space, state->config_space, in pci_load_saved_state()
1759 sizeof(state->config_space)); in pci_load_saved_state()
1761 cap = state->cap; in pci_load_saved_state()
1762 while (cap->size) { in pci_load_saved_state()
1765 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); in pci_load_saved_state()
1766 if (!tmp || tmp->cap.size != cap->size) in pci_load_saved_state()
1767 return -EINVAL; in pci_load_saved_state()
1769 memcpy(tmp->cap.data, cap->data, tmp->cap.size); in pci_load_saved_state()
1771 sizeof(struct pci_cap_saved_data) + cap->size); in pci_load_saved_state()
1774 dev->state_saved = true; in pci_load_saved_state()
1780 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1804 u16 cmd; in do_pci_enable_device() local
1808 if (err < 0 && err != -EIO) in do_pci_enable_device()
1820 if (dev->msi_enabled || dev->msix_enabled) in do_pci_enable_device()
1825 pci_read_config_word(dev, PCI_COMMAND, &cmd); in do_pci_enable_device()
1826 if (cmd & PCI_COMMAND_INTX_DISABLE) in do_pci_enable_device()
1828 cmd & ~PCI_COMMAND_INTX_DISABLE); in do_pci_enable_device()
1835 * pci_reenable_device - Resume abandoned device
1844 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); in pci_reenable_device()
1859 if (!dev->is_busmaster) in pci_enable_bridge()
1883 pci_update_current_state(dev, dev->current_state); in pci_enable_device_flags()
1885 if (atomic_inc_return(&dev->enable_cnt) > 1) in pci_enable_device_flags()
1894 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
1897 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
1902 atomic_dec(&dev->enable_cnt); in pci_enable_device_flags()
1907 * pci_enable_device_io - Initialize a device for use with IO space
1910 * Initialize device before it's used by a driver. Ask low-level code
1921 * pci_enable_device_mem - Initialize a device for use with Memory space
1924 * Initialize device before it's used by a driver. Ask low-level code
1935 * pci_enable_device - Initialize device before it's used by a driver.
1938 * Initialize device before it's used by a driver. Ask low-level code
1952 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
1953 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
1972 if (dev->msi_enabled) in pcim_release()
1974 if (dev->msix_enabled) in pcim_release()
1978 if (this->region_mask & (1 << i)) in pcim_release()
1981 if (this->mwi) in pcim_release()
1984 if (this->restore_intx) in pcim_release()
1985 pci_intx(dev, this->orig_intx); in pcim_release()
1987 if (this->enabled && !this->pinned) in pcim_release()
1995 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); in get_pci_dr()
2002 return devres_get(&pdev->dev, new_dr, NULL, NULL); in get_pci_dr()
2008 return devres_find(&pdev->dev, pcim_release, NULL, NULL); in find_pci_dr()
2013 * pcim_enable_device - Managed pci_enable_device()
2025 return -ENOMEM; in pcim_enable_device()
2026 if (dr->enabled) in pcim_enable_device()
2031 pdev->is_managed = 1; in pcim_enable_device()
2032 dr->enabled = 1; in pcim_enable_device()
2039 * pcim_pin_device - Pin managed PCI device
2051 WARN_ON(!dr || !dr->enabled); in pcim_pin_device()
2053 dr->pinned = 1; in pcim_pin_device()
2058 * pcibios_add_device - provide arch specific hooks when adding device dev
2071 * pcibios_release_device - provide arch specific hooks when releasing
2082 * pcibios_disable_device - disable arch specific PCI resources for device dev
2092 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2096 * Permits the platform to provide architecture-specific functionality when
2116 * pci_disable_enabled_device - Disable device without updating enable_cnt
2129 * pci_disable_device - Disable PCI device after use
2133 * anymore. This only involves disabling PCI bus-mastering, if active.
2144 dr->enabled = 0; in pci_disable_device()
2146 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, in pci_disable_device()
2147 "disabling already-disabled device"); in pci_disable_device()
2149 if (atomic_dec_return(&dev->enable_cnt) != 0) in pci_disable_device()
2154 dev->is_busmaster = 0; in pci_disable_device()
2159 * pcibios_set_pcie_reset_state - set reset state for device dev
2169 return -EINVAL; in pcibios_set_pcie_reset_state()
2173 * pci_set_pcie_reset_state - set reset state for device dev
2194 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2203 * pci_check_pme_status - Check if given device has generated PME.
2216 if (!dev->pm_cap) in pci_check_pme_status()
2219 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; in pci_check_pme_status()
2238 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2247 if (pme_poll_reset && dev->pme_poll) in pci_pme_wakeup()
2248 dev->pme_poll = false; in pci_pme_wakeup()
2252 pm_request_resume(&dev->dev); in pci_pme_wakeup()
2258 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2269 * pci_pme_capable - check the capability of PCI device to generate PME#
2275 if (!dev->pm_cap) in pci_pme_capable()
2278 return !!(dev->pme_support & (1 << state)); in pci_pme_capable()
2288 if (pme_dev->dev->pme_poll) { in pci_pme_list_scan()
2291 bridge = pme_dev->dev->bus->self; in pci_pme_list_scan()
2297 if (bridge && bridge->current_state != PCI_D0) in pci_pme_list_scan()
2303 if (pme_dev->dev->current_state == PCI_D3cold) in pci_pme_list_scan()
2306 pci_pme_wakeup(pme_dev->dev, NULL); in pci_pme_list_scan()
2308 list_del(&pme_dev->list); in pci_pme_list_scan()
2322 if (!dev->pme_support) in __pci_pme_active()
2325 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in __pci_pme_active()
2331 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in __pci_pme_active()
2335 * pci_pme_restore - Restore PME configuration after config space restore.
2342 if (!dev->pme_support) in pci_pme_restore()
2345 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_pme_restore()
2346 if (dev->wakeup_prepared) { in pci_pme_restore()
2353 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_pme_restore()
2357 * pci_pme_active - enable or disable PCI device's PME# function
2379 * Although PCIe uses in-band PME message instead of PME# line in pci_pme_active()
2388 if (dev->pme_poll) { in pci_pme_active()
2397 pme_dev->dev = dev; in pci_pme_active()
2399 list_add(&pme_dev->list, &pci_pme_list); in pci_pme_active()
2408 if (pme_dev->dev == dev) { in pci_pme_active()
2409 list_del(&pme_dev->list); in pci_pme_active()
2423 * __pci_enable_wake - enable PCI device as wakeup event source
2429 * When such events involves platform-specific hooks, those hooks are
2437 * -EINVAL is returned if device is not supposed to wake up the system
2439 * the native mechanism fail to enable the generation of wake-up events
2446 * Bridges that are not power-manageable directly only signal in __pci_enable_wake()
2449 * power-manageable may signal wakeup for themselves (for example, in __pci_enable_wake()
2456 if (!!enable == !!dev->wakeup_prepared) in __pci_enable_wake()
2462 * enable. To disable wake-up we call the platform first, for symmetry. in __pci_enable_wake()
2483 dev->wakeup_prepared = true; in __pci_enable_wake()
2487 dev->wakeup_prepared = false; in __pci_enable_wake()
2494 * pci_enable_wake - change wakeup settings for a PCI device
2504 if (enable && !device_may_wakeup(&pci_dev->dev)) in pci_enable_wake()
2505 return -EINVAL; in pci_enable_wake()
2512 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2514 * @enable: True to enable wake-up event generation; false to disable
2517 * and this function allows them to set that up cleanly - pci_enable_wake()
2518 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2523 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2534 * pci_target_state - find an appropriate low power state for a given PCI dev
2568 if (!dev->pm_cap) in pci_target_state()
2572 * If the device is in D3cold even though it's not power-manageable by in pci_target_state()
2573 * the platform, it may have been powered down by non-standard means. in pci_target_state()
2576 if (dev->current_state == PCI_D3cold) in pci_target_state()
2579 if (wakeup && dev->pme_support) { in pci_target_state()
2586 while (state && !(dev->pme_support & (1 << state))) in pci_target_state()
2587 state--; in pci_target_state()
2591 else if (dev->pme_support & 1) in pci_target_state()
2599 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2609 bool wakeup = device_may_wakeup(&dev->dev); in pci_prepare_to_sleep()
2614 return -EIO; in pci_prepare_to_sleep()
2628 * pci_back_from_sleep - turn PCI device on during system-wide transition
2632 * Disable device's system wake-up capability and put it into D0.
2642 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2645 * Prepare @dev to generate wake-up events at run time and put it into a low
2653 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); in pci_finish_runtime_suspend()
2655 return -EIO; in pci_finish_runtime_suspend()
2657 dev->runtime_d3cold = target_state == PCI_D3cold; in pci_finish_runtime_suspend()
2665 dev->runtime_d3cold = false; in pci_finish_runtime_suspend()
2672 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2675 * Return true if the device itself is capable of generating wake-up events
2677 * PME and one of its upstream bridges can generate wake-up events.
2681 struct pci_bus *bus = dev->bus; in pci_dev_run_wake()
2683 if (!dev->pme_support) in pci_dev_run_wake()
2686 /* PME-capable in principle, but not from the target power state */ in pci_dev_run_wake()
2690 if (device_can_wakeup(&dev->dev)) in pci_dev_run_wake()
2693 while (bus->parent) { in pci_dev_run_wake()
2694 struct pci_dev *bridge = bus->self; in pci_dev_run_wake()
2696 if (device_can_wakeup(&bridge->dev)) in pci_dev_run_wake()
2699 bus = bus->parent; in pci_dev_run_wake()
2703 if (bus->bridge) in pci_dev_run_wake()
2704 return device_can_wakeup(bus->bridge); in pci_dev_run_wake()
2711 * pci_dev_need_resume - Check if it is necessary to resume the device.
2714 * Return 'true' if the device is not runtime-suspended or it has to be
2717 * (system-wide) transition.
2721 struct device *dev = &pci_dev->dev; in pci_dev_need_resume()
2734 return target_state != pci_dev->current_state && in pci_dev_need_resume()
2736 pci_dev->current_state != PCI_D3hot; in pci_dev_need_resume()
2740 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2752 struct device *dev = &pci_dev->dev; in pci_dev_adjust_pme()
2754 spin_lock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2757 pci_dev->current_state < PCI_D3cold) in pci_dev_adjust_pme()
2760 spin_unlock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2764 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2767 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2773 struct device *dev = &pci_dev->dev; in pci_dev_complete_resume()
2778 spin_lock_irq(&dev->power.lock); in pci_dev_complete_resume()
2780 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) in pci_dev_complete_resume()
2783 spin_unlock_irq(&dev->power.lock); in pci_dev_complete_resume()
2788 struct device *dev = &pdev->dev; in pci_config_pm_runtime_get()
2789 struct device *parent = dev->parent; in pci_config_pm_runtime_get()
2795 * pdev->current_state is set to PCI_D3cold during suspending, in pci_config_pm_runtime_get()
2804 if (pdev->current_state == PCI_D3cold) in pci_config_pm_runtime_get()
2810 struct device *dev = &pdev->dev; in pci_config_pm_runtime_put()
2811 struct device *parent = dev->parent; in pci_config_pm_runtime_put()
2827 .ident = "X299 DESIGNARE EX-CF",
2830 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2838 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2858 * may not be put into D3 by the OS (Thunderbolt on non-Macs). in pci_bridge_d3_possible()
2860 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) in pci_bridge_d3_possible()
2867 if (bridge->is_thunderbolt) in pci_bridge_d3_possible()
2879 if (bridge->is_hotplug_bridge) in pci_bridge_d3_possible()
2902 dev->no_d3cold || !dev->d3cold_allowed || in pci_dev_check_d3cold()
2905 (device_may_wakeup(&dev->dev) && in pci_dev_check_d3cold()
2917 * pci_bridge_d3_update - Update bridge D3 capabilities
2926 bool remove = !device_is_registered(&dev->dev); in pci_bridge_d3_update()
2938 if (remove && bridge->bridge_d3) in pci_bridge_d3_update()
2958 if (d3cold_ok && !bridge->bridge_d3) in pci_bridge_d3_update()
2959 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, in pci_bridge_d3_update()
2962 if (bridge->bridge_d3 != d3cold_ok) { in pci_bridge_d3_update()
2963 bridge->bridge_d3 = d3cold_ok; in pci_bridge_d3_update()
2970 * pci_d3cold_enable - Enable D3cold for device
2979 if (dev->no_d3cold) { in pci_d3cold_enable()
2980 dev->no_d3cold = false; in pci_d3cold_enable()
2987 * pci_d3cold_disable - Disable D3cold for device
2996 if (!dev->no_d3cold) { in pci_d3cold_disable()
2997 dev->no_d3cold = true; in pci_d3cold_disable()
3004 * pci_pm_init - Initialize PM functions of given PCI device
3013 pm_runtime_forbid(&dev->dev); in pci_pm_init()
3014 pm_runtime_set_active(&dev->dev); in pci_pm_init()
3015 pm_runtime_enable(&dev->dev); in pci_pm_init()
3016 device_enable_async_suspend(&dev->dev); in pci_pm_init()
3017 dev->wakeup_prepared = false; in pci_pm_init()
3019 dev->pm_cap = 0; in pci_pm_init()
3020 dev->pme_support = 0; in pci_pm_init()
3035 dev->pm_cap = pm; in pci_pm_init()
3036 dev->d3hot_delay = PCI_PM_D3HOT_WAIT; in pci_pm_init()
3037 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; in pci_pm_init()
3038 dev->bridge_d3 = pci_bridge_d3_possible(dev); in pci_pm_init()
3039 dev->d3cold_allowed = true; in pci_pm_init()
3041 dev->d1_support = false; in pci_pm_init()
3042 dev->d2_support = false; in pci_pm_init()
3045 dev->d1_support = true; in pci_pm_init()
3047 dev->d2_support = true; in pci_pm_init()
3049 if (dev->d1_support || dev->d2_support) in pci_pm_init()
3051 dev->d1_support ? " D1" : "", in pci_pm_init()
3052 dev->d2_support ? " D2" : ""); in pci_pm_init()
3063 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; in pci_pm_init()
3064 dev->pme_poll = true; in pci_pm_init()
3066 * Make device's PM flags reflect the wake-up capability, but in pci_pm_init()
3069 device_set_wakeup_capable(&dev->dev, true); in pci_pm_init()
3076 dev->imm_ready = 1; in pci_pm_init()
3106 return &dev->resource[bei]; in pci_ea_get_resource()
3110 return &dev->resource[PCI_IOV_RESOURCES + in pci_ea_get_resource()
3111 bei - PCI_EA_BEI_VF_BAR0]; in pci_ea_get_resource()
3114 return &dev->resource[PCI_ROM_RESOURCE]; in pci_ea_get_resource()
3172 /* Read Base MSBs (if 64-bit entry) */ in pci_ea_read()
3181 /* entry starts above 32-bit boundary, can't use */ in pci_ea_read()
3191 /* Read MaxOffset MSBs (if 64-bit entry) */ in pci_ea_read()
3213 if (ent_size != ent_offset - offset) { in pci_ea_read()
3215 ent_size, ent_offset - offset); in pci_ea_read()
3219 res->name = pci_name(dev); in pci_ea_read()
3220 res->start = start; in pci_ea_read()
3221 res->end = end; in pci_ea_read()
3222 res->flags = flags; in pci_ea_read()
3232 bei - PCI_EA_BEI_VF_BAR0, res, prop); in pci_ea_read()
3255 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, in pci_ea_init()
3262 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in pci_ea_init()
3273 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); in pci_add_saved_cap()
3277 * _pci_add_cap_save_buffer - allocate buffer for saving given
3300 return -ENOMEM; in _pci_add_cap_save_buffer()
3302 save_state->cap.cap_nr = cap; in _pci_add_cap_save_buffer()
3303 save_state->cap.cap_extended = extended; in _pci_add_cap_save_buffer()
3304 save_state->cap.size = size; in _pci_add_cap_save_buffer()
3321 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3335 pci_err(dev, "unable to preallocate PCI-X save buffer\n"); in pci_allocate_cap_save_buffers()
3350 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) in pci_free_cap_save_buffers()
3355 * pci_configure_ari - enable or disable ARI forwarding
3366 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) in pci_configure_ari()
3369 bridge = dev->bus->self; in pci_configure_ari()
3380 bridge->ari_enabled = 1; in pci_configure_ari()
3384 bridge->ari_enabled = 0; in pci_configure_ari()
3393 pos = pdev->acs_cap; in pci_acs_flags_enabled()
3400 * capability field can therefore be assumed as hard-wired enabled. in pci_acs_flags_enabled()
3410 * pci_acs_enabled - test ACS against required flags for a given device
3420 * opportunity for peer-to-peer access. We therefore return 'true'
3434 * Conventional PCI and PCI-X devices never support ACS, either in pci_acs_enabled()
3443 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, in pci_acs_enabled()
3445 * handle them as we would a non-PCIe device. in pci_acs_enabled()
3459 * implement ACS in order to indicate their peer-to-peer capabilities, in pci_acs_enabled()
3460 * regardless of whether they are single- or multi-function devices. in pci_acs_enabled()
3467 * implemented by the remaining PCIe types to indicate peer-to-peer in pci_acs_enabled()
3476 if (!pdev->multifunction) in pci_acs_enabled()
3490 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
3509 if (pci_is_root_bus(pdev->bus)) in pci_acs_path_enabled()
3512 parent = pdev->bus->self; in pci_acs_path_enabled()
3519 * pci_acs_init - Initialize ACS if hardware supports it
3524 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); in pci_acs_init()
3536 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3541 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3542 * Returns -ENOENT if no ctrl register for the BAR could be found.
3551 return -ENOTSUPP; in pci_rebar_find_pos()
3566 return -ENOENT; in pci_rebar_find_pos()
3570 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3590 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && in pci_rebar_get_possible_sizes()
3598 * pci_rebar_get_current_size - get the current size of a BAR
3619 * pci_rebar_set_size - set a new size for a BAR
3644 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3653 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3658 struct pci_bus *bus = dev->bus; in pci_enable_atomic_ops_to_root()
3663 return -EINVAL; in pci_enable_atomic_ops_to_root()
3669 * completers, and no peer-to-peer. in pci_enable_atomic_ops_to_root()
3678 return -EINVAL; in pci_enable_atomic_ops_to_root()
3681 while (bus->parent) { in pci_enable_atomic_ops_to_root()
3682 bridge = bus->self; in pci_enable_atomic_ops_to_root()
3691 return -EINVAL; in pci_enable_atomic_ops_to_root()
3697 return -EINVAL; in pci_enable_atomic_ops_to_root()
3706 return -EINVAL; in pci_enable_atomic_ops_to_root()
3709 bus = bus->parent; in pci_enable_atomic_ops_to_root()
3719 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3724 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3725 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3733 if (pci_ari_enabled(dev->bus)) in pci_swizzle_interrupt_pin()
3736 slot = PCI_SLOT(dev->devfn); in pci_swizzle_interrupt_pin()
3738 return (((pin - 1) + slot) % 4) + 1; in pci_swizzle_interrupt_pin()
3745 pin = dev->pin; in pci_get_interrupt_pin()
3747 return -1; in pci_get_interrupt_pin()
3749 while (!pci_is_root_bus(dev->bus)) { in pci_get_interrupt_pin()
3751 dev = dev->bus->self; in pci_get_interrupt_pin()
3758 * pci_common_swizzle - swizzle INTx all the way to root bridge
3762 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3769 while (!pci_is_root_bus(dev->bus)) { in pci_common_swizzle()
3771 dev = dev->bus->self; in pci_common_swizzle()
3774 return PCI_SLOT(dev->devfn); in pci_common_swizzle()
3779 * pci_release_region - Release a PCI bar
3803 dr->region_mask &= ~(1 << bar); in pci_release_region()
3808 * __pci_request_region - Reserved PCI I/O and memory resource
3847 dr->region_mask |= 1 << bar; in __pci_request_region()
3853 &pdev->resource[bar]); in __pci_request_region()
3854 return -EBUSY; in __pci_request_region()
3858 * pci_request_region - Reserve PCI I/O and memory resource
3878 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3907 while (--i >= 0) in __pci_request_selected_regions()
3911 return -EBUSY; in __pci_request_selected_regions()
3916 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3937 * pci_release_regions - Release reserved PCI I/O and memory resources
3948 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1); in pci_release_regions()
3953 * pci_request_regions - Reserve PCI I/O and memory resources
3968 ((1 << PCI_STD_NUM_BARS) - 1), res_name); in pci_request_regions()
3973 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
3990 ((1 << PCI_STD_NUM_BARS) - 1), res_name); in pci_request_regions_exclusive()
4006 return -EINVAL; in pci_register_io_range()
4010 return -ENOMEM; in pci_register_io_range()
4012 range->fwnode = fwnode; in pci_register_io_range()
4013 range->size = size; in pci_register_io_range()
4014 range->hw_start = addr; in pci_register_io_range()
4015 range->flags = LOGIC_PIO_CPU_MMIO; in pci_register_io_range()
4022 if (ret == -EEXIST) in pci_register_io_range()
4050 return (unsigned long)-1; in pci_address_to_pio()
4057 * pci_remap_iospace - Remap the memory mapped I/O space
4069 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_remap_iospace()
4071 if (!(res->flags & IORESOURCE_IO)) in pci_remap_iospace()
4072 return -EINVAL; in pci_remap_iospace()
4074 if (res->end > IO_SPACE_LIMIT) in pci_remap_iospace()
4075 return -EINVAL; in pci_remap_iospace()
4085 return -ENODEV; in pci_remap_iospace()
4091 * pci_unmap_iospace - Unmap the memory mapped I/O space
4101 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_unmap_iospace()
4116 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4132 return -ENOMEM; in devm_pci_remap_iospace()
4147 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4177 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4191 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4206 return IOMEM_ERR_PTR(-EINVAL); in devm_pci_remap_cfg_resource()
4210 name = res->name ?: dev_name(dev); in devm_pci_remap_cfg_resource()
4212 if (!devm_request_mem_region(dev, res->start, size, name)) { in devm_pci_remap_cfg_resource()
4214 return IOMEM_ERR_PTR(-EBUSY); in devm_pci_remap_cfg_resource()
4217 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size); in devm_pci_remap_cfg_resource()
4220 devm_release_mem_region(dev, res->start, size); in devm_pci_remap_cfg_resource()
4221 dest_ptr = IOMEM_ERR_PTR(-ENOMEM); in devm_pci_remap_cfg_resource()
4230 u16 old_cmd, cmd; in __pci_set_master() local
4234 cmd = old_cmd | PCI_COMMAND_MASTER; in __pci_set_master()
4236 cmd = old_cmd & ~PCI_COMMAND_MASTER; in __pci_set_master()
4237 if (cmd != old_cmd) { in __pci_set_master()
4240 pci_write_config_word(dev, PCI_COMMAND, cmd); in __pci_set_master()
4242 dev->is_busmaster = enable; in __pci_set_master()
4246 * pcibios_setup - process "pci=" kernel boot arguments
4258 * pcibios_set_master - enable PCI bus-mastering for device dev
4261 * Enables PCI bus-mastering for the device. This is the default
4285 * pci_set_master - enables bus-mastering for device dev
4288 * Enables bus-mastering on the device and calls pcibios_set_master()
4299 * pci_clear_master - disables bus-mastering for device dev
4309 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4314 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4316 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4323 return -EINVAL; in pci_set_cacheline_size()
4342 return -EINVAL; in pci_set_cacheline_size()
4347 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4350 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4352 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4360 u16 cmd; in pci_set_mwi()
4366 pci_read_config_word(dev, PCI_COMMAND, &cmd); in pci_set_mwi()
4367 if (!(cmd & PCI_COMMAND_INVALIDATE)) { in pci_set_mwi()
4368 pci_dbg(dev, "enabling Mem-Wr-Inval\n"); in pci_set_mwi()
4369 cmd |= PCI_COMMAND_INVALIDATE; in pci_set_mwi()
4370 pci_write_config_word(dev, PCI_COMMAND, cmd); in pci_set_mwi()
4378 * pcim_set_mwi - a device-managed pci_set_mwi()
4383 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4391 return -ENOMEM; in pcim_set_mwi()
4393 dr->mwi = 1; in pcim_set_mwi()
4399 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4402 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4405 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4418 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4421 * Disables PCI Memory-Write-Invalidate transaction on the device
4426 u16 cmd; in pci_clear_mwi() local
4428 pci_read_config_word(dev, PCI_COMMAND, &cmd); in pci_clear_mwi()
4429 if (cmd & PCI_COMMAND_INVALIDATE) { in pci_clear_mwi()
4430 cmd &= ~PCI_COMMAND_INVALIDATE; in pci_clear_mwi()
4431 pci_write_config_word(dev, PCI_COMMAND, cmd); in pci_clear_mwi()
4438 * pci_intx - enables/disables PCI INTx for device dev
4461 if (dr && !dr->restore_intx) { in pci_intx()
4462 dr->restore_intx = 1; in pci_intx()
4463 dr->orig_intx = !enable; in pci_intx()
4471 struct pci_bus *bus = dev->bus; in pci_check_and_set_intx_mask()
4487 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); in pci_check_and_set_intx_mask()
4506 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); in pci_check_and_set_intx_mask()
4515 * pci_check_and_mask_intx - mask INTx on pending interrupt
4528 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4542 * pci_wait_for_pending_transaction - wait for pending transaction
4558 * pcie_has_flr - check if a device supports function level resets
4568 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pcie_has_flr()
4577 * pcie_flr - initiate a PCIe function level reset
4591 if (dev->imm_ready) in pcie_flr()
4612 return -ENOTTY; in pci_af_flr()
4614 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pci_af_flr()
4615 return -ENOTTY; in pci_af_flr()
4619 return -ENOTTY; in pci_af_flr()
4625 * Wait for Transaction Pending bit to clear. A word-aligned test in pci_af_flr()
4635 if (dev->imm_ready) in pci_af_flr()
4650 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4656 * PCI_D0. If that's the case and the device is not in a low-power state
4660 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4668 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) in pci_pm_reset()
4669 return -ENOTTY; in pci_pm_reset()
4671 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); in pci_pm_reset()
4673 return -ENOTTY; in pci_pm_reset()
4678 if (dev->current_state != PCI_D0) in pci_pm_reset()
4679 return -EINVAL; in pci_pm_reset()
4683 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4688 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4691 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); in pci_pm_reset()
4695 * pcie_wait_for_link_delay - Wait until link is active or inactive
4713 if (!pdev->link_active_reporting) { in pcie_wait_for_link_delay()
4737 timeout -= 10; in pcie_wait_for_link_delay()
4746 * pcie_wait_for_link - Wait until link is active or inactive
4770 list_for_each_entry(pdev, &bus->devices, bus_list) { in pci_bus_max_d3cold_delay()
4771 if (pdev->d3cold_delay < min_delay) in pci_bus_max_d3cold_delay()
4772 min_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
4773 if (pdev->d3cold_delay > max_delay) in pci_bus_max_d3cold_delay()
4774 max_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
4781 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4799 if (!pci_is_bridge(dev) || !dev->bridge_d3) in pci_bridge_wait_for_secondary_bus()
4806 * For any hot-added devices the access delay is handled in pciehp in pci_bridge_wait_for_secondary_bus()
4810 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) { in pci_bridge_wait_for_secondary_bus()
4816 delay = pci_bus_max_d3cold_delay(dev->subordinate); in pci_bridge_wait_for_secondary_bus()
4822 child = list_first_entry(&dev->subordinate->devices, struct pci_dev, in pci_bridge_wait_for_secondary_bus()
4827 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before in pci_bridge_wait_for_secondary_bus()
4846 * device that did not respond is a broken device. There is in pci_bridge_wait_for_secondary_bus()
4898 * be re-initialized. PCIe has some ways to shorten this, in pci_reset_secondary_bus()
4910 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4914 * Devices on the secondary bus are left in power-on state.
4928 if (pci_is_root_bus(dev->bus) || dev->subordinate || in pci_parent_bus_reset()
4929 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_parent_bus_reset()
4930 return -ENOTTY; in pci_parent_bus_reset()
4932 list_for_each_entry(pdev, &dev->bus->devices, bus_list) in pci_parent_bus_reset()
4934 return -ENOTTY; in pci_parent_bus_reset()
4939 return pci_bridge_secondary_bus_reset(dev->bus->self); in pci_parent_bus_reset()
4944 int rc = -ENOTTY; in pci_reset_hotplug_slot()
4946 if (!hotplug || !try_module_get(hotplug->owner)) in pci_reset_hotplug_slot()
4949 if (hotplug->ops->reset_slot) in pci_reset_hotplug_slot()
4950 rc = hotplug->ops->reset_slot(hotplug, probe); in pci_reset_hotplug_slot()
4952 module_put(hotplug->owner); in pci_reset_hotplug_slot()
4959 if (dev->multifunction || dev->subordinate || !dev->slot || in pci_dev_reset_slot_function()
4960 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_dev_reset_slot_function()
4961 return -ENOTTY; in pci_dev_reset_slot_function()
4963 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); in pci_dev_reset_slot_function()
4970 device_lock(&dev->dev); in pci_dev_lock()
4977 if (device_trylock(&dev->dev)) in pci_dev_trylock()
4987 device_unlock(&dev->dev); in pci_dev_unlock()
4994 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_save_and_disable()
4997 * dev->driver->err_handler->reset_prepare() is protected against in pci_dev_save_and_disable()
4998 * races with ->remove() by the device lock, which must be held by in pci_dev_save_and_disable()
5001 if (err_handler && err_handler->reset_prepare) in pci_dev_save_and_disable()
5002 err_handler->reset_prepare(dev); in pci_dev_save_and_disable()
5005 * Wake-up device prior to save. PM registers default to D0 after in pci_dev_save_and_disable()
5007 * to a non-D0 state anyway. in pci_dev_save_and_disable()
5014 * INTx-disable which is set. This not only disables MMIO and I/O port in pci_dev_save_and_disable()
5016 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 in pci_dev_save_and_disable()
5017 * compliant devices, INTx-disable prevents legacy interrupts. in pci_dev_save_and_disable()
5025 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_restore()
5030 * dev->driver->err_handler->reset_done() is protected against in pci_dev_restore()
5031 * races with ->remove() by the device lock, which must be held by in pci_dev_restore()
5034 if (err_handler && err_handler->reset_done) in pci_dev_restore()
5035 err_handler->reset_done(dev); in pci_dev_restore()
5039 * __pci_reset_function_locked - reset a PCI device function while holding
5065 * A reset method returns -ENOTTY if it doesn't support this device in __pci_reset_function_locked()
5070 * reset mechanisms might be broken on the device. in __pci_reset_function_locked()
5073 if (rc != -ENOTTY) in __pci_reset_function_locked()
5077 if (rc != -ENOTTY) in __pci_reset_function_locked()
5081 if (rc != -ENOTTY) in __pci_reset_function_locked()
5084 if (rc != -ENOTTY) in __pci_reset_function_locked()
5087 if (rc != -ENOTTY) in __pci_reset_function_locked()
5094 * pci_probe_reset_function - check whether the device can be safely reset
5111 if (rc != -ENOTTY) in pci_probe_reset_function()
5116 if (rc != -ENOTTY) in pci_probe_reset_function()
5119 if (rc != -ENOTTY) in pci_probe_reset_function()
5122 if (rc != -ENOTTY) in pci_probe_reset_function()
5129 * pci_reset_function - quiesce and reset a PCI device function
5148 if (!dev->reset_fn) in pci_reset_function()
5149 return -ENOTTY; in pci_reset_function()
5164 * pci_reset_function_locked - quiesce and reset a PCI device function
5184 if (!dev->reset_fn) in pci_reset_function_locked()
5185 return -ENOTTY; in pci_reset_function_locked()
5198 * pci_try_reset_function - quiesce and reset a PCI device function
5201 * Same as above, except return -EAGAIN if unable to lock device.
5207 if (!dev->reset_fn) in pci_try_reset_function()
5208 return -ENOTTY; in pci_try_reset_function()
5211 return -EAGAIN; in pci_try_reset_function()
5228 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_bus_resetable()
5231 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_resetable()
5232 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_bus_resetable()
5233 (dev->subordinate && !pci_bus_resetable(dev->subordinate))) in pci_bus_resetable()
5245 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_lock()
5247 if (dev->subordinate) in pci_bus_lock()
5248 pci_bus_lock(dev->subordinate); in pci_bus_lock()
5257 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_unlock()
5258 if (dev->subordinate) in pci_bus_unlock()
5259 pci_bus_unlock(dev->subordinate); in pci_bus_unlock()
5269 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5272 if (dev->subordinate) { in pci_bus_trylock()
5273 if (!pci_bus_trylock(dev->subordinate)) { in pci_bus_trylock()
5282 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5283 if (dev->subordinate) in pci_bus_trylock()
5284 pci_bus_unlock(dev->subordinate); in pci_bus_trylock()
5295 if (slot->bus->self && in pci_slot_resetable()
5296 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_slot_resetable()
5299 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_resetable()
5300 if (!dev->slot || dev->slot != slot) in pci_slot_resetable()
5302 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_slot_resetable()
5303 (dev->subordinate && !pci_bus_resetable(dev->subordinate))) in pci_slot_resetable()
5315 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_lock()
5316 if (!dev->slot || dev->slot != slot) in pci_slot_lock()
5319 if (dev->subordinate) in pci_slot_lock()
5320 pci_bus_lock(dev->subordinate); in pci_slot_lock()
5329 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_unlock()
5330 if (!dev->slot || dev->slot != slot) in pci_slot_unlock()
5332 if (dev->subordinate) in pci_slot_unlock()
5333 pci_bus_unlock(dev->subordinate); in pci_slot_unlock()
5343 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_trylock()
5344 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5348 if (dev->subordinate) { in pci_slot_trylock()
5349 if (!pci_bus_trylock(dev->subordinate)) { in pci_slot_trylock()
5359 &slot->bus->devices, bus_list) { in pci_slot_trylock()
5360 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5362 if (dev->subordinate) in pci_slot_trylock()
5363 pci_bus_unlock(dev->subordinate); in pci_slot_trylock()
5377 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_save_and_disable_locked()
5379 if (dev->subordinate) in pci_bus_save_and_disable_locked()
5380 pci_bus_save_and_disable_locked(dev->subordinate); in pci_bus_save_and_disable_locked()
5393 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_restore_locked()
5395 if (dev->subordinate) in pci_bus_restore_locked()
5396 pci_bus_restore_locked(dev->subordinate); in pci_bus_restore_locked()
5408 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_save_and_disable_locked()
5409 if (!dev->slot || dev->slot != slot) in pci_slot_save_and_disable_locked()
5412 if (dev->subordinate) in pci_slot_save_and_disable_locked()
5413 pci_bus_save_and_disable_locked(dev->subordinate); in pci_slot_save_and_disable_locked()
5426 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_restore_locked()
5427 if (!dev->slot || dev->slot != slot) in pci_slot_restore_locked()
5430 if (dev->subordinate) in pci_slot_restore_locked()
5431 pci_bus_restore_locked(dev->subordinate); in pci_slot_restore_locked()
5440 return -ENOTTY; in pci_slot_reset()
5447 rc = pci_reset_hotplug_slot(slot->hotplug, probe); in pci_slot_reset()
5456 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5468 * __pci_reset_slot - Try to reset a PCI slot
5480 * Same as above except return -EAGAIN if the slot cannot be locked
5493 rc = pci_reset_hotplug_slot(slot->hotplug, 0); in __pci_reset_slot()
5497 rc = -EAGAIN; in __pci_reset_slot()
5506 if (!bus->self || !pci_bus_resetable(bus)) in pci_bus_reset()
5507 return -ENOTTY; in pci_bus_reset()
5516 ret = pci_bridge_secondary_bus_reset(bus->self); in pci_bus_reset()
5524 * pci_bus_error_reset - reset the bridge's subordinate bus
5533 struct pci_bus *bus = bridge->subordinate; in pci_bus_error_reset()
5537 return -ENOTTY; in pci_bus_error_reset()
5540 if (list_empty(&bus->slots)) in pci_bus_error_reset()
5543 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
5547 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
5555 return pci_bus_reset(bridge->subordinate, 0); in pci_bus_error_reset()
5559 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5571 * __pci_reset_bus - Try to reset a PCI bus
5574 * Same as above except return -EAGAIN if the bus cannot be locked
5587 rc = pci_bridge_secondary_bus_reset(bus->self); in __pci_reset_bus()
5591 rc = -EAGAIN; in __pci_reset_bus()
5597 * pci_reset_bus - Try to reset a PCI bus
5600 * Same as above except return -EAGAIN if the bus cannot be locked
5604 return (!pci_probe_reset_slot(pdev->slot)) ? in pci_reset_bus()
5605 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); in pci_reset_bus()
5610 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5623 return -EINVAL; in pcix_get_max_mmrbc()
5626 return -EINVAL; in pcix_get_max_mmrbc()
5633 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5642 u16 cmd; in pcix_get_mmrbc() local
5646 return -EINVAL; in pcix_get_mmrbc()
5648 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) in pcix_get_mmrbc()
5649 return -EINVAL; in pcix_get_mmrbc()
5651 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); in pcix_get_mmrbc()
5656 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5668 u16 cmd; in pcix_set_mmrbc() local
5671 return -EINVAL; in pcix_set_mmrbc()
5673 v = ffs(mmrbc) - 10; in pcix_set_mmrbc()
5677 return -EINVAL; in pcix_set_mmrbc()
5680 return -EINVAL; in pcix_set_mmrbc()
5683 return -E2BIG; in pcix_set_mmrbc()
5685 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) in pcix_set_mmrbc()
5686 return -EINVAL; in pcix_set_mmrbc()
5688 o = (cmd & PCI_X_CMD_MAX_READ) >> 2; in pcix_set_mmrbc()
5690 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) in pcix_set_mmrbc()
5691 return -EIO; in pcix_set_mmrbc()
5693 cmd &= ~PCI_X_CMD_MAX_READ; in pcix_set_mmrbc()
5694 cmd |= v << 2; in pcix_set_mmrbc()
5695 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) in pcix_set_mmrbc()
5696 return -EIO; in pcix_set_mmrbc()
5703 * pcie_get_readrq - get PCI Express read request size
5719 * pcie_set_readrq - set PCI Express maximum memory read request
5732 return -EINVAL; in pcie_set_readrq()
5746 v = (ffs(rq) - 8) << 12; in pcie_set_readrq()
5756 * pcie_get_mps - get PCI Express maximum payload size
5772 * pcie_set_mps - set PCI Express maximum payload size
5785 return -EINVAL; in pcie_set_mps()
5787 v = ffs(mps) - 8; in pcie_set_mps()
5788 if (v > dev->pcie_mpss) in pcie_set_mps()
5789 return -EINVAL; in pcie_set_mps()
5800 * pcie_bandwidth_available - determine minimum link settings of a PCIe
5858 * pcie_get_speed_cap - query for the PCI device's link speed capability
5879 /* PCIe r3.0-compliant */ in pcie_get_speed_cap()
5894 * pcie_get_width_cap - query for the PCI device's link width capability
5913 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
5935 * __pcie_print_link_status - Report the PCI device's link speed and width
5968 * pcie_print_link_status - Report the PCI device's link speed and width
5980 * pci_select_bars - Make BAR mask from the type of resource
6014 * pci_set_vga_state - set VGA decode state on device and parents if requested
6026 u16 cmd; in pci_set_vga_state() local
6037 pci_read_config_word(dev, PCI_COMMAND, &cmd); in pci_set_vga_state()
6039 cmd |= command_bits; in pci_set_vga_state()
6041 cmd &= ~command_bits; in pci_set_vga_state()
6042 pci_write_config_word(dev, PCI_COMMAND, cmd); in pci_set_vga_state()
6048 bus = dev->bus; in pci_set_vga_state()
6050 bridge = bus->self; in pci_set_vga_state()
6053 &cmd); in pci_set_vga_state()
6055 cmd |= PCI_BRIDGE_CTL_VGA; in pci_set_vga_state()
6057 cmd &= ~PCI_BRIDGE_CTL_VGA; in pci_set_vga_state()
6059 cmd); in pci_set_vga_state()
6061 bus = bus->parent; in pci_set_vga_state()
6074 adev = ACPI_COMPANION(&pdev->dev); in pci_pr3_present()
6078 return adev->power.flags.power_resources && in pci_pr3_present()
6079 acpi_has_method(adev->handle, "_PR3"); in pci_pr3_present()
6085 * pci_add_dma_alias - Add a DMA devfn alias for a device
6090 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6091 * which is used to program permissible bus-devfn source addresses for DMA
6094 * from their logical bus-devfn. Examples include device quirks where the
6095 * device simply uses the wrong devfn, as well as non-transparent bridges
6108 nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from); in pci_add_dma_alias()
6109 devfn_to = devfn_from + nr_devfns - 1; in pci_add_dma_alias()
6111 if (!dev->dma_alias_mask) in pci_add_dma_alias()
6112 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL); in pci_add_dma_alias()
6113 if (!dev->dma_alias_mask) { in pci_add_dma_alias()
6118 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns); in pci_add_dma_alias()
6131 return (dev1->dma_alias_mask && in pci_devs_are_dma_aliases()
6132 test_bit(dev2->devfn, dev1->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6133 (dev2->dma_alias_mask && in pci_devs_are_dma_aliases()
6134 test_bit(dev1->devfn, dev2->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6145 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); in pci_device_is_present()
6151 struct pci_dev *bridge = dev->bus->self; in pci_ignore_hotplug()
6153 dev->ignore_hotplug = 1; in pci_ignore_hotplug()
6156 bridge->ignore_hotplug = 1; in pci_ignore_hotplug()
6161 * pci_real_dma_dev - Get PCI DMA device for PCI device
6164 * Permits the platform to provide architecture-specific functionality to
6181 * Arches that don't want to expose struct resource to userland as-is in
6188 *start = rsrc->start; in pci_resource_to_user()
6189 *end = rsrc->end; in pci_resource_to_user()
6196 * pci_specified_resource_alignment - get resource alignment specified by user.
6260 struct resource *r = &dev->resource[bar]; in pci_request_resource_alignment()
6263 if (!(r->flags & IORESOURCE_MEM)) in pci_request_resource_alignment()
6266 if (r->flags & IORESOURCE_PCI_FIXED) { in pci_request_resource_alignment()
6293 * set r->start to the desired alignment. By itself this in pci_request_resource_alignment()
6308 r->start = 0; in pci_request_resource_alignment()
6309 r->end = align - 1; in pci_request_resource_alignment()
6311 r->flags &= ~IORESOURCE_SIZEALIGN; in pci_request_resource_alignment()
6312 r->flags |= IORESOURCE_STARTALIGN; in pci_request_resource_alignment()
6313 r->start = align; in pci_request_resource_alignment()
6314 r->end = r->start + size - 1; in pci_request_resource_alignment()
6316 r->flags |= IORESOURCE_UNSET; in pci_request_resource_alignment()
6323 * Later on, the kernel will assign page-aligned memory resource back
6335 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec in pci_reassigndev_resource_alignment()
6337 * described by the VF BARx register in the PF's SR-IOV capability. in pci_reassigndev_resource_alignment()
6340 if (dev->is_virtfn) in pci_reassigndev_resource_alignment()
6348 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && in pci_reassigndev_resource_alignment()
6349 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { in pci_reassigndev_resource_alignment()
6366 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_reassigndev_resource_alignment()
6368 r = &dev->resource[i]; in pci_reassigndev_resource_alignment()
6369 if (!(r->flags & IORESOURCE_MEM)) in pci_reassigndev_resource_alignment()
6371 r->flags |= IORESOURCE_UNSET; in pci_reassigndev_resource_alignment()
6372 r->end = resource_size(r) - 1; in pci_reassigndev_resource_alignment()
6373 r->start = 0; in pci_reassigndev_resource_alignment()
6393 if (count >= 2 && buf[count - 2] != '\n' && count < PAGE_SIZE - 1) { in resource_alignment_show()
6394 buf[count - 1] = '\n'; in resource_alignment_show()
6407 return -ENOMEM; in resource_alignment_store()
6433 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6442 static int use_dt_domains = -1; in of_pci_bus_find_domain_nr()
6443 int domain = -1; in of_pci_bus_find_domain_nr()
6446 domain = of_get_pci_domain_nr(parent->of_node); in of_pci_bus_find_domain_nr()
6471 * invalidating the domain value (domain = -1) and printing a in of_pci_bus_find_domain_nr()
6481 pr_err("Node %pOF has ", parent->of_node); in of_pci_bus_find_domain_nr()
6482 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n"); in of_pci_bus_find_domain_nr()
6483 domain = -1; in of_pci_bus_find_domain_nr()
6497 * pci_ext_cfg_avail - can we access extended PCI config space?