Lines Matching +full:xusb +full:- +full:padctl
1 // SPDX-License-Identifier: GPL-2.0-only
22 #include "xusb.h"
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
254 to_tegra210_xusb_padctl(struct tegra_xusb_padctl *padctl) in to_tegra210_xusb_padctl() argument
256 return container_of(padctl, struct tegra210_xusb_padctl, base); in to_tegra210_xusb_padctl()
259 /* must be called under padctl->lock */
260 static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl) in tegra210_pex_uphy_enable() argument
262 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_enable()
267 if (pcie->enable > 0) { in tegra210_pex_uphy_enable()
268 pcie->enable++; in tegra210_pex_uphy_enable()
272 err = clk_prepare_enable(pcie->pll); in tegra210_pex_uphy_enable()
276 err = reset_control_deassert(pcie->rst); in tegra210_pex_uphy_enable()
280 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
285 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
287 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
292 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
294 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
296 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
298 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
300 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
302 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
304 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
306 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
314 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
316 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
323 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
325 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
327 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
329 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
332 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
336 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
338 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in tegra210_pex_uphy_enable()
340 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
342 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
347 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
355 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
359 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
361 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
366 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
374 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
378 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
380 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
385 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
393 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
397 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
400 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
405 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
413 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
417 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
419 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
424 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
432 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
436 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
438 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
442 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
444 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
446 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
448 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
450 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
452 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in tegra210_pex_uphy_enable()
458 pcie->enable++; in tegra210_pex_uphy_enable()
463 reset_control_assert(pcie->rst); in tegra210_pex_uphy_enable()
465 clk_disable_unprepare(pcie->pll); in tegra210_pex_uphy_enable()
469 static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl) in tegra210_pex_uphy_disable() argument
471 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_disable()
473 mutex_lock(&padctl->lock); in tegra210_pex_uphy_disable()
475 if (WARN_ON(pcie->enable == 0)) in tegra210_pex_uphy_disable()
478 if (--pcie->enable > 0) in tegra210_pex_uphy_disable()
481 reset_control_assert(pcie->rst); in tegra210_pex_uphy_disable()
482 clk_disable_unprepare(pcie->pll); in tegra210_pex_uphy_disable()
485 mutex_unlock(&padctl->lock); in tegra210_pex_uphy_disable()
488 /* must be called under padctl->lock */
489 static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl, bool usb) in tegra210_sata_uphy_enable() argument
491 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata); in tegra210_sata_uphy_enable()
496 if (sata->enable > 0) { in tegra210_sata_uphy_enable()
497 sata->enable++; in tegra210_sata_uphy_enable()
501 err = clk_prepare_enable(sata->pll); in tegra210_sata_uphy_enable()
505 err = reset_control_deassert(sata->rst); in tegra210_sata_uphy_enable()
509 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
514 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
516 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5); in tegra210_sata_uphy_enable()
521 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5); in tegra210_sata_uphy_enable()
523 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
525 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
527 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
529 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
531 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
533 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
535 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
550 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
552 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
565 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
567 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
569 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
571 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
574 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
578 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
580 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in tegra210_sata_uphy_enable()
582 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
584 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
589 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
597 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
601 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
603 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
608 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
616 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
620 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
622 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
627 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
635 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
639 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
642 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
647 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
655 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
659 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
661 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
666 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
674 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
678 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
680 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
684 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
686 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in tegra210_sata_uphy_enable()
688 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
690 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in tegra210_sata_uphy_enable()
692 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
694 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in tegra210_sata_uphy_enable()
700 sata->enable++; in tegra210_sata_uphy_enable()
705 reset_control_assert(sata->rst); in tegra210_sata_uphy_enable()
707 clk_disable_unprepare(sata->pll); in tegra210_sata_uphy_enable()
711 static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl) in tegra210_sata_uphy_disable() argument
713 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata); in tegra210_sata_uphy_disable()
715 mutex_lock(&padctl->lock); in tegra210_sata_uphy_disable()
717 if (WARN_ON(sata->enable == 0)) in tegra210_sata_uphy_disable()
720 if (--sata->enable > 0) in tegra210_sata_uphy_disable()
723 reset_control_assert(sata->rst); in tegra210_sata_uphy_disable()
724 clk_disable_unprepare(sata->pll); in tegra210_sata_uphy_disable()
727 mutex_unlock(&padctl->lock); in tegra210_sata_uphy_disable()
730 static int tegra210_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) in tegra210_xusb_padctl_enable() argument
734 mutex_lock(&padctl->lock); in tegra210_xusb_padctl_enable()
736 if (padctl->enable++ > 0) in tegra210_xusb_padctl_enable()
739 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
741 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
745 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
747 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
751 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
753 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_enable()
756 mutex_unlock(&padctl->lock); in tegra210_xusb_padctl_enable()
760 static int tegra210_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) in tegra210_xusb_padctl_disable() argument
764 mutex_lock(&padctl->lock); in tegra210_xusb_padctl_disable()
766 if (WARN_ON(padctl->enable == 0)) in tegra210_xusb_padctl_disable()
769 if (--padctl->enable > 0) in tegra210_xusb_padctl_disable()
772 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
774 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
778 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
780 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
784 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
786 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_xusb_padctl_disable()
789 mutex_unlock(&padctl->lock); in tegra210_xusb_padctl_disable()
793 static int tegra210_hsic_set_idle(struct tegra_xusb_padctl *padctl, in tegra210_hsic_set_idle() argument
798 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_set_idle()
813 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_set_idle()
818 static int tegra210_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl, in tegra210_usb3_set_lfps_detect() argument
825 port = tegra_xusb_find_port(padctl, "usb3", index); in tegra210_usb3_set_lfps_detect()
827 return -ENODEV; in tegra210_usb3_set_lfps_detect()
829 lane = port->lane; in tegra210_usb3_set_lfps_detect()
831 if (lane->pad == padctl->pcie) in tegra210_usb3_set_lfps_detect()
832 offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index); in tegra210_usb3_set_lfps_detect()
836 value = padctl_readl(padctl, offset); in tegra210_usb3_set_lfps_detect()
850 padctl_writel(padctl, value, offset); in tegra210_usb3_set_lfps_detect()
867 "xusb",
872 TEGRA210_LANE("usb2-0", 0x004, 0, 0x3, usb2),
873 TEGRA210_LANE("usb2-1", 0x004, 2, 0x3, usb2),
874 TEGRA210_LANE("usb2-2", 0x004, 4, 0x3, usb2),
875 TEGRA210_LANE("usb2-3", 0x004, 6, 0x3, usb2),
887 return ERR_PTR(-ENOMEM); in tegra210_usb2_lane_probe()
889 INIT_LIST_HEAD(&usb2->base.list); in tegra210_usb2_lane_probe()
890 usb2->base.soc = &pad->soc->lanes[index]; in tegra210_usb2_lane_probe()
891 usb2->base.index = index; in tegra210_usb2_lane_probe()
892 usb2->base.pad = pad; in tegra210_usb2_lane_probe()
893 usb2->base.np = np; in tegra210_usb2_lane_probe()
895 err = tegra_xusb_lane_parse_dt(&usb2->base, np); in tegra210_usb2_lane_probe()
901 return &usb2->base; in tegra210_usb2_lane_probe()
919 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_init() local
922 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_usb2_phy_init()
927 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_usb2_phy_init()
929 return tegra210_xusb_padctl_enable(padctl); in tegra210_usb2_phy_init()
936 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_usb2_phy_exit()
939 static int tegra210_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl, in tegra210_xusb_padctl_vbus_override() argument
944 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear"); in tegra210_xusb_padctl_vbus_override()
946 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_vbus_override()
958 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_vbus_override()
963 static int tegra210_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl, in tegra210_xusb_padctl_id_override() argument
968 dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear"); in tegra210_xusb_padctl_id_override()
970 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
975 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
978 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
992 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID); in tegra210_xusb_padctl_id_override()
1001 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_set_mode() local
1002 struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl, in tegra210_usb2_phy_set_mode()
1003 lane->index); in tegra210_usb2_phy_set_mode()
1006 mutex_lock(&padctl->lock); in tegra210_usb2_phy_set_mode()
1008 dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode); in tegra210_usb2_phy_set_mode()
1012 tegra210_xusb_padctl_id_override(padctl, true); in tegra210_usb2_phy_set_mode()
1014 err = regulator_enable(port->supply); in tegra210_usb2_phy_set_mode()
1016 tegra210_xusb_padctl_vbus_override(padctl, true); in tegra210_usb2_phy_set_mode()
1023 if (regulator_is_enabled(port->supply)) in tegra210_usb2_phy_set_mode()
1024 regulator_disable(port->supply); in tegra210_usb2_phy_set_mode()
1026 tegra210_xusb_padctl_id_override(padctl, false); in tegra210_usb2_phy_set_mode()
1027 tegra210_xusb_padctl_vbus_override(padctl, false); in tegra210_usb2_phy_set_mode()
1031 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_set_mode()
1040 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); in tegra210_usb2_phy_power_on()
1041 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_power_on() local
1044 unsigned int index = lane->index; in tegra210_usb2_phy_power_on()
1048 port = tegra_xusb_find_usb2_port(padctl, index); in tegra210_usb2_phy_power_on()
1050 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index); in tegra210_usb2_phy_power_on()
1051 return -ENODEV; in tegra210_usb2_phy_power_on()
1054 priv = to_tegra210_xusb_padctl(padctl); in tegra210_usb2_phy_power_on()
1056 if (port->usb3_port_fake != -1) { in tegra210_usb2_phy_power_on()
1057 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_on()
1059 port->usb3_port_fake); in tegra210_usb2_phy_power_on()
1061 port->usb3_port_fake, index); in tegra210_usb2_phy_power_on()
1062 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_on()
1064 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1066 port->usb3_port_fake); in tegra210_usb2_phy_power_on()
1067 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1071 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1073 port->usb3_port_fake); in tegra210_usb2_phy_power_on()
1074 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1078 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1080 port->usb3_port_fake); in tegra210_usb2_phy_power_on()
1081 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_on()
1084 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
1097 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
1099 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_usb2_phy_power_on()
1101 if (port->mode == USB_DR_MODE_UNKNOWN) in tegra210_usb2_phy_power_on()
1103 else if (port->mode == USB_DR_MODE_PERIPHERAL) in tegra210_usb2_phy_power_on()
1105 else if (port->mode == USB_DR_MODE_HOST) in tegra210_usb2_phy_power_on()
1107 else if (port->mode == USB_DR_MODE_OTG) in tegra210_usb2_phy_power_on()
1109 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP); in tegra210_usb2_phy_power_on()
1111 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra210_usb2_phy_power_on()
1117 value |= (priv->fuse.hs_curr_level[index] + in tegra210_usb2_phy_power_on()
1118 usb2->hs_curr_level_offset) << in tegra210_usb2_phy_power_on()
1120 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra210_usb2_phy_power_on()
1122 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra210_usb2_phy_power_on()
1130 value |= (priv->fuse.hs_term_range_adj << in tegra210_usb2_phy_power_on()
1132 (priv->fuse.rpd_ctrl << in tegra210_usb2_phy_power_on()
1134 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra210_usb2_phy_power_on()
1136 value = padctl_readl(padctl, in tegra210_usb2_phy_power_on()
1140 if (port->mode == USB_DR_MODE_HOST) in tegra210_usb2_phy_power_on()
1146 padctl_writel(padctl, value, in tegra210_usb2_phy_power_on()
1149 if (port->supply && port->mode == USB_DR_MODE_HOST) { in tegra210_usb2_phy_power_on()
1150 err = regulator_enable(port->supply); in tegra210_usb2_phy_power_on()
1155 mutex_lock(&padctl->lock); in tegra210_usb2_phy_power_on()
1157 if (pad->enable > 0) { in tegra210_usb2_phy_power_on()
1158 pad->enable++; in tegra210_usb2_phy_power_on()
1159 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
1163 err = clk_prepare_enable(pad->clk); in tegra210_usb2_phy_power_on()
1167 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1176 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1178 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
1180 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_on()
1184 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1186 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra210_usb2_phy_power_on()
1190 clk_disable_unprepare(pad->clk); in tegra210_usb2_phy_power_on()
1192 pad->enable++; in tegra210_usb2_phy_power_on()
1193 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
1198 regulator_disable(port->supply); in tegra210_usb2_phy_power_on()
1199 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
1206 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); in tegra210_usb2_phy_power_off()
1207 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_power_off() local
1211 port = tegra_xusb_find_usb2_port(padctl, lane->index); in tegra210_usb2_phy_power_off()
1213 dev_err(&phy->dev, "no port found for USB2 lane %u\n", in tegra210_usb2_phy_power_off()
1214 lane->index); in tegra210_usb2_phy_power_off()
1215 return -ENODEV; in tegra210_usb2_phy_power_off()
1218 mutex_lock(&padctl->lock); in tegra210_usb2_phy_power_off()
1220 if (port->usb3_port_fake != -1) { in tegra210_usb2_phy_power_off()
1221 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
1223 port->usb3_port_fake); in tegra210_usb2_phy_power_off()
1224 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
1228 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
1230 port->usb3_port_fake); in tegra210_usb2_phy_power_off()
1231 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
1235 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
1237 port->usb3_port_fake); in tegra210_usb2_phy_power_off()
1238 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb2_phy_power_off()
1240 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_off()
1241 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->usb3_port_fake, in tegra210_usb2_phy_power_off()
1243 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb2_phy_power_off()
1246 if (WARN_ON(pad->enable == 0)) in tegra210_usb2_phy_power_off()
1249 if (--pad->enable > 0) in tegra210_usb2_phy_power_off()
1252 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_off()
1254 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra210_usb2_phy_power_off()
1257 regulator_disable(port->supply); in tegra210_usb2_phy_power_off()
1258 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_off()
1272 tegra210_usb2_pad_probe(struct tegra_xusb_padctl *padctl, in tegra210_usb2_pad_probe() argument
1282 return ERR_PTR(-ENOMEM); in tegra210_usb2_pad_probe()
1284 pad = &usb2->base; in tegra210_usb2_pad_probe()
1285 pad->ops = &tegra210_usb2_lane_ops; in tegra210_usb2_pad_probe()
1286 pad->soc = soc; in tegra210_usb2_pad_probe()
1288 err = tegra_xusb_pad_init(pad, padctl, np); in tegra210_usb2_pad_probe()
1294 usb2->clk = devm_clk_get(&pad->dev, "trk"); in tegra210_usb2_pad_probe()
1295 if (IS_ERR(usb2->clk)) { in tegra210_usb2_pad_probe()
1296 err = PTR_ERR(usb2->clk); in tegra210_usb2_pad_probe()
1297 dev_err(&pad->dev, "failed to get trk clock: %d\n", err); in tegra210_usb2_pad_probe()
1305 dev_set_drvdata(&pad->dev, pad); in tegra210_usb2_pad_probe()
1310 device_unregister(&pad->dev); in tegra210_usb2_pad_probe()
1336 "xusb",
1340 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic),
1352 return ERR_PTR(-ENOMEM); in tegra210_hsic_lane_probe()
1354 INIT_LIST_HEAD(&hsic->base.list); in tegra210_hsic_lane_probe()
1355 hsic->base.soc = &pad->soc->lanes[index]; in tegra210_hsic_lane_probe()
1356 hsic->base.index = index; in tegra210_hsic_lane_probe()
1357 hsic->base.pad = pad; in tegra210_hsic_lane_probe()
1358 hsic->base.np = np; in tegra210_hsic_lane_probe()
1360 err = tegra_xusb_lane_parse_dt(&hsic->base, np); in tegra210_hsic_lane_probe()
1366 return &hsic->base; in tegra210_hsic_lane_probe()
1384 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_init() local
1387 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_hsic_phy_init()
1392 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra210_hsic_phy_init()
1394 return tegra210_xusb_padctl_enable(padctl); in tegra210_hsic_phy_init()
1401 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_hsic_phy_exit()
1408 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); in tegra210_hsic_phy_power_on()
1409 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_power_on() local
1410 unsigned int index = lane->index; in tegra210_hsic_phy_power_on()
1414 err = regulator_enable(pad->supply); in tegra210_hsic_phy_power_on()
1418 padctl_writel(padctl, hsic->strobe_trim, in tegra210_hsic_phy_power_on()
1421 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_on()
1424 value |= (hsic->tx_rtune_p << in tegra210_hsic_phy_power_on()
1426 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_on()
1428 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index)); in tegra210_hsic_phy_power_on()
1433 value |= (hsic->rx_strobe_trim << in tegra210_hsic_phy_power_on()
1435 (hsic->rx_data_trim << in tegra210_hsic_phy_power_on()
1437 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index)); in tegra210_hsic_phy_power_on()
1439 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_on()
1455 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_on()
1457 err = clk_prepare_enable(pad->clk); in tegra210_hsic_phy_power_on()
1461 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1470 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1474 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1476 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in tegra210_hsic_phy_power_on()
1480 clk_disable_unprepare(pad->clk); in tegra210_hsic_phy_power_on()
1485 regulator_disable(pad->supply); in tegra210_hsic_phy_power_on()
1492 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); in tegra210_hsic_phy_power_off()
1493 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_power_off() local
1494 unsigned int index = lane->index; in tegra210_hsic_phy_power_off()
1497 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index)); in tegra210_hsic_phy_power_off()
1507 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index)); in tegra210_hsic_phy_power_off()
1509 regulator_disable(pad->supply); in tegra210_hsic_phy_power_off()
1523 tegra210_hsic_pad_probe(struct tegra_xusb_padctl *padctl, in tegra210_hsic_pad_probe() argument
1533 return ERR_PTR(-ENOMEM); in tegra210_hsic_pad_probe()
1535 pad = &hsic->base; in tegra210_hsic_pad_probe()
1536 pad->ops = &tegra210_hsic_lane_ops; in tegra210_hsic_pad_probe()
1537 pad->soc = soc; in tegra210_hsic_pad_probe()
1539 err = tegra_xusb_pad_init(pad, padctl, np); in tegra210_hsic_pad_probe()
1545 hsic->clk = devm_clk_get(&pad->dev, "trk"); in tegra210_hsic_pad_probe()
1546 if (IS_ERR(hsic->clk)) { in tegra210_hsic_pad_probe()
1547 err = PTR_ERR(hsic->clk); in tegra210_hsic_pad_probe()
1548 dev_err(&pad->dev, "failed to get trk clock: %d\n", err); in tegra210_hsic_pad_probe()
1556 dev_set_drvdata(&pad->dev, pad); in tegra210_hsic_pad_probe()
1561 device_unregister(&pad->dev); in tegra210_hsic_pad_probe()
1586 "pcie-x1",
1587 "usb3-ss",
1589 "pcie-x4",
1593 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, pcie),
1594 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, pcie),
1595 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, pcie),
1596 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, pcie),
1597 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, pcie),
1598 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, pcie),
1599 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie),
1611 return ERR_PTR(-ENOMEM); in tegra210_pcie_lane_probe()
1613 INIT_LIST_HEAD(&pcie->base.list); in tegra210_pcie_lane_probe()
1614 pcie->base.soc = &pad->soc->lanes[index]; in tegra210_pcie_lane_probe()
1615 pcie->base.index = index; in tegra210_pcie_lane_probe()
1616 pcie->base.pad = pad; in tegra210_pcie_lane_probe()
1617 pcie->base.np = np; in tegra210_pcie_lane_probe()
1619 err = tegra_xusb_lane_parse_dt(&pcie->base, np); in tegra210_pcie_lane_probe()
1625 return &pcie->base; in tegra210_pcie_lane_probe()
1644 return tegra210_xusb_padctl_enable(lane->pad->padctl); in tegra210_pcie_phy_init()
1651 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_pcie_phy_exit()
1657 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pcie_phy_power_on() local
1661 mutex_lock(&padctl->lock); in tegra210_pcie_phy_power_on()
1663 err = tegra210_pex_uphy_enable(padctl); in tegra210_pcie_phy_power_on()
1667 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_on()
1668 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); in tegra210_pcie_phy_power_on()
1669 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_on()
1672 mutex_unlock(&padctl->lock); in tegra210_pcie_phy_power_on()
1679 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pcie_phy_power_off() local
1682 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_off()
1683 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); in tegra210_pcie_phy_power_off()
1684 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_pcie_phy_power_off()
1686 tegra210_pex_uphy_disable(padctl); in tegra210_pcie_phy_power_off()
1700 tegra210_pcie_pad_probe(struct tegra_xusb_padctl *padctl, in tegra210_pcie_pad_probe() argument
1710 return ERR_PTR(-ENOMEM); in tegra210_pcie_pad_probe()
1712 pad = &pcie->base; in tegra210_pcie_pad_probe()
1713 pad->ops = &tegra210_pcie_lane_ops; in tegra210_pcie_pad_probe()
1714 pad->soc = soc; in tegra210_pcie_pad_probe()
1716 err = tegra_xusb_pad_init(pad, padctl, np); in tegra210_pcie_pad_probe()
1722 pcie->pll = devm_clk_get(&pad->dev, "pll"); in tegra210_pcie_pad_probe()
1723 if (IS_ERR(pcie->pll)) { in tegra210_pcie_pad_probe()
1724 err = PTR_ERR(pcie->pll); in tegra210_pcie_pad_probe()
1725 dev_err(&pad->dev, "failed to get PLL: %d\n", err); in tegra210_pcie_pad_probe()
1729 pcie->rst = devm_reset_control_get(&pad->dev, "phy"); in tegra210_pcie_pad_probe()
1730 if (IS_ERR(pcie->rst)) { in tegra210_pcie_pad_probe()
1731 err = PTR_ERR(pcie->rst); in tegra210_pcie_pad_probe()
1732 dev_err(&pad->dev, "failed to get PCIe pad reset: %d\n", err); in tegra210_pcie_pad_probe()
1740 dev_set_drvdata(&pad->dev, pad); in tegra210_pcie_pad_probe()
1745 device_unregister(&pad->dev); in tegra210_pcie_pad_probe()
1770 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, pcie),
1782 return ERR_PTR(-ENOMEM); in tegra210_sata_lane_probe()
1784 INIT_LIST_HEAD(&sata->base.list); in tegra210_sata_lane_probe()
1785 sata->base.soc = &pad->soc->lanes[index]; in tegra210_sata_lane_probe()
1786 sata->base.index = index; in tegra210_sata_lane_probe()
1787 sata->base.pad = pad; in tegra210_sata_lane_probe()
1788 sata->base.np = np; in tegra210_sata_lane_probe()
1790 err = tegra_xusb_lane_parse_dt(&sata->base, np); in tegra210_sata_lane_probe()
1796 return &sata->base; in tegra210_sata_lane_probe()
1815 return tegra210_xusb_padctl_enable(lane->pad->padctl); in tegra210_sata_phy_init()
1822 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_sata_phy_exit()
1828 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_sata_phy_power_on() local
1832 mutex_lock(&padctl->lock); in tegra210_sata_phy_power_on()
1834 err = tegra210_sata_uphy_enable(padctl, false); in tegra210_sata_phy_power_on()
1838 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_on()
1839 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); in tegra210_sata_phy_power_on()
1840 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_on()
1843 mutex_unlock(&padctl->lock); in tegra210_sata_phy_power_on()
1850 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_sata_phy_power_off() local
1853 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_off()
1854 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); in tegra210_sata_phy_power_off()
1855 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX); in tegra210_sata_phy_power_off()
1857 tegra210_sata_uphy_disable(lane->pad->padctl); in tegra210_sata_phy_power_off()
1871 tegra210_sata_pad_probe(struct tegra_xusb_padctl *padctl, in tegra210_sata_pad_probe() argument
1881 return ERR_PTR(-ENOMEM); in tegra210_sata_pad_probe()
1883 pad = &sata->base; in tegra210_sata_pad_probe()
1884 pad->ops = &tegra210_sata_lane_ops; in tegra210_sata_pad_probe()
1885 pad->soc = soc; in tegra210_sata_pad_probe()
1887 err = tegra_xusb_pad_init(pad, padctl, np); in tegra210_sata_pad_probe()
1893 sata->rst = devm_reset_control_get(&pad->dev, "phy"); in tegra210_sata_pad_probe()
1894 if (IS_ERR(sata->rst)) { in tegra210_sata_pad_probe()
1895 err = PTR_ERR(sata->rst); in tegra210_sata_pad_probe()
1896 dev_err(&pad->dev, "failed to get SATA pad reset: %d\n", err); in tegra210_sata_pad_probe()
1904 dev_set_drvdata(&pad->dev, pad); in tegra210_sata_pad_probe()
1909 device_unregister(&pad->dev); in tegra210_sata_pad_probe()
1952 return tegra_xusb_find_lane(port->padctl, "usb2", port->index); in tegra210_usb2_port_map()
1975 return tegra_xusb_find_lane(port->padctl, "hsic", port->index); in tegra210_hsic_port_map()
1988 struct tegra_xusb_padctl *padctl = port->padctl; in tegra210_usb3_port_enable() local
1989 struct tegra_xusb_lane *lane = usb3->base.lane; in tegra210_usb3_port_enable()
1990 unsigned int index = port->index; in tegra210_usb3_port_enable()
1994 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_enable()
1996 if (!usb3->internal) in tegra210_usb3_port_enable()
2002 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port); in tegra210_usb3_port_enable()
2003 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_enable()
2006 * TODO: move this code into the PCIe/SATA PHY ->power_on() callbacks in tegra210_usb3_port_enable()
2010 err = regulator_enable(usb3->supply); in tegra210_usb3_port_enable()
2014 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); in tegra210_usb3_port_enable()
2019 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index)); in tegra210_usb3_port_enable()
2021 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); in tegra210_usb3_port_enable()
2026 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index)); in tegra210_usb3_port_enable()
2028 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL, in tegra210_usb3_port_enable()
2031 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); in tegra210_usb3_port_enable()
2036 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index)); in tegra210_usb3_port_enable()
2038 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL, in tegra210_usb3_port_enable()
2041 if (lane->pad == padctl->sata) in tegra210_usb3_port_enable()
2042 err = tegra210_sata_uphy_enable(padctl, true); in tegra210_usb3_port_enable()
2044 err = tegra210_pex_uphy_enable(padctl); in tegra210_usb3_port_enable()
2047 dev_err(&port->dev, "%s: failed to enable UPHY: %d\n", in tegra210_usb3_port_enable()
2052 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
2054 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
2058 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
2060 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
2064 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
2066 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_enable()
2074 struct tegra_xusb_padctl *padctl = port->padctl; in tegra210_usb3_port_disable() local
2075 struct tegra_xusb_lane *lane = port->lane; in tegra210_usb3_port_disable()
2076 unsigned int index = port->index; in tegra210_usb3_port_disable()
2079 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
2081 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
2085 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
2087 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
2091 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
2093 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1); in tegra210_usb3_port_disable()
2095 if (lane->pad == padctl->sata) in tegra210_usb3_port_disable()
2096 tegra210_sata_uphy_disable(padctl); in tegra210_usb3_port_disable()
2098 tegra210_pex_uphy_disable(padctl); in tegra210_usb3_port_disable()
2100 regulator_disable(usb3->supply); in tegra210_usb3_port_disable()
2102 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_disable()
2105 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP); in tegra210_usb3_port_disable()
2121 return tegra_xusb_port_find_lane(port, tegra210_usb3_map, "usb3-ss"); in tegra210_usb3_port_map()
2134 struct tegra_xusb_padctl *padctl; in tegra210_utmi_port_reset() local
2139 padctl = lane->pad->padctl; in tegra210_utmi_port_reset()
2141 value = padctl_readl(padctl, in tegra210_utmi_port_reset()
2142 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(lane->index)); in tegra210_utmi_port_reset()
2146 tegra210_xusb_padctl_vbus_override(padctl, false); in tegra210_utmi_port_reset()
2147 tegra210_xusb_padctl_vbus_override(padctl, true); in tegra210_utmi_port_reset()
2165 for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) { in tegra210_xusb_read_fuse_calibration()
2166 fuse->hs_curr_level[i] = in tegra210_xusb_read_fuse_calibration()
2171 fuse->hs_term_range_adj = in tegra210_xusb_read_fuse_calibration()
2179 fuse->rpd_ctrl = in tegra210_xusb_read_fuse_calibration()
2190 struct tegra210_xusb_padctl *padctl; in tegra210_xusb_padctl_probe() local
2193 padctl = devm_kzalloc(dev, sizeof(*padctl), GFP_KERNEL); in tegra210_xusb_padctl_probe()
2194 if (!padctl) in tegra210_xusb_padctl_probe()
2195 return ERR_PTR(-ENOMEM); in tegra210_xusb_padctl_probe()
2197 padctl->base.dev = dev; in tegra210_xusb_padctl_probe()
2198 padctl->base.soc = soc; in tegra210_xusb_padctl_probe()
2200 err = tegra210_xusb_read_fuse_calibration(&padctl->fuse); in tegra210_xusb_padctl_probe()
2204 return &padctl->base; in tegra210_xusb_padctl_probe()
2207 static void tegra210_xusb_padctl_remove(struct tegra_xusb_padctl *padctl) in tegra210_xusb_padctl_remove() argument
2221 "avdd-pll-utmip",
2222 "avdd-pll-uerefe",
2223 "dvdd-pex-pll",
2224 "hvdd-pex-pll-e",
2252 MODULE_DESCRIPTION("NVIDIA Tegra 210 XUSB Pad Controller driver");