Lines Matching +full:rx +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
9 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/dma-imx.h>
101 void (*rx)(struct spi_imx_data *); member
123 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
128 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
133 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
138 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
144 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
146 if (spi_imx->rx_buf) { \
147 *(type *)spi_imx->rx_buf = val; \
148 spi_imx->rx_buf += sizeof(type); \
151 spi_imx->remainder -= sizeof(type); \
159 if (spi_imx->tx_buf) { \
160 val = *(type *)spi_imx->tx_buf; \
161 spi_imx->tx_buf += sizeof(type); \
164 spi_imx->count -= sizeof(type); \
166 writel(val, spi_imx->base + MXC_CSPITXDATA); \
228 if (!use_dma || master->fallback) in spi_imx_can_dma()
231 if (!master->dma_rx) in spi_imx_can_dma()
234 if (spi_imx->slave_mode) in spi_imx_can_dma()
237 if (transfer->len < spi_imx->devtype_data->fifo_size) in spi_imx_can_dma()
240 spi_imx->dynamic_burst = 0; in spi_imx_can_dma()
286 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap_u32()
291 if (spi_imx->rx_buf) { in spi_imx_buf_rx_swap_u32()
293 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_buf_rx_swap_u32()
299 *(u32 *)spi_imx->rx_buf = val; in spi_imx_buf_rx_swap_u32()
300 spi_imx->rx_buf += sizeof(u32); in spi_imx_buf_rx_swap_u32()
303 spi_imx->remainder -= sizeof(u32); in spi_imx_buf_rx_swap_u32()
311 unaligned = spi_imx->remainder % 4; in spi_imx_buf_rx_swap()
318 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { in spi_imx_buf_rx_swap()
323 val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap()
325 while (unaligned--) { in spi_imx_buf_rx_swap()
326 if (spi_imx->rx_buf) { in spi_imx_buf_rx_swap()
327 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; in spi_imx_buf_rx_swap()
328 spi_imx->rx_buf++; in spi_imx_buf_rx_swap()
330 spi_imx->remainder--; in spi_imx_buf_rx_swap()
341 if (spi_imx->tx_buf) { in spi_imx_buf_tx_swap_u32()
342 val = *(u32 *)spi_imx->tx_buf; in spi_imx_buf_tx_swap_u32()
343 spi_imx->tx_buf += sizeof(u32); in spi_imx_buf_tx_swap_u32()
346 spi_imx->count -= sizeof(u32); in spi_imx_buf_tx_swap_u32()
348 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_buf_tx_swap_u32()
355 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap_u32()
363 unaligned = spi_imx->count % 4; in spi_imx_buf_tx_swap()
370 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { in spi_imx_buf_tx_swap()
375 while (unaligned--) { in spi_imx_buf_tx_swap()
376 if (spi_imx->tx_buf) { in spi_imx_buf_tx_swap()
377 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); in spi_imx_buf_tx_swap()
378 spi_imx->tx_buf++; in spi_imx_buf_tx_swap()
380 spi_imx->count--; in spi_imx_buf_tx_swap()
383 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap()
388 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); in mx53_ecspi_rx_slave()
390 if (spi_imx->rx_buf) { in mx53_ecspi_rx_slave()
391 int n_bytes = spi_imx->slave_burst % sizeof(val); in mx53_ecspi_rx_slave()
396 memcpy(spi_imx->rx_buf, in mx53_ecspi_rx_slave()
397 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); in mx53_ecspi_rx_slave()
399 spi_imx->rx_buf += n_bytes; in mx53_ecspi_rx_slave()
400 spi_imx->slave_burst -= n_bytes; in mx53_ecspi_rx_slave()
403 spi_imx->remainder -= sizeof(u32); in mx53_ecspi_rx_slave()
409 int n_bytes = spi_imx->count % sizeof(val); in mx53_ecspi_tx_slave()
414 if (spi_imx->tx_buf) { in mx53_ecspi_tx_slave()
415 memcpy(((u8 *)&val) + sizeof(val) - n_bytes, in mx53_ecspi_tx_slave()
416 spi_imx->tx_buf, n_bytes); in mx53_ecspi_tx_slave()
418 spi_imx->tx_buf += n_bytes; in mx53_ecspi_tx_slave()
421 spi_imx->count -= n_bytes; in mx53_ecspi_tx_slave()
423 writel(val, spi_imx->base + MXC_CSPITXDATA); in mx53_ecspi_tx_slave()
431 * there are two 4-bit dividers, the pre-divider divides by in mx51_ecspi_clkdiv()
432 * $pre, the post-divider by 2^$post in mx51_ecspi_clkdiv()
435 unsigned int fin = spi_imx->spi_clk; in mx51_ecspi_clkdiv()
440 post = fls(fin) - fls(fspi); in mx51_ecspi_clkdiv()
446 post = max(4U, post) - 4; in mx51_ecspi_clkdiv()
448 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", in mx51_ecspi_clkdiv()
453 pre = DIV_ROUND_UP(fin, fspi << post) - 1; in mx51_ecspi_clkdiv()
455 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", in mx51_ecspi_clkdiv()
478 writel(val, spi_imx->base + MX51_ECSPI_INT); in mx51_ecspi_intctrl()
485 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_trigger()
487 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_trigger()
492 writel(0, spi_imx->base + MX51_ECSPI_DMA); in mx51_disable_dma()
497 u32 ctrl; in mx51_ecspi_disable() local
499 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_disable()
500 ctrl &= ~MX51_ECSPI_CTRL_ENABLE; in mx51_ecspi_disable()
501 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_disable()
507 struct spi_device *spi = msg->spi; in mx51_ecspi_prepare_message()
509 u32 ctrl = MX51_ECSPI_CTRL_ENABLE; in mx51_ecspi_prepare_message() local
512 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); in mx51_ecspi_prepare_message()
515 if (spi_imx->slave_mode) in mx51_ecspi_prepare_message()
516 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK; in mx51_ecspi_prepare_message()
518 ctrl |= MX51_ECSPI_CTRL_MODE_MASK; in mx51_ecspi_prepare_message()
523 if (spi->mode & SPI_READY) in mx51_ecspi_prepare_message()
524 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); in mx51_ecspi_prepare_message()
527 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); in mx51_ecspi_prepare_message()
530 * The ctrl register must be written first, with the EN bit set other in mx51_ecspi_prepare_message()
533 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_message()
535 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); in mx51_ecspi_prepare_message()
536 if (spi->mode & SPI_LOOP) in mx51_ecspi_prepare_message()
540 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); in mx51_ecspi_prepare_message()
547 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) in mx51_ecspi_prepare_message()
548 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); in mx51_ecspi_prepare_message()
550 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); in mx51_ecspi_prepare_message()
552 if (spi->mode & SPI_CPHA) in mx51_ecspi_prepare_message()
553 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); in mx51_ecspi_prepare_message()
555 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); in mx51_ecspi_prepare_message()
557 if (spi->mode & SPI_CPOL) { in mx51_ecspi_prepare_message()
558 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); in mx51_ecspi_prepare_message()
559 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); in mx51_ecspi_prepare_message()
561 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); in mx51_ecspi_prepare_message()
562 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); in mx51_ecspi_prepare_message()
565 if (spi->mode & SPI_CS_HIGH) in mx51_ecspi_prepare_message()
566 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); in mx51_ecspi_prepare_message()
568 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); in mx51_ecspi_prepare_message()
570 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); in mx51_ecspi_prepare_message()
583 * Because spi_imx->spi_bus_clk is only set in bitbang prepare_message in mx51_ecspi_prepare_message()
589 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in mx51_ecspi_prepare_message()
590 if (!xfer->speed_hz) in mx51_ecspi_prepare_message()
592 min_speed_hz = min(xfer->speed_hz, min_speed_hz); in mx51_ecspi_prepare_message()
607 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_transfer() local
611 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; in mx51_ecspi_prepare_transfer()
612 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) in mx51_ecspi_prepare_transfer()
613 ctrl |= (spi_imx->slave_burst * 8 - 1) in mx51_ecspi_prepare_transfer()
616 ctrl |= (spi_imx->bits_per_word - 1) in mx51_ecspi_prepare_transfer()
620 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET | in mx51_ecspi_prepare_transfer()
622 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk); in mx51_ecspi_prepare_transfer()
623 spi_imx->spi_bus_clk = clk; in mx51_ecspi_prepare_transfer()
625 if (spi_imx->usedma) in mx51_ecspi_prepare_transfer()
626 ctrl |= MX51_ECSPI_CTRL_SMC; in mx51_ecspi_prepare_transfer()
628 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_transfer()
639 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | in mx51_setup_wml()
640 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) | in mx51_setup_wml()
641 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | in mx51_setup_wml()
643 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); in mx51_setup_wml()
648 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; in mx51_ecspi_rx_available()
655 readl(spi_imx->base + MXC_CSPIRXDATA); in mx51_ecspi_reset()
698 writel(val, spi_imx->base + MXC_CSPIINT); in mx31_intctrl()
705 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx31_trigger()
707 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx31_trigger()
722 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << in mx31_prepare_transfer()
724 spi_imx->spi_bus_clk = clk; in mx31_prepare_transfer()
727 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; in mx31_prepare_transfer()
730 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; in mx31_prepare_transfer()
733 if (spi->mode & SPI_CPHA) in mx31_prepare_transfer()
735 if (spi->mode & SPI_CPOL) in mx31_prepare_transfer()
737 if (spi->mode & SPI_CS_HIGH) in mx31_prepare_transfer()
739 if (!spi->cs_gpiod) in mx31_prepare_transfer()
740 reg |= (spi->chip_select) << in mx31_prepare_transfer()
744 if (spi_imx->usedma) in mx31_prepare_transfer()
747 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx31_prepare_transfer()
749 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); in mx31_prepare_transfer()
750 if (spi->mode & SPI_LOOP) in mx31_prepare_transfer()
754 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); in mx31_prepare_transfer()
756 if (spi_imx->usedma) { in mx31_prepare_transfer()
762 spi_imx->base + MX31_CSPI_DMAREG); in mx31_prepare_transfer()
770 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; in mx31_rx_available()
776 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) in mx31_reset()
777 readl(spi_imx->base + MXC_CSPIRXDATA); in mx31_reset()
802 writel(val, spi_imx->base + MXC_CSPIINT); in mx21_intctrl()
809 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx21_trigger()
811 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx21_trigger()
827 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk) in mx21_prepare_transfer()
829 spi_imx->spi_bus_clk = clk; in mx21_prepare_transfer()
831 reg |= spi_imx->bits_per_word - 1; in mx21_prepare_transfer()
833 if (spi->mode & SPI_CPHA) in mx21_prepare_transfer()
835 if (spi->mode & SPI_CPOL) in mx21_prepare_transfer()
837 if (spi->mode & SPI_CS_HIGH) in mx21_prepare_transfer()
839 if (!spi->cs_gpiod) in mx21_prepare_transfer()
840 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT; in mx21_prepare_transfer()
842 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx21_prepare_transfer()
849 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; in mx21_rx_available()
854 writel(1, spi_imx->base + MXC_RESET); in mx21_reset()
877 writel(val, spi_imx->base + MXC_CSPIINT); in mx1_intctrl()
884 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx1_trigger()
886 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx1_trigger()
901 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << in mx1_prepare_transfer()
903 spi_imx->spi_bus_clk = clk; in mx1_prepare_transfer()
905 reg |= spi_imx->bits_per_word - 1; in mx1_prepare_transfer()
907 if (spi->mode & SPI_CPHA) in mx1_prepare_transfer()
909 if (spi->mode & SPI_CPOL) in mx1_prepare_transfer()
912 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx1_prepare_transfer()
919 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; in mx1_rx_available()
924 writel(1, spi_imx->base + MXC_RESET); in mx1_reset()
1033 .name = "imx1-cspi",
1036 .name = "imx21-cspi",
1039 .name = "imx27-cspi",
1042 .name = "imx31-cspi",
1045 .name = "imx35-cspi",
1048 .name = "imx51-ecspi",
1051 .name = "imx53-ecspi",
1059 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1060 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1061 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1062 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1063 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1064 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1065 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1072 u32 ctrl; in spi_imx_set_burst_len() local
1074 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in spi_imx_set_burst_len()
1075 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; in spi_imx_set_burst_len()
1076 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); in spi_imx_set_burst_len()
1077 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in spi_imx_set_burst_len()
1084 if (spi_imx->dynamic_burst) in spi_imx_push()
1087 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_push()
1093 if (!spi_imx->remainder) { in spi_imx_push()
1094 if (spi_imx->dynamic_burst) { in spi_imx_push()
1097 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; in spi_imx_push()
1104 spi_imx->remainder = burst_len; in spi_imx_push()
1106 spi_imx->remainder = fifo_words; in spi_imx_push()
1110 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { in spi_imx_push()
1111 if (!spi_imx->count) in spi_imx_push()
1113 if (spi_imx->dynamic_burst && in spi_imx_push()
1114 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, in spi_imx_push()
1117 spi_imx->tx(spi_imx); in spi_imx_push()
1118 spi_imx->txfifo++; in spi_imx_push()
1121 if (!spi_imx->slave_mode) in spi_imx_push()
1122 spi_imx->devtype_data->trigger(spi_imx); in spi_imx_push()
1129 while (spi_imx->txfifo && in spi_imx_isr()
1130 spi_imx->devtype_data->rx_available(spi_imx)) { in spi_imx_isr()
1131 spi_imx->rx(spi_imx); in spi_imx_isr()
1132 spi_imx->txfifo--; in spi_imx_isr()
1135 if (spi_imx->count) { in spi_imx_isr()
1140 if (spi_imx->txfifo) { in spi_imx_isr()
1141 /* No data left to push, but still waiting for rx data, in spi_imx_isr()
1144 spi_imx->devtype_data->intctrl( in spi_imx_isr()
1149 spi_imx->devtype_data->intctrl(spi_imx, 0); in spi_imx_isr()
1150 complete(&spi_imx->xfer_done); in spi_imx_isr()
1159 struct dma_slave_config rx = {}, tx = {}; in spi_imx_dma_configure() local
1162 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { in spi_imx_dma_configure()
1173 return -EINVAL; in spi_imx_dma_configure()
1177 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; in spi_imx_dma_configure()
1179 tx.dst_maxburst = spi_imx->wml; in spi_imx_dma_configure()
1180 ret = dmaengine_slave_config(master->dma_tx, &tx); in spi_imx_dma_configure()
1182 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); in spi_imx_dma_configure()
1186 rx.direction = DMA_DEV_TO_MEM; in spi_imx_dma_configure()
1187 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; in spi_imx_dma_configure()
1188 rx.src_addr_width = buswidth; in spi_imx_dma_configure()
1189 rx.src_maxburst = spi_imx->wml; in spi_imx_dma_configure()
1190 ret = dmaengine_slave_config(master->dma_rx, &rx); in spi_imx_dma_configure()
1192 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); in spi_imx_dma_configure()
1202 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in spi_imx_setupxfer()
1207 if (!t->speed_hz) { in spi_imx_setupxfer()
1208 if (!spi->max_speed_hz) { in spi_imx_setupxfer()
1209 dev_err(&spi->dev, "no speed_hz provided!\n"); in spi_imx_setupxfer()
1210 return -EINVAL; in spi_imx_setupxfer()
1212 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n"); in spi_imx_setupxfer()
1213 spi_imx->spi_bus_clk = spi->max_speed_hz; in spi_imx_setupxfer()
1215 spi_imx->spi_bus_clk = t->speed_hz; in spi_imx_setupxfer()
1217 spi_imx->bits_per_word = t->bits_per_word; in spi_imx_setupxfer()
1220 * Initialize the functions for transfer. To transfer non byte-aligned in spi_imx_setupxfer()
1221 * words, we have to use multiple word-size bursts, we can't use in spi_imx_setupxfer()
1224 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode && in spi_imx_setupxfer()
1225 (spi_imx->bits_per_word == 8 || in spi_imx_setupxfer()
1226 spi_imx->bits_per_word == 16 || in spi_imx_setupxfer()
1227 spi_imx->bits_per_word == 32)) { in spi_imx_setupxfer()
1229 spi_imx->rx = spi_imx_buf_rx_swap; in spi_imx_setupxfer()
1230 spi_imx->tx = spi_imx_buf_tx_swap; in spi_imx_setupxfer()
1231 spi_imx->dynamic_burst = 1; in spi_imx_setupxfer()
1234 if (spi_imx->bits_per_word <= 8) { in spi_imx_setupxfer()
1235 spi_imx->rx = spi_imx_buf_rx_u8; in spi_imx_setupxfer()
1236 spi_imx->tx = spi_imx_buf_tx_u8; in spi_imx_setupxfer()
1237 } else if (spi_imx->bits_per_word <= 16) { in spi_imx_setupxfer()
1238 spi_imx->rx = spi_imx_buf_rx_u16; in spi_imx_setupxfer()
1239 spi_imx->tx = spi_imx_buf_tx_u16; in spi_imx_setupxfer()
1241 spi_imx->rx = spi_imx_buf_rx_u32; in spi_imx_setupxfer()
1242 spi_imx->tx = spi_imx_buf_tx_u32; in spi_imx_setupxfer()
1244 spi_imx->dynamic_burst = 0; in spi_imx_setupxfer()
1247 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) in spi_imx_setupxfer()
1248 spi_imx->usedma = true; in spi_imx_setupxfer()
1250 spi_imx->usedma = false; in spi_imx_setupxfer()
1252 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) { in spi_imx_setupxfer()
1253 spi_imx->rx = mx53_ecspi_rx_slave; in spi_imx_setupxfer()
1254 spi_imx->tx = mx53_ecspi_tx_slave; in spi_imx_setupxfer()
1255 spi_imx->slave_burst = t->len; in spi_imx_setupxfer()
1258 spi_imx->devtype_data->prepare_transfer(spi_imx, spi); in spi_imx_setupxfer()
1265 struct spi_master *master = spi_imx->bitbang.master; in spi_imx_sdma_exit()
1267 if (master->dma_rx) { in spi_imx_sdma_exit()
1268 dma_release_channel(master->dma_rx); in spi_imx_sdma_exit()
1269 master->dma_rx = NULL; in spi_imx_sdma_exit()
1272 if (master->dma_tx) { in spi_imx_sdma_exit()
1273 dma_release_channel(master->dma_tx); in spi_imx_sdma_exit()
1274 master->dma_tx = NULL; in spi_imx_sdma_exit()
1287 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; in spi_imx_sdma_init()
1290 master->dma_tx = dma_request_chan(dev, "tx"); in spi_imx_sdma_init()
1291 if (IS_ERR(master->dma_tx)) { in spi_imx_sdma_init()
1292 ret = PTR_ERR(master->dma_tx); in spi_imx_sdma_init()
1294 master->dma_tx = NULL; in spi_imx_sdma_init()
1298 /* Prepare for RX : */ in spi_imx_sdma_init()
1299 master->dma_rx = dma_request_chan(dev, "rx"); in spi_imx_sdma_init()
1300 if (IS_ERR(master->dma_rx)) { in spi_imx_sdma_init()
1301 ret = PTR_ERR(master->dma_rx); in spi_imx_sdma_init()
1302 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); in spi_imx_sdma_init()
1303 master->dma_rx = NULL; in spi_imx_sdma_init()
1307 init_completion(&spi_imx->dma_rx_completion); in spi_imx_sdma_init()
1308 init_completion(&spi_imx->dma_tx_completion); in spi_imx_sdma_init()
1309 master->can_dma = spi_imx_can_dma; in spi_imx_sdma_init()
1310 master->max_dma_len = MAX_SDMA_BD_BYTES; in spi_imx_sdma_init()
1311 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | in spi_imx_sdma_init()
1324 complete(&spi_imx->dma_rx_completion); in spi_imx_dma_rx_callback()
1331 complete(&spi_imx->dma_tx_completion); in spi_imx_dma_tx_callback()
1339 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; in spi_imx_calculate_timeout()
1354 struct spi_master *master = spi_imx->bitbang.master; in spi_imx_dma_transfer()
1355 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; in spi_imx_dma_transfer() local
1356 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); in spi_imx_dma_transfer()
1361 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); in spi_imx_dma_transfer()
1362 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { in spi_imx_dma_transfer()
1370 spi_imx->wml = i; in spi_imx_dma_transfer()
1376 if (!spi_imx->devtype_data->setup_wml) { in spi_imx_dma_transfer()
1377 dev_err(spi_imx->dev, "No setup_wml()?\n"); in spi_imx_dma_transfer()
1378 ret = -EINVAL; in spi_imx_dma_transfer()
1381 spi_imx->devtype_data->setup_wml(spi_imx); in spi_imx_dma_transfer()
1384 * The TX DMA setup starts the transfer, so make sure RX is configured in spi_imx_dma_transfer()
1387 desc_rx = dmaengine_prep_slave_sg(master->dma_rx, in spi_imx_dma_transfer()
1388 rx->sgl, rx->nents, DMA_DEV_TO_MEM, in spi_imx_dma_transfer()
1391 ret = -EINVAL; in spi_imx_dma_transfer()
1395 desc_rx->callback = spi_imx_dma_rx_callback; in spi_imx_dma_transfer()
1396 desc_rx->callback_param = (void *)spi_imx; in spi_imx_dma_transfer()
1398 reinit_completion(&spi_imx->dma_rx_completion); in spi_imx_dma_transfer()
1399 dma_async_issue_pending(master->dma_rx); in spi_imx_dma_transfer()
1401 desc_tx = dmaengine_prep_slave_sg(master->dma_tx, in spi_imx_dma_transfer()
1402 tx->sgl, tx->nents, DMA_MEM_TO_DEV, in spi_imx_dma_transfer()
1405 dmaengine_terminate_all(master->dma_tx); in spi_imx_dma_transfer()
1406 dmaengine_terminate_all(master->dma_rx); in spi_imx_dma_transfer()
1407 return -EINVAL; in spi_imx_dma_transfer()
1410 desc_tx->callback = spi_imx_dma_tx_callback; in spi_imx_dma_transfer()
1411 desc_tx->callback_param = (void *)spi_imx; in spi_imx_dma_transfer()
1413 reinit_completion(&spi_imx->dma_tx_completion); in spi_imx_dma_transfer()
1414 dma_async_issue_pending(master->dma_tx); in spi_imx_dma_transfer()
1416 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); in spi_imx_dma_transfer()
1419 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, in spi_imx_dma_transfer()
1422 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); in spi_imx_dma_transfer()
1423 dmaengine_terminate_all(master->dma_tx); in spi_imx_dma_transfer()
1424 dmaengine_terminate_all(master->dma_rx); in spi_imx_dma_transfer()
1425 return -ETIMEDOUT; in spi_imx_dma_transfer()
1428 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, in spi_imx_dma_transfer()
1431 dev_err(&master->dev, "I/O Error in DMA RX\n"); in spi_imx_dma_transfer()
1432 spi_imx->devtype_data->reset(spi_imx); in spi_imx_dma_transfer()
1433 dmaengine_terminate_all(master->dma_rx); in spi_imx_dma_transfer()
1434 return -ETIMEDOUT; in spi_imx_dma_transfer()
1437 return transfer->len; in spi_imx_dma_transfer()
1440 transfer->error |= SPI_TRANS_FAIL_NO_START; in spi_imx_dma_transfer()
1447 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in spi_imx_pio_transfer()
1451 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_pio_transfer()
1452 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_pio_transfer()
1453 spi_imx->count = transfer->len; in spi_imx_pio_transfer()
1454 spi_imx->txfifo = 0; in spi_imx_pio_transfer()
1455 spi_imx->remainder = 0; in spi_imx_pio_transfer()
1457 reinit_completion(&spi_imx->xfer_done); in spi_imx_pio_transfer()
1461 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); in spi_imx_pio_transfer()
1463 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); in spi_imx_pio_transfer()
1465 timeout = wait_for_completion_timeout(&spi_imx->xfer_done, in spi_imx_pio_transfer()
1468 dev_err(&spi->dev, "I/O Error in PIO\n"); in spi_imx_pio_transfer()
1469 spi_imx->devtype_data->reset(spi_imx); in spi_imx_pio_transfer()
1470 return -ETIMEDOUT; in spi_imx_pio_transfer()
1473 return transfer->len; in spi_imx_pio_transfer()
1479 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in spi_imx_pio_transfer_slave()
1480 int ret = transfer->len; in spi_imx_pio_transfer_slave()
1483 transfer->len > MX53_MAX_TRANSFER_BYTES) { in spi_imx_pio_transfer_slave()
1484 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", in spi_imx_pio_transfer_slave()
1486 return -EMSGSIZE; in spi_imx_pio_transfer_slave()
1489 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_pio_transfer_slave()
1490 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_pio_transfer_slave()
1491 spi_imx->count = transfer->len; in spi_imx_pio_transfer_slave()
1492 spi_imx->txfifo = 0; in spi_imx_pio_transfer_slave()
1493 spi_imx->remainder = 0; in spi_imx_pio_transfer_slave()
1495 reinit_completion(&spi_imx->xfer_done); in spi_imx_pio_transfer_slave()
1496 spi_imx->slave_aborted = false; in spi_imx_pio_transfer_slave()
1500 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); in spi_imx_pio_transfer_slave()
1502 if (wait_for_completion_interruptible(&spi_imx->xfer_done) || in spi_imx_pio_transfer_slave()
1503 spi_imx->slave_aborted) { in spi_imx_pio_transfer_slave()
1504 dev_dbg(&spi->dev, "interrupted\n"); in spi_imx_pio_transfer_slave()
1505 ret = -EINTR; in spi_imx_pio_transfer_slave()
1514 if (spi_imx->devtype_data->disable) in spi_imx_pio_transfer_slave()
1515 spi_imx->devtype_data->disable(spi_imx); in spi_imx_pio_transfer_slave()
1523 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in spi_imx_transfer()
1525 transfer->effective_speed_hz = spi_imx->spi_bus_clk; in spi_imx_transfer()
1528 while (spi_imx->devtype_data->rx_available(spi_imx)) in spi_imx_transfer()
1529 readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_transfer()
1531 if (spi_imx->slave_mode) in spi_imx_transfer()
1534 if (spi_imx->usedma) in spi_imx_transfer()
1542 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, in spi_imx_setup()
1543 spi->mode, spi->bits_per_word, spi->max_speed_hz); in spi_imx_setup()
1558 ret = pm_runtime_get_sync(spi_imx->dev); in spi_imx_prepare_message()
1560 pm_runtime_put_noidle(spi_imx->dev); in spi_imx_prepare_message()
1561 dev_err(spi_imx->dev, "failed to enable clock\n"); in spi_imx_prepare_message()
1565 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); in spi_imx_prepare_message()
1567 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_prepare_message()
1568 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_prepare_message()
1579 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_unprepare_message()
1580 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_unprepare_message()
1588 spi_imx->slave_aborted = true; in spi_imx_slave_abort()
1589 complete(&spi_imx->xfer_done); in spi_imx_slave_abort()
1596 struct device_node *np = pdev->dev.of_node; in spi_imx_probe()
1598 of_match_device(spi_imx_dt_ids, &pdev->dev); in spi_imx_probe()
1603 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data : in spi_imx_probe()
1604 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; in spi_imx_probe()
1608 slave_mode = devtype_data->has_slavemode && in spi_imx_probe()
1609 of_property_read_bool(np, "spi-slave"); in spi_imx_probe()
1611 master = spi_alloc_slave(&pdev->dev, in spi_imx_probe()
1614 master = spi_alloc_master(&pdev->dev, in spi_imx_probe()
1617 return -ENOMEM; in spi_imx_probe()
1619 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); in spi_imx_probe()
1627 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); in spi_imx_probe()
1628 master->bus_num = np ? -1 : pdev->id; in spi_imx_probe()
1629 master->use_gpio_descriptors = true; in spi_imx_probe()
1632 spi_imx->bitbang.master = master; in spi_imx_probe()
1633 spi_imx->dev = &pdev->dev; in spi_imx_probe()
1634 spi_imx->slave_mode = slave_mode; in spi_imx_probe()
1636 spi_imx->devtype_data = devtype_data; in spi_imx_probe()
1644 if (!device_property_read_u32(&pdev->dev, "num-cs", &val)) in spi_imx_probe()
1645 master->num_chipselect = val; in spi_imx_probe()
1647 master->num_chipselect = 3; in spi_imx_probe()
1649 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; in spi_imx_probe()
1650 spi_imx->bitbang.txrx_bufs = spi_imx_transfer; in spi_imx_probe()
1651 spi_imx->bitbang.master->setup = spi_imx_setup; in spi_imx_probe()
1652 spi_imx->bitbang.master->cleanup = spi_imx_cleanup; in spi_imx_probe()
1653 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; in spi_imx_probe()
1654 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; in spi_imx_probe()
1655 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort; in spi_imx_probe()
1656 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ in spi_imx_probe()
1660 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; in spi_imx_probe()
1662 spi_imx->spi_drctl = spi_drctl; in spi_imx_probe()
1664 init_completion(&spi_imx->xfer_done); in spi_imx_probe()
1667 spi_imx->base = devm_ioremap_resource(&pdev->dev, res); in spi_imx_probe()
1668 if (IS_ERR(spi_imx->base)) { in spi_imx_probe()
1669 ret = PTR_ERR(spi_imx->base); in spi_imx_probe()
1672 spi_imx->base_phys = res->start; in spi_imx_probe()
1680 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, in spi_imx_probe()
1681 dev_name(&pdev->dev), spi_imx); in spi_imx_probe()
1683 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); in spi_imx_probe()
1687 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in spi_imx_probe()
1688 if (IS_ERR(spi_imx->clk_ipg)) { in spi_imx_probe()
1689 ret = PTR_ERR(spi_imx->clk_ipg); in spi_imx_probe()
1693 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); in spi_imx_probe()
1694 if (IS_ERR(spi_imx->clk_per)) { in spi_imx_probe()
1695 ret = PTR_ERR(spi_imx->clk_per); in spi_imx_probe()
1699 ret = clk_prepare_enable(spi_imx->clk_per); in spi_imx_probe()
1703 ret = clk_prepare_enable(spi_imx->clk_ipg); in spi_imx_probe()
1707 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT); in spi_imx_probe()
1708 pm_runtime_use_autosuspend(spi_imx->dev); in spi_imx_probe()
1709 pm_runtime_get_noresume(spi_imx->dev); in spi_imx_probe()
1710 pm_runtime_set_active(spi_imx->dev); in spi_imx_probe()
1711 pm_runtime_enable(spi_imx->dev); in spi_imx_probe()
1713 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); in spi_imx_probe()
1718 if (spi_imx->devtype_data->has_dmamode) { in spi_imx_probe()
1719 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); in spi_imx_probe()
1720 if (ret == -EPROBE_DEFER) in spi_imx_probe()
1724 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n", in spi_imx_probe()
1728 spi_imx->devtype_data->reset(spi_imx); in spi_imx_probe()
1730 spi_imx->devtype_data->intctrl(spi_imx, 0); in spi_imx_probe()
1732 master->dev.of_node = pdev->dev.of_node; in spi_imx_probe()
1733 ret = spi_bitbang_start(&spi_imx->bitbang); in spi_imx_probe()
1735 dev_err_probe(&pdev->dev, ret, "bitbang start failed\n"); in spi_imx_probe()
1739 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_probe()
1740 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_probe()
1745 if (spi_imx->devtype_data->has_dmamode) in spi_imx_probe()
1748 pm_runtime_dont_use_autosuspend(spi_imx->dev); in spi_imx_probe()
1749 pm_runtime_set_suspended(&pdev->dev); in spi_imx_probe()
1750 pm_runtime_disable(spi_imx->dev); in spi_imx_probe()
1752 clk_disable_unprepare(spi_imx->clk_ipg); in spi_imx_probe()
1754 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_probe()
1767 spi_bitbang_stop(&spi_imx->bitbang); in spi_imx_remove()
1769 ret = pm_runtime_get_sync(spi_imx->dev); in spi_imx_remove()
1771 pm_runtime_put_noidle(spi_imx->dev); in spi_imx_remove()
1772 dev_err(spi_imx->dev, "failed to enable clock\n"); in spi_imx_remove()
1776 writel(0, spi_imx->base + MXC_CSPICTRL); in spi_imx_remove()
1778 pm_runtime_dont_use_autosuspend(spi_imx->dev); in spi_imx_remove()
1779 pm_runtime_put_sync(spi_imx->dev); in spi_imx_remove()
1780 pm_runtime_disable(spi_imx->dev); in spi_imx_remove()
1796 ret = clk_prepare_enable(spi_imx->clk_per); in spi_imx_runtime_resume()
1800 ret = clk_prepare_enable(spi_imx->clk_ipg); in spi_imx_runtime_resume()
1802 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_runtime_resume()
1816 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_runtime_suspend()
1817 clk_disable_unprepare(spi_imx->clk_ipg); in spi_imx_runtime_suspend()