Lines Matching +full:spi +full:- +full:controller
1 // SPDX-License-Identifier: GPL-2.0
3 // STMicroelectronics STM32 SPI Controller driver (master mode only)
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
19 #include <linux/spi/spi.h>
23 /* STM32F4 SPI registers */
72 /* STM32F4 SPI Baud Rate min/max divisor */
76 /* STM32H7 SPI registers */
153 /* STM32H7 SPI Master Baud Rate min/max divisor */
157 /* STM32H7 SPI Communication mode */
163 /* SPI Communication type */
179 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
191 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
192 * @en: enable register and SPI enable bit
193 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
194 * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
199 * @rx: SPI RX data register
200 * @tx: SPI TX data register
217 * struct stm32_spi_cfg - stm32 compatible configuration data
221 * @disable: routine to disable controller
222 * @config: routine to configure controller as SPI Master
235 * @irq_handler_event: Interrupt handler for SPI controller events
236 * @irq_handler_thread: thread of interrupt handler for SPI controller
244 int (*get_fifo_size)(struct stm32_spi *spi);
245 int (*get_bpw_mask)(struct stm32_spi *spi);
246 void (*disable)(struct stm32_spi *spi);
247 int (*config)(struct stm32_spi *spi);
248 void (*set_bpw)(struct stm32_spi *spi);
249 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
250 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
251 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
252 void (*transfer_one_dma_start)(struct stm32_spi *spi);
255 int (*transfer_one_irq)(struct stm32_spi *spi);
264 * struct stm32_spi - private data of the SPI controller
265 * @dev: driver model representation of the controller
266 * @master: controller master interface
269 * @clk: hw kernel clock feeding the SPI clock generator
270 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
271 * @rst: SPI controller reset line
273 * @irq: SPI controller interrupt line
275 * @cur_midi: master inter-data idleness in ns
277 * @cur_bpw: number of bits in a single SPI data frame
279 * @cur_comm: SPI communication mode
288 * @phys_addr: SPI registers physical base address
335 /* SPI data transfer is enabled but spi_ker_ck is idle.
353 static inline void stm32_spi_set_bits(struct stm32_spi *spi, in stm32_spi_set_bits() argument
356 writel_relaxed(readl_relaxed(spi->base + offset) | bits, in stm32_spi_set_bits()
357 spi->base + offset); in stm32_spi_set_bits()
360 static inline void stm32_spi_clr_bits(struct stm32_spi *spi, in stm32_spi_clr_bits() argument
363 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, in stm32_spi_clr_bits()
364 spi->base + offset); in stm32_spi_clr_bits()
368 * stm32h7_spi_get_fifo_size - Return fifo size
369 * @spi: pointer to the spi controller data structure
371 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi) in stm32h7_spi_get_fifo_size() argument
376 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
378 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_get_fifo_size()
380 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) in stm32h7_spi_get_fifo_size()
381 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_get_fifo_size()
383 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_get_fifo_size()
385 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
387 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); in stm32h7_spi_get_fifo_size()
393 * stm32f4_spi_get_bpw_mask - Return bits per word mask
394 * @spi: pointer to the spi controller data structure
396 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi) in stm32f4_spi_get_bpw_mask() argument
398 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); in stm32f4_spi_get_bpw_mask()
403 * stm32h7_spi_get_bpw_mask - Return bits per word mask
404 * @spi: pointer to the spi controller data structure
406 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi) in stm32h7_spi_get_bpw_mask() argument
411 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
415 * maximum data size of periperal instances is limited to 16-bit in stm32h7_spi_get_bpw_mask()
417 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE); in stm32h7_spi_get_bpw_mask()
419 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_get_bpw_mask()
424 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
426 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); in stm32h7_spi_get_bpw_mask()
432 * stm32_spi_prepare_mbr - Determine baud rate divisor value
433 * @spi: pointer to the spi controller data structure
438 * Return baud rate divisor value in case of success or -EINVAL
440 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz, in stm32_spi_prepare_mbr() argument
445 /* Ensure spi->clk_rate is even */ in stm32_spi_prepare_mbr()
446 div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz); in stm32_spi_prepare_mbr()
449 * SPI framework set xfer->speed_hz to master->max_speed_hz if in stm32_spi_prepare_mbr()
450 * xfer->speed_hz is greater than master->max_speed_hz, and it returns in stm32_spi_prepare_mbr()
451 * an error when xfer->speed_hz is lower than master->min_speed_hz, so in stm32_spi_prepare_mbr()
456 return -EINVAL; in stm32_spi_prepare_mbr()
459 if (div & (div - 1)) in stm32_spi_prepare_mbr()
462 mbrdiv = fls(div) - 1; in stm32_spi_prepare_mbr()
464 spi->cur_speed = spi->clk_rate / (1 << mbrdiv); in stm32_spi_prepare_mbr()
466 return mbrdiv - 1; in stm32_spi_prepare_mbr()
470 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
471 * @spi: pointer to the spi controller data structure
474 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len) in stm32h7_spi_prepare_fthlv() argument
479 half_fifo = (spi->fifo_size / 2); in stm32h7_spi_prepare_fthlv()
487 if (spi->cur_bpw <= 8) in stm32h7_spi_prepare_fthlv()
489 else if (spi->cur_bpw <= 16) in stm32h7_spi_prepare_fthlv()
495 if (spi->cur_bpw > 8) in stm32h7_spi_prepare_fthlv()
498 fthlv += (fthlv % 4) ? (4 - (fthlv % 4)) : 0; in stm32h7_spi_prepare_fthlv()
507 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
508 * @spi: pointer to the spi controller data structure
513 static void stm32f4_spi_write_tx(struct stm32_spi *spi) in stm32f4_spi_write_tx() argument
515 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & in stm32f4_spi_write_tx()
517 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32f4_spi_write_tx()
519 if (spi->cur_bpw == 16) { in stm32f4_spi_write_tx()
520 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
522 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR); in stm32f4_spi_write_tx()
523 spi->tx_len -= sizeof(u16); in stm32f4_spi_write_tx()
525 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
527 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR); in stm32f4_spi_write_tx()
528 spi->tx_len -= sizeof(u8); in stm32f4_spi_write_tx()
532 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32f4_spi_write_tx()
536 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
537 * @spi: pointer to the spi controller data structure
542 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi) in stm32h7_spi_write_txfifo() argument
544 while ((spi->tx_len > 0) && in stm32h7_spi_write_txfifo()
545 (readl_relaxed(spi->base + STM32H7_SPI_SR) & in stm32h7_spi_write_txfifo()
547 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32h7_spi_write_txfifo()
549 if (spi->tx_len >= sizeof(u32)) { in stm32h7_spi_write_txfifo()
550 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
552 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
553 spi->tx_len -= sizeof(u32); in stm32h7_spi_write_txfifo()
554 } else if (spi->tx_len >= sizeof(u16)) { in stm32h7_spi_write_txfifo()
555 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
557 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
558 spi->tx_len -= sizeof(u16); in stm32h7_spi_write_txfifo()
560 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
562 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
563 spi->tx_len -= sizeof(u8); in stm32h7_spi_write_txfifo()
567 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32h7_spi_write_txfifo()
571 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
572 * @spi: pointer to the spi controller data structure
577 static void stm32f4_spi_read_rx(struct stm32_spi *spi) in stm32f4_spi_read_rx() argument
579 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & in stm32f4_spi_read_rx()
581 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32f4_spi_read_rx()
583 if (spi->cur_bpw == 16) { in stm32f4_spi_read_rx()
584 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
586 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_read_rx()
587 spi->rx_len -= sizeof(u16); in stm32f4_spi_read_rx()
589 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
591 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_read_rx()
592 spi->rx_len -= sizeof(u8); in stm32f4_spi_read_rx()
596 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len); in stm32f4_spi_read_rx()
600 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
601 * @spi: pointer to the spi controller data structure
607 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush) in stm32h7_spi_read_rxfifo() argument
609 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
613 while ((spi->rx_len > 0) && in stm32h7_spi_read_rxfifo()
616 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32h7_spi_read_rxfifo()
618 if ((spi->rx_len >= sizeof(u32)) || in stm32h7_spi_read_rxfifo()
620 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
622 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
623 spi->rx_len -= sizeof(u32); in stm32h7_spi_read_rxfifo()
624 } else if ((spi->rx_len >= sizeof(u16)) || in stm32h7_spi_read_rxfifo()
625 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) { in stm32h7_spi_read_rxfifo()
626 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
628 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
629 spi->rx_len -= sizeof(u16); in stm32h7_spi_read_rxfifo()
631 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
633 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
634 spi->rx_len -= sizeof(u8); in stm32h7_spi_read_rxfifo()
637 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
642 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__, in stm32h7_spi_read_rxfifo()
643 flush ? "(flush)" : "", spi->rx_len); in stm32h7_spi_read_rxfifo()
647 * stm32_spi_enable - Enable SPI controller
648 * @spi: pointer to the spi controller data structure
650 static void stm32_spi_enable(struct stm32_spi *spi) in stm32_spi_enable() argument
652 dev_dbg(spi->dev, "enable controller\n"); in stm32_spi_enable()
654 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, in stm32_spi_enable()
655 spi->cfg->regs->en.mask); in stm32_spi_enable()
659 * stm32f4_spi_disable - Disable SPI controller
660 * @spi: pointer to the spi controller data structure
662 static void stm32f4_spi_disable(struct stm32_spi *spi) in stm32f4_spi_disable() argument
667 dev_dbg(spi->dev, "disable controller\n"); in stm32f4_spi_disable()
669 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_disable()
671 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) & in stm32f4_spi_disable()
673 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_disable()
678 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE | in stm32f4_spi_disable()
683 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR, in stm32f4_spi_disable()
686 dev_warn(spi->dev, "disabling condition timeout\n"); in stm32f4_spi_disable()
689 if (spi->cur_usedma && spi->dma_tx) in stm32f4_spi_disable()
690 dmaengine_terminate_all(spi->dma_tx); in stm32f4_spi_disable()
691 if (spi->cur_usedma && spi->dma_rx) in stm32f4_spi_disable()
692 dmaengine_terminate_all(spi->dma_rx); in stm32f4_spi_disable()
694 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE); in stm32f4_spi_disable()
696 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN | in stm32f4_spi_disable()
700 readl_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_disable()
701 readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_disable()
703 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_disable()
707 * stm32h7_spi_disable - Disable SPI controller
708 * @spi: pointer to the spi controller data structure
710 * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
712 * RX-Fifo.
718 static void stm32h7_spi_disable(struct stm32_spi *spi) in stm32h7_spi_disable() argument
723 dev_dbg(spi->dev, "disable controller\n"); in stm32h7_spi_disable()
725 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_disable()
727 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
730 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
735 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR, in stm32h7_spi_disable()
740 spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
742 spi->base + STM32H7_SPI_SR, in stm32h7_spi_disable()
745 dev_warn(spi->dev, in stm32h7_spi_disable()
750 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0)) in stm32h7_spi_disable()
751 stm32h7_spi_read_rxfifo(spi, true); in stm32h7_spi_disable()
753 if (spi->cur_usedma && spi->dma_tx) in stm32h7_spi_disable()
754 dmaengine_terminate_all(spi->dma_tx); in stm32h7_spi_disable()
755 if (spi->cur_usedma && spi->dma_rx) in stm32h7_spi_disable()
756 dmaengine_terminate_all(spi->dma_rx); in stm32h7_spi_disable()
758 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_disable()
760 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN | in stm32h7_spi_disable()
764 writel_relaxed(0, spi->base + STM32H7_SPI_IER); in stm32h7_spi_disable()
765 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_disable()
767 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
771 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
772 * @master: controller master interface
773 * @spi_dev: pointer to the spi device
774 * @transfer: pointer to spi transfer
784 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_can_dma() local
786 if (spi->cfg->has_fifo) in stm32_spi_can_dma()
787 dma_size = spi->fifo_size; in stm32_spi_can_dma()
791 dev_dbg(spi->dev, "%s: %s\n", __func__, in stm32_spi_can_dma()
792 (transfer->len > dma_size) ? "true" : "false"); in stm32_spi_can_dma()
794 return (transfer->len > dma_size); in stm32_spi_can_dma()
798 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
800 * @dev_id: SPI controller master interface
805 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32f4_spi_irq_event() local
809 spin_lock(&spi->lock); in stm32f4_spi_irq_event()
811 sr = readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_irq_event()
818 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX || in stm32f4_spi_irq_event()
819 spi->cur_comm == SPI_3WIRE_TX)) { in stm32f4_spi_irq_event()
825 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX || in stm32f4_spi_irq_event()
826 spi->cur_comm == SPI_SIMPLEX_RX || in stm32f4_spi_irq_event()
827 spi->cur_comm == SPI_3WIRE_RX)) { in stm32f4_spi_irq_event()
834 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr); in stm32f4_spi_irq_event()
835 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
840 dev_warn(spi->dev, "Overrun: received value discarded\n"); in stm32f4_spi_irq_event()
843 readl_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_irq_event()
844 readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_irq_event()
856 if (spi->tx_buf) in stm32f4_spi_irq_event()
857 stm32f4_spi_write_tx(spi); in stm32f4_spi_irq_event()
858 if (spi->tx_len == 0) in stm32f4_spi_irq_event()
863 stm32f4_spi_read_rx(spi); in stm32f4_spi_irq_event()
864 if (spi->rx_len == 0) in stm32f4_spi_irq_event()
866 else if (spi->tx_buf)/* Load data for discontinuous mode */ in stm32f4_spi_irq_event()
867 stm32f4_spi_write_tx(spi); in stm32f4_spi_irq_event()
873 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, in stm32f4_spi_irq_event()
877 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
881 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
886 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
888 * @dev_id: SPI controller master interface
893 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32f4_spi_irq_thread() local
896 stm32f4_spi_disable(spi); in stm32f4_spi_irq_thread()
902 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
904 * @dev_id: SPI controller master interface
909 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32h7_spi_irq_thread() local
914 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_irq_thread()
916 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_irq_thread()
917 ier = readl_relaxed(spi->base + STM32H7_SPI_IER); in stm32h7_spi_irq_thread()
927 * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP in stm32h7_spi_irq_thread()
928 * are set. So in case of Full-Duplex, need to poll TXP and RXP event. in stm32h7_spi_irq_thread()
930 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma) in stm32h7_spi_irq_thread()
934 dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", in stm32h7_spi_irq_thread()
936 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
945 dev_dbg_ratelimited(spi->dev, "Communication suspended\n"); in stm32h7_spi_irq_thread()
946 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
947 stm32h7_spi_read_rxfifo(spi, false); in stm32h7_spi_irq_thread()
952 if (spi->cur_usedma) in stm32h7_spi_irq_thread()
957 dev_warn(spi->dev, "Mode fault: transfer aborted\n"); in stm32h7_spi_irq_thread()
962 dev_err(spi->dev, "Overrun: RX data lost\n"); in stm32h7_spi_irq_thread()
967 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
968 stm32h7_spi_read_rxfifo(spi, true); in stm32h7_spi_irq_thread()
973 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) in stm32h7_spi_irq_thread()
974 stm32h7_spi_write_txfifo(spi); in stm32h7_spi_irq_thread()
977 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
978 stm32h7_spi_read_rxfifo(spi, false); in stm32h7_spi_irq_thread()
980 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_irq_thread()
982 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
985 stm32h7_spi_disable(spi); in stm32h7_spi_irq_thread()
993 * stm32_spi_prepare_msg - set up the controller to transfer a single message
994 * @master: controller master interface
995 * @msg: pointer to spi message
1000 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_prepare_msg() local
1001 struct spi_device *spi_dev = msg->spi; in stm32_spi_prepare_msg()
1002 struct device_node *np = spi_dev->dev.of_node; in stm32_spi_prepare_msg()
1006 /* SPI slave device may need time between data frames */ in stm32_spi_prepare_msg()
1007 spi->cur_midi = 0; in stm32_spi_prepare_msg()
1008 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) in stm32_spi_prepare_msg()
1009 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); in stm32_spi_prepare_msg()
1011 if (spi_dev->mode & SPI_CPOL) in stm32_spi_prepare_msg()
1012 setb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
1014 clrb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
1016 if (spi_dev->mode & SPI_CPHA) in stm32_spi_prepare_msg()
1017 setb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1019 clrb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1021 if (spi_dev->mode & SPI_LSB_FIRST) in stm32_spi_prepare_msg()
1022 setb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
1024 clrb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
1026 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", in stm32_spi_prepare_msg()
1027 spi_dev->mode & SPI_CPOL, in stm32_spi_prepare_msg()
1028 spi_dev->mode & SPI_CPHA, in stm32_spi_prepare_msg()
1029 spi_dev->mode & SPI_LSB_FIRST, in stm32_spi_prepare_msg()
1030 spi_dev->mode & SPI_CS_HIGH); in stm32_spi_prepare_msg()
1032 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_prepare_msg()
1037 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & in stm32_spi_prepare_msg()
1039 spi->base + spi->cfg->regs->cpol.reg); in stm32_spi_prepare_msg()
1041 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_prepare_msg()
1047 * stm32f4_spi_dma_tx_cb - dma callback
1048 * @data: pointer to the spi controller data structure
1054 struct stm32_spi *spi = data; in stm32f4_spi_dma_tx_cb() local
1056 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32f4_spi_dma_tx_cb()
1057 spi_finalize_current_transfer(spi->master); in stm32f4_spi_dma_tx_cb()
1058 stm32f4_spi_disable(spi); in stm32f4_spi_dma_tx_cb()
1063 * stm32f4_spi_dma_rx_cb - dma callback
1064 * @data: pointer to the spi controller data structure
1070 struct stm32_spi *spi = data; in stm32f4_spi_dma_rx_cb() local
1072 spi_finalize_current_transfer(spi->master); in stm32f4_spi_dma_rx_cb()
1073 stm32f4_spi_disable(spi); in stm32f4_spi_dma_rx_cb()
1077 * stm32h7_spi_dma_cb - dma callback
1078 * @data: pointer to the spi controller data structure
1085 struct stm32_spi *spi = data; in stm32h7_spi_dma_cb() local
1089 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_dma_cb()
1091 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_dma_cb()
1093 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_dma_cb()
1096 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr); in stm32h7_spi_dma_cb()
1102 * stm32_spi_dma_config - configure dma slave channel depending on current
1104 * @spi: pointer to the spi controller data structure
1108 static void stm32_spi_dma_config(struct stm32_spi *spi, in stm32_spi_dma_config() argument
1115 if (spi->cur_bpw <= 8) in stm32_spi_dma_config()
1117 else if (spi->cur_bpw <= 16) in stm32_spi_dma_config()
1122 if (spi->cfg->has_fifo) { in stm32_spi_dma_config()
1124 if (spi->cur_fthlv == 2) in stm32_spi_dma_config()
1127 maxburst = spi->cur_fthlv; in stm32_spi_dma_config()
1133 dma_conf->direction = dir; in stm32_spi_dma_config()
1134 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */ in stm32_spi_dma_config()
1135 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; in stm32_spi_dma_config()
1136 dma_conf->src_addr_width = buswidth; in stm32_spi_dma_config()
1137 dma_conf->src_maxburst = maxburst; in stm32_spi_dma_config()
1139 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1141 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */ in stm32_spi_dma_config()
1142 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; in stm32_spi_dma_config()
1143 dma_conf->dst_addr_width = buswidth; in stm32_spi_dma_config()
1144 dma_conf->dst_maxburst = maxburst; in stm32_spi_dma_config()
1146 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1152 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
1154 * @spi: pointer to the spi controller data structure
1159 static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) in stm32f4_spi_transfer_one_irq() argument
1165 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32f4_spi_transfer_one_irq()
1167 } else if (spi->cur_comm == SPI_FULL_DUPLEX || in stm32f4_spi_transfer_one_irq()
1168 spi->cur_comm == SPI_SIMPLEX_RX || in stm32f4_spi_transfer_one_irq()
1169 spi->cur_comm == SPI_3WIRE_RX) { in stm32f4_spi_transfer_one_irq()
1170 /* In transmit-only mode, the OVR flag is set in the SR register in stm32f4_spi_transfer_one_irq()
1176 return -EINVAL; in stm32f4_spi_transfer_one_irq()
1179 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_transfer_one_irq()
1181 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2); in stm32f4_spi_transfer_one_irq()
1183 stm32_spi_enable(spi); in stm32f4_spi_transfer_one_irq()
1186 if (spi->tx_buf) in stm32f4_spi_transfer_one_irq()
1187 stm32f4_spi_write_tx(spi); in stm32f4_spi_transfer_one_irq()
1189 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_transfer_one_irq()
1195 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1197 * @spi: pointer to the spi controller data structure
1202 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi) in stm32h7_spi_transfer_one_irq() argument
1208 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ in stm32h7_spi_transfer_one_irq()
1210 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ in stm32h7_spi_transfer_one_irq()
1212 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ in stm32h7_spi_transfer_one_irq()
1219 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1221 stm32_spi_enable(spi); in stm32h7_spi_transfer_one_irq()
1224 if (spi->tx_buf) in stm32h7_spi_transfer_one_irq()
1225 stm32h7_spi_write_txfifo(spi); in stm32h7_spi_transfer_one_irq()
1227 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); in stm32h7_spi_transfer_one_irq()
1229 writel_relaxed(ier, spi->base + STM32H7_SPI_IER); in stm32h7_spi_transfer_one_irq()
1231 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1237 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1239 * @spi: pointer to the spi controller data structure
1241 static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi) in stm32f4_spi_transfer_one_dma_start() argument
1244 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX || in stm32f4_spi_transfer_one_dma_start()
1245 spi->cur_comm == SPI_FULL_DUPLEX) { in stm32f4_spi_transfer_one_dma_start()
1247 * In transmit-only mode, the OVR flag is set in the SR register in stm32f4_spi_transfer_one_dma_start()
1251 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE); in stm32f4_spi_transfer_one_dma_start()
1254 stm32_spi_enable(spi); in stm32f4_spi_transfer_one_dma_start()
1258 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1260 * @spi: pointer to the spi controller data structure
1262 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi) in stm32h7_spi_transfer_one_dma_start() argument
1265 stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE | in stm32h7_spi_transfer_one_dma_start()
1270 stm32_spi_enable(spi); in stm32h7_spi_transfer_one_dma_start()
1272 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); in stm32h7_spi_transfer_one_dma_start()
1276 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1277 * @spi: pointer to the spi controller data structure
1283 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, in stm32_spi_transfer_one_dma() argument
1290 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1293 if (spi->rx_buf && spi->dma_rx) { in stm32_spi_transfer_one_dma()
1294 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); in stm32_spi_transfer_one_dma()
1295 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); in stm32_spi_transfer_one_dma()
1298 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1299 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1302 spi->dma_rx, xfer->rx_sg.sgl, in stm32_spi_transfer_one_dma()
1303 xfer->rx_sg.nents, in stm32_spi_transfer_one_dma()
1309 if (spi->tx_buf && spi->dma_tx) { in stm32_spi_transfer_one_dma()
1310 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV); in stm32_spi_transfer_one_dma()
1311 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); in stm32_spi_transfer_one_dma()
1314 spi->dma_tx, xfer->tx_sg.sgl, in stm32_spi_transfer_one_dma()
1315 xfer->tx_sg.nents, in stm32_spi_transfer_one_dma()
1320 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) || in stm32_spi_transfer_one_dma()
1321 (spi->rx_buf && spi->dma_rx && !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1324 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1328 rx_dma_desc->callback = spi->cfg->dma_rx_cb; in stm32_spi_transfer_one_dma()
1329 rx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1332 dev_err(spi->dev, "Rx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1336 dma_async_issue_pending(spi->dma_rx); in stm32_spi_transfer_one_dma()
1340 if (spi->cur_comm == SPI_SIMPLEX_TX || in stm32_spi_transfer_one_dma()
1341 spi->cur_comm == SPI_3WIRE_TX) { in stm32_spi_transfer_one_dma()
1342 tx_dma_desc->callback = spi->cfg->dma_tx_cb; in stm32_spi_transfer_one_dma()
1343 tx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1347 dev_err(spi->dev, "Tx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1351 dma_async_issue_pending(spi->dma_tx); in stm32_spi_transfer_one_dma()
1354 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, in stm32_spi_transfer_one_dma()
1355 spi->cfg->regs->dma_tx_en.mask); in stm32_spi_transfer_one_dma()
1358 spi->cfg->transfer_one_dma_start(spi); in stm32_spi_transfer_one_dma()
1360 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1365 if (spi->dma_rx) in stm32_spi_transfer_one_dma()
1366 dmaengine_terminate_all(spi->dma_rx); in stm32_spi_transfer_one_dma()
1369 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1370 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1372 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1374 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); in stm32_spi_transfer_one_dma()
1376 spi->cur_usedma = false; in stm32_spi_transfer_one_dma()
1377 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one_dma()
1381 * stm32f4_spi_set_bpw - Configure bits per word
1382 * @spi: pointer to the spi controller data structure
1384 static void stm32f4_spi_set_bpw(struct stm32_spi *spi) in stm32f4_spi_set_bpw() argument
1386 if (spi->cur_bpw == 16) in stm32f4_spi_set_bpw()
1387 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); in stm32f4_spi_set_bpw()
1389 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); in stm32f4_spi_set_bpw()
1393 * stm32h7_spi_set_bpw - configure bits per word
1394 * @spi: pointer to the spi controller data structure
1396 static void stm32h7_spi_set_bpw(struct stm32_spi *spi) in stm32h7_spi_set_bpw() argument
1401 bpw = spi->cur_bpw - 1; in stm32h7_spi_set_bpw()
1407 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen); in stm32h7_spi_set_bpw()
1408 fthlv = spi->cur_fthlv - 1; in stm32h7_spi_set_bpw()
1415 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & in stm32h7_spi_set_bpw()
1417 spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_set_bpw()
1421 * stm32_spi_set_mbr - Configure baud rate divisor in master mode
1422 * @spi: pointer to the spi controller data structure
1425 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv) in stm32_spi_set_mbr() argument
1429 clrb |= spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1430 setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) & in stm32_spi_set_mbr()
1431 spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1433 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & in stm32_spi_set_mbr()
1435 spi->base + spi->cfg->regs->br.reg); in stm32_spi_set_mbr()
1439 * stm32_spi_communication_type - return transfer communication type
1440 * @spi_dev: pointer to the spi device
1441 * @transfer: pointer to spi transfer
1448 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */ in stm32_spi_communication_type()
1450 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL in stm32_spi_communication_type()
1451 * is forbidden and unvalidated by SPI subsystem so depending in stm32_spi_communication_type()
1455 if (!transfer->tx_buf) in stm32_spi_communication_type()
1460 if (!transfer->tx_buf) in stm32_spi_communication_type()
1462 else if (!transfer->rx_buf) in stm32_spi_communication_type()
1470 * stm32f4_spi_set_mode - configure communication mode
1471 * @spi: pointer to the spi controller data structure
1474 static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) in stm32f4_spi_set_mode() argument
1477 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, in stm32f4_spi_set_mode()
1482 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, in stm32f4_spi_set_mode()
1486 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, in stm32f4_spi_set_mode()
1488 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, in stm32f4_spi_set_mode()
1491 return -EINVAL; in stm32f4_spi_set_mode()
1498 * stm32h7_spi_set_mode - configure communication mode
1499 * @spi: pointer to the spi controller data structure
1502 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) in stm32h7_spi_set_mode() argument
1509 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); in stm32h7_spi_set_mode()
1512 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); in stm32h7_spi_set_mode()
1526 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_set_mode()
1528 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_set_mode()
1534 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1536 * @spi: pointer to the spi controller data structure
1539 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len) in stm32h7_spi_data_idleness() argument
1544 if ((len > 1) && (spi->cur_midi > 0)) { in stm32h7_spi_data_idleness()
1545 u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed); in stm32h7_spi_data_idleness()
1546 u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns), in stm32h7_spi_data_idleness()
1550 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", in stm32h7_spi_data_idleness()
1556 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_data_idleness()
1558 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_data_idleness()
1562 * stm32h7_spi_number_of_data - configure number of data at current transfer
1563 * @spi: pointer to the spi controller data structure
1566 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words) in stm32h7_spi_number_of_data() argument
1574 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) & in stm32h7_spi_number_of_data()
1576 spi->base + STM32H7_SPI_CR2); in stm32h7_spi_number_of_data()
1578 return -EMSGSIZE; in stm32h7_spi_number_of_data()
1585 * stm32_spi_transfer_one_setup - common setup to transfer a single
1588 * @spi: pointer to the spi controller data structure
1589 * @spi_dev: pointer to the spi device
1590 * @transfer: pointer to spi transfer
1592 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, in stm32_spi_transfer_one_setup() argument
1601 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1603 spi->cur_xferlen = transfer->len; in stm32_spi_transfer_one_setup()
1605 spi->cur_bpw = transfer->bits_per_word; in stm32_spi_transfer_one_setup()
1606 spi->cfg->set_bpw(spi); in stm32_spi_transfer_one_setup()
1608 /* Update spi->cur_speed with real clock speed */ in stm32_spi_transfer_one_setup()
1609 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz, in stm32_spi_transfer_one_setup()
1610 spi->cfg->baud_rate_div_min, in stm32_spi_transfer_one_setup()
1611 spi->cfg->baud_rate_div_max); in stm32_spi_transfer_one_setup()
1617 transfer->speed_hz = spi->cur_speed; in stm32_spi_transfer_one_setup()
1618 stm32_spi_set_mbr(spi, mbr); in stm32_spi_transfer_one_setup()
1621 ret = spi->cfg->set_mode(spi, comm_type); in stm32_spi_transfer_one_setup()
1625 spi->cur_comm = comm_type; in stm32_spi_transfer_one_setup()
1627 if (spi->cfg->set_data_idleness) in stm32_spi_transfer_one_setup()
1628 spi->cfg->set_data_idleness(spi, transfer->len); in stm32_spi_transfer_one_setup()
1630 if (spi->cur_bpw <= 8) in stm32_spi_transfer_one_setup()
1631 nb_words = transfer->len; in stm32_spi_transfer_one_setup()
1632 else if (spi->cur_bpw <= 16) in stm32_spi_transfer_one_setup()
1633 nb_words = DIV_ROUND_UP(transfer->len * 8, 16); in stm32_spi_transfer_one_setup()
1635 nb_words = DIV_ROUND_UP(transfer->len * 8, 32); in stm32_spi_transfer_one_setup()
1637 if (spi->cfg->set_number_of_data) { in stm32_spi_transfer_one_setup()
1638 ret = spi->cfg->set_number_of_data(spi, nb_words); in stm32_spi_transfer_one_setup()
1643 dev_dbg(spi->dev, "transfer communication mode set to %d\n", in stm32_spi_transfer_one_setup()
1644 spi->cur_comm); in stm32_spi_transfer_one_setup()
1645 dev_dbg(spi->dev, in stm32_spi_transfer_one_setup()
1646 "data frame of %d-bit, data packet of %d data frames\n", in stm32_spi_transfer_one_setup()
1647 spi->cur_bpw, spi->cur_fthlv); in stm32_spi_transfer_one_setup()
1648 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); in stm32_spi_transfer_one_setup()
1649 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", in stm32_spi_transfer_one_setup()
1650 spi->cur_xferlen, nb_words); in stm32_spi_transfer_one_setup()
1651 dev_dbg(spi->dev, "dma %s\n", in stm32_spi_transfer_one_setup()
1652 (spi->cur_usedma) ? "enabled" : "disabled"); in stm32_spi_transfer_one_setup()
1655 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1661 * stm32_spi_transfer_one - transfer a single spi_transfer
1662 * @master: controller master interface
1663 * @spi_dev: pointer to the spi device
1664 * @transfer: pointer to spi transfer
1673 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_transfer_one() local
1677 if (transfer->len == 0) in stm32_spi_transfer_one()
1680 spi->tx_buf = transfer->tx_buf; in stm32_spi_transfer_one()
1681 spi->rx_buf = transfer->rx_buf; in stm32_spi_transfer_one()
1682 spi->tx_len = spi->tx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1683 spi->rx_len = spi->rx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1685 spi->cur_usedma = (master->can_dma && in stm32_spi_transfer_one()
1686 master->can_dma(master, spi_dev, transfer)); in stm32_spi_transfer_one()
1688 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer); in stm32_spi_transfer_one()
1690 dev_err(spi->dev, "SPI transfer setup failed\n"); in stm32_spi_transfer_one()
1694 if (spi->cur_usedma) in stm32_spi_transfer_one()
1695 return stm32_spi_transfer_one_dma(spi, transfer); in stm32_spi_transfer_one()
1697 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one()
1701 * stm32_spi_unprepare_msg - relax the hardware
1702 * @master: controller master interface
1703 * @msg: pointer to the spi message
1708 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_unprepare_msg() local
1710 spi->cfg->disable(spi); in stm32_spi_unprepare_msg()
1716 * stm32f4_spi_config - Configure SPI controller as SPI master
1717 * @spi: pointer to the spi controller data structure
1719 static int stm32f4_spi_config(struct stm32_spi *spi) in stm32f4_spi_config() argument
1723 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_config()
1726 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR, in stm32f4_spi_config()
1730 * - SS input value high in stm32f4_spi_config()
1731 * - transmitter half duplex direction in stm32f4_spi_config()
1732 * - Set the master mode (default Motorola mode) in stm32f4_spi_config()
1733 * - Consider 1 master/n slaves configuration and in stm32f4_spi_config()
1736 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI | in stm32f4_spi_config()
1741 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_config()
1747 * stm32h7_spi_config - Configure SPI controller as SPI master
1748 * @spi: pointer to the spi controller data structure
1750 static int stm32h7_spi_config(struct stm32_spi *spi) in stm32h7_spi_config() argument
1754 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_config()
1757 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR, in stm32h7_spi_config()
1761 * - SS input value high in stm32h7_spi_config()
1762 * - transmitter half duplex direction in stm32h7_spi_config()
1763 * - automatic communication suspend when RX-Fifo is full in stm32h7_spi_config()
1765 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI | in stm32h7_spi_config()
1770 * - Set the master mode (default Motorola mode) in stm32h7_spi_config()
1771 * - Consider 1 master/n slaves configuration and in stm32h7_spi_config()
1773 * - keep control of all associated GPIOs in stm32h7_spi_config()
1775 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER | in stm32h7_spi_config()
1779 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_config()
1823 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1824 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1832 struct stm32_spi *spi; in stm32_spi_probe() local
1836 master = devm_spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi)); in stm32_spi_probe()
1838 dev_err(&pdev->dev, "spi master allocation failed\n"); in stm32_spi_probe()
1839 return -ENOMEM; in stm32_spi_probe()
1843 spi = spi_master_get_devdata(master); in stm32_spi_probe()
1844 spi->dev = &pdev->dev; in stm32_spi_probe()
1845 spi->master = master; in stm32_spi_probe()
1846 spin_lock_init(&spi->lock); in stm32_spi_probe()
1848 spi->cfg = (const struct stm32_spi_cfg *) in stm32_spi_probe()
1849 of_match_device(pdev->dev.driver->of_match_table, in stm32_spi_probe()
1850 &pdev->dev)->data; in stm32_spi_probe()
1853 spi->base = devm_ioremap_resource(&pdev->dev, res); in stm32_spi_probe()
1854 if (IS_ERR(spi->base)) in stm32_spi_probe()
1855 return PTR_ERR(spi->base); in stm32_spi_probe()
1857 spi->phys_addr = (dma_addr_t)res->start; in stm32_spi_probe()
1859 spi->irq = platform_get_irq(pdev, 0); in stm32_spi_probe()
1860 if (spi->irq <= 0) in stm32_spi_probe()
1861 return dev_err_probe(&pdev->dev, spi->irq, in stm32_spi_probe()
1864 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, in stm32_spi_probe()
1865 spi->cfg->irq_handler_event, in stm32_spi_probe()
1866 spi->cfg->irq_handler_thread, in stm32_spi_probe()
1867 IRQF_ONESHOT, pdev->name, master); in stm32_spi_probe()
1869 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, in stm32_spi_probe()
1874 spi->clk = devm_clk_get(&pdev->dev, NULL); in stm32_spi_probe()
1875 if (IS_ERR(spi->clk)) { in stm32_spi_probe()
1876 ret = PTR_ERR(spi->clk); in stm32_spi_probe()
1877 dev_err(&pdev->dev, "clk get failed: %d\n", ret); in stm32_spi_probe()
1881 ret = clk_prepare_enable(spi->clk); in stm32_spi_probe()
1883 dev_err(&pdev->dev, "clk enable failed: %d\n", ret); in stm32_spi_probe()
1886 spi->clk_rate = clk_get_rate(spi->clk); in stm32_spi_probe()
1887 if (!spi->clk_rate) { in stm32_spi_probe()
1888 dev_err(&pdev->dev, "clk rate = 0\n"); in stm32_spi_probe()
1889 ret = -EINVAL; in stm32_spi_probe()
1893 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); in stm32_spi_probe()
1894 if (!IS_ERR(spi->rst)) { in stm32_spi_probe()
1895 reset_control_assert(spi->rst); in stm32_spi_probe()
1897 reset_control_deassert(spi->rst); in stm32_spi_probe()
1900 if (spi->cfg->has_fifo) in stm32_spi_probe()
1901 spi->fifo_size = spi->cfg->get_fifo_size(spi); in stm32_spi_probe()
1903 ret = spi->cfg->config(spi); in stm32_spi_probe()
1905 dev_err(&pdev->dev, "controller configuration failed: %d\n", in stm32_spi_probe()
1910 master->dev.of_node = pdev->dev.of_node; in stm32_spi_probe()
1911 master->auto_runtime_pm = true; in stm32_spi_probe()
1912 master->bus_num = pdev->id; in stm32_spi_probe()
1913 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | in stm32_spi_probe()
1915 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi); in stm32_spi_probe()
1916 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min; in stm32_spi_probe()
1917 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max; in stm32_spi_probe()
1918 master->use_gpio_descriptors = true; in stm32_spi_probe()
1919 master->prepare_message = stm32_spi_prepare_msg; in stm32_spi_probe()
1920 master->transfer_one = stm32_spi_transfer_one; in stm32_spi_probe()
1921 master->unprepare_message = stm32_spi_unprepare_msg; in stm32_spi_probe()
1922 master->flags = SPI_MASTER_MUST_TX; in stm32_spi_probe()
1924 spi->dma_tx = dma_request_chan(spi->dev, "tx"); in stm32_spi_probe()
1925 if (IS_ERR(spi->dma_tx)) { in stm32_spi_probe()
1926 ret = PTR_ERR(spi->dma_tx); in stm32_spi_probe()
1927 spi->dma_tx = NULL; in stm32_spi_probe()
1928 if (ret == -EPROBE_DEFER) in stm32_spi_probe()
1931 dev_warn(&pdev->dev, "failed to request tx dma channel\n"); in stm32_spi_probe()
1933 master->dma_tx = spi->dma_tx; in stm32_spi_probe()
1936 spi->dma_rx = dma_request_chan(spi->dev, "rx"); in stm32_spi_probe()
1937 if (IS_ERR(spi->dma_rx)) { in stm32_spi_probe()
1938 ret = PTR_ERR(spi->dma_rx); in stm32_spi_probe()
1939 spi->dma_rx = NULL; in stm32_spi_probe()
1940 if (ret == -EPROBE_DEFER) in stm32_spi_probe()
1943 dev_warn(&pdev->dev, "failed to request rx dma channel\n"); in stm32_spi_probe()
1945 master->dma_rx = spi->dma_rx; in stm32_spi_probe()
1948 if (spi->dma_tx || spi->dma_rx) in stm32_spi_probe()
1949 master->can_dma = stm32_spi_can_dma; in stm32_spi_probe()
1951 pm_runtime_set_active(&pdev->dev); in stm32_spi_probe()
1952 pm_runtime_get_noresume(&pdev->dev); in stm32_spi_probe()
1953 pm_runtime_enable(&pdev->dev); in stm32_spi_probe()
1957 dev_err(&pdev->dev, "spi master registration failed: %d\n", in stm32_spi_probe()
1962 if (!master->cs_gpiods) { in stm32_spi_probe()
1963 dev_err(&pdev->dev, "no CS gpios available\n"); in stm32_spi_probe()
1964 ret = -EINVAL; in stm32_spi_probe()
1968 dev_info(&pdev->dev, "driver initialized\n"); in stm32_spi_probe()
1973 pm_runtime_disable(&pdev->dev); in stm32_spi_probe()
1974 pm_runtime_put_noidle(&pdev->dev); in stm32_spi_probe()
1975 pm_runtime_set_suspended(&pdev->dev); in stm32_spi_probe()
1977 if (spi->dma_tx) in stm32_spi_probe()
1978 dma_release_channel(spi->dma_tx); in stm32_spi_probe()
1979 if (spi->dma_rx) in stm32_spi_probe()
1980 dma_release_channel(spi->dma_rx); in stm32_spi_probe()
1982 clk_disable_unprepare(spi->clk); in stm32_spi_probe()
1990 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_remove() local
1992 pm_runtime_get_sync(&pdev->dev); in stm32_spi_remove()
1995 spi->cfg->disable(spi); in stm32_spi_remove()
1997 pm_runtime_disable(&pdev->dev); in stm32_spi_remove()
1998 pm_runtime_put_noidle(&pdev->dev); in stm32_spi_remove()
1999 pm_runtime_set_suspended(&pdev->dev); in stm32_spi_remove()
2000 if (master->dma_tx) in stm32_spi_remove()
2001 dma_release_channel(master->dma_tx); in stm32_spi_remove()
2002 if (master->dma_rx) in stm32_spi_remove()
2003 dma_release_channel(master->dma_rx); in stm32_spi_remove()
2005 clk_disable_unprepare(spi->clk); in stm32_spi_remove()
2008 pinctrl_pm_select_sleep_state(&pdev->dev); in stm32_spi_remove()
2017 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_runtime_suspend() local
2019 clk_disable_unprepare(spi->clk); in stm32_spi_runtime_suspend()
2027 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_runtime_resume() local
2034 return clk_prepare_enable(spi->clk); in stm32_spi_runtime_resume()
2054 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_resume() local
2063 clk_disable_unprepare(spi->clk); in stm32_spi_resume()
2074 spi->cfg->config(spi); in stm32_spi_resume()
2102 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");