Lines Matching +full:11 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt driver - Port/Switch config area registers
65 * struct tb_cap_extended_short - Switch extended short capability
80 * struct tb_cap_extended_long - Switch extended long capability
98 * struct tb_cap_any - Structure capable of hold every capability
130 u32 unknown3:11;
136 bool clock:1; /* send pulse to transfer one bit */
156 u32 drom_offset; /* 32 bit register, but eeprom addresses are 16 bit */
195 #define ROUTER_CS_5_SLP BIT(0)
196 #define ROUTER_CS_5_WOP BIT(1)
197 #define ROUTER_CS_5_WOU BIT(2)
198 #define ROUTER_CS_5_C3S BIT(23)
199 #define ROUTER_CS_5_PTO BIT(24)
200 #define ROUTER_CS_5_UTO BIT(25)
201 #define ROUTER_CS_5_HCO BIT(26)
202 #define ROUTER_CS_5_CV BIT(31)
204 #define ROUTER_CS_6_SLPR BIT(0)
205 #define ROUTER_CS_6_TNS BIT(1)
206 #define ROUTER_CS_6_WOPS BIT(2)
207 #define ROUTER_CS_6_WOUS BIT(3)
208 #define ROUTER_CS_6_HCI BIT(18)
209 #define ROUTER_CS_6_CR BIT(25)
216 #define ROUTER_CS_26_ONS BIT(30)
217 #define ROUTER_CS_26_OV BIT(31)
221 #define TMU_RTR_CS_0_TD BIT(27)
222 #define TMU_RTR_CS_0_UCAP BIT(30)
255 u32 max_counters:11;
269 u32 max_in_hop_id:11;
270 u32 max_out_hop_id:11;
284 #define ADP_CS_4_LCK BIT(31)
291 #define TMU_ADP_CS_3_UDM BIT(29)
302 #define LANE_ADP_CS_1_LD BIT(14)
303 #define LANE_ADP_CS_1_LB BIT(15)
317 #define PORT_CS_1_WNR_WRITE BIT(24)
318 #define PORT_CS_1_NR BIT(25)
319 #define PORT_CS_1_RC BIT(26)
320 #define PORT_CS_1_PND BIT(31)
323 #define PORT_CS_18_BE BIT(8)
324 #define PORT_CS_18_TCM BIT(9)
325 #define PORT_CS_18_WOU4S BIT(18)
327 #define PORT_CS_19_PC BIT(3)
328 #define PORT_CS_19_PID BIT(4)
329 #define PORT_CS_19_WOC BIT(16)
330 #define PORT_CS_19_WOD BIT(17)
331 #define PORT_CS_19_WOU4 BIT(18)
337 #define ADP_DP_CS_0_AE BIT(30)
338 #define ADP_DP_CS_0_VE BIT(31)
340 #define ADP_DP_CS_1_AUX_RX_HOPID_MASK GENMASK(21, 11)
341 #define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT 11
343 #define ADP_DP_CS_2_HDP BIT(6)
345 #define ADP_DP_CS_3_HDPC BIT(9)
349 #define DP_STATUS_CTRL_CMHS BIT(25)
350 #define DP_STATUS_CTRL_UF BIT(26)
356 #define DP_COMMON_CAP_RATE_MASK GENMASK(11, 8)
367 #define DP_COMMON_CAP_DPRX_DONE BIT(31)
371 #define ADP_PCIE_CS_0_PE BIT(31)
375 #define ADP_USB3_CS_0_V BIT(30)
376 #define ADP_USB3_CS_0_PE BIT(31)
378 #define ADP_USB3_CS_1_CUBW_MASK GENMASK(11, 0)
381 #define ADP_USB3_CS_1_HCA BIT(31)
383 #define ADP_USB3_CS_2_AUBW_MASK GENMASK(11, 0)
386 #define ADP_USB3_CS_2_CMR BIT(31)
392 #define ADP_USB3_CS_4_ULV BIT(7)
400 u32 next_hop:11; /*
414 u32 counter:11; /* index into TB_CFG_COUNTERS on this port */
442 #define TB_LC_PORT_ATTR_BE BIT(12)
445 #define TB_LC_SX_CTRL_WOC BIT(1)
446 #define TB_LC_SX_CTRL_WOD BIT(2)
447 #define TB_LC_SX_CTRL_WOU4 BIT(5)
448 #define TB_LC_SX_CTRL_WOP BIT(6)
449 #define TB_LC_SX_CTRL_L1C BIT(16)
450 #define TB_LC_SX_CTRL_L1D BIT(17)
451 #define TB_LC_SX_CTRL_L2C BIT(20)
452 #define TB_LC_SX_CTRL_L2D BIT(21)
453 #define TB_LC_SX_CTRL_UPSTREAM BIT(30)
454 #define TB_LC_SX_CTRL_SLP BIT(31)