Lines Matching +full:rx +full:- +full:int +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0+
30 #include <linux/dma-mapping.h>
33 #include <linux/platform_data/serial-imx.h>
34 #include <linux/platform_data/dma-imx.h>
125 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
154 #define UTS_LOOP (1<<12) /* Loop tx and rx */
161 /* We've been assigned a range on the "Low-density serial ports" major */
174 #define DRIVER_NAME "IMX-uart"
202 unsigned int old_status;
203 unsigned int have_rtscts:1;
204 unsigned int have_rtsgpio:1;
205 unsigned int dte_mode:1;
206 unsigned int inverted_tx:1;
207 unsigned int inverted_rx:1;
212 struct mctrl_gpios *gpios; member
215 unsigned int ucr1;
216 unsigned int ucr2;
217 unsigned int ucr3;
218 unsigned int ucr4;
219 unsigned int ufcr;
222 unsigned int dma_is_enabled:1;
223 unsigned int dma_is_rxing:1;
224 unsigned int dma_is_txing:1;
229 unsigned int rx_periods;
231 unsigned int tx_bytes;
232 unsigned int dma_tx_nents;
233 unsigned int saved_reg[10];
242 unsigned int ucr1;
243 unsigned int ucr2;
244 unsigned int ucr3;
268 .name = "imx1-uart",
271 .name = "imx21-uart",
274 .name = "imx53-uart",
277 .name = "imx6q-uart",
286 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
287 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
288 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
289 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
298 sport->ucr1 = val; in imx_uart_writel()
301 sport->ucr2 = val; in imx_uart_writel()
304 sport->ucr3 = val; in imx_uart_writel()
307 sport->ucr4 = val; in imx_uart_writel()
310 sport->ufcr = val; in imx_uart_writel()
315 writel(val, sport->port.membase + offset); in imx_uart_writel()
322 return sport->ucr1; in imx_uart_readl()
331 if (!(sport->ucr2 & UCR2_SRST)) in imx_uart_readl()
332 sport->ucr2 = readl(sport->port.membase + offset); in imx_uart_readl()
333 return sport->ucr2; in imx_uart_readl()
336 return sport->ucr3; in imx_uart_readl()
339 return sport->ucr4; in imx_uart_readl()
342 return sport->ufcr; in imx_uart_readl()
345 return readl(sport->port.membase + offset); in imx_uart_readl()
351 return sport->devdata->uts_reg; in imx_uart_uts_reg()
354 static inline int imx_uart_is_imx1(struct imx_port *sport) in imx_uart_is_imx1()
356 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
359 static inline int imx_uart_is_imx21(struct imx_port *sport) in imx_uart_is_imx21()
361 return sport->devdata->devtype == IMX21_UART; in imx_uart_is_imx21()
364 static inline int imx_uart_is_imx53(struct imx_port *sport) in imx_uart_is_imx53()
366 return sport->devdata->devtype == IMX53_UART; in imx_uart_is_imx53()
369 static inline int imx_uart_is_imx6q(struct imx_port *sport) in imx_uart_is_imx6q()
371 return sport->devdata->devtype == IMX6Q_UART; in imx_uart_is_imx6q()
381 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
382 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
383 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
390 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
391 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
392 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
401 sport->port.mctrl |= TIOCM_RTS; in imx_uart_rts_active()
402 mctrl_gpio_set(sport->gpios, sport->port.mctrl); in imx_uart_rts_active()
411 sport->port.mctrl &= ~TIOCM_RTS; in imx_uart_rts_inactive()
412 mctrl_gpio_set(sport->gpios, sport->port.mctrl); in imx_uart_rts_inactive()
428 unsigned int ucr1, ucr2; in imx_uart_start_rx()
435 if (sport->dma_is_enabled) { in imx_uart_start_rx()
453 if (sport->tx_state == OFF) in imx_uart_stop_tx()
460 if (sport->dma_is_txing) in imx_uart_stop_tx()
477 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_stop_tx()
478 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
479 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
480 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
481 port->rs485.delay_rts_after_send); in imx_uart_stop_tx()
485 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
486 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
489 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
492 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_stop_tx()
500 sport->tx_state = OFF; in imx_uart_stop_tx()
503 sport->tx_state = OFF; in imx_uart_stop_tx()
517 if (sport->dma_is_enabled) { in imx_uart_stop_rx()
536 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
538 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
546 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_transmit_buffer()
548 if (sport->port.x_char) { in imx_uart_transmit_buffer()
550 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
551 sport->port.icount.tx++; in imx_uart_transmit_buffer()
552 sport->port.x_char = 0; in imx_uart_transmit_buffer()
556 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
557 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
561 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
564 * We've just sent a X-char Ensure the TX DMA is enabled in imx_uart_transmit_buffer()
569 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
582 /* send xmit->buf[xmit->tail] in imx_uart_transmit_buffer()
584 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); in imx_uart_transmit_buffer()
585 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in imx_uart_transmit_buffer()
586 sport->port.icount.tx++; in imx_uart_transmit_buffer()
590 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
593 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
599 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
600 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx_callback()
604 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
606 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
613 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); in imx_uart_dma_tx_callback()
614 sport->port.icount.tx += sport->tx_bytes; in imx_uart_dma_tx_callback()
616 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
618 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
621 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
623 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
625 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
631 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
637 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx()
638 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
640 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
641 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
643 int ret; in imx_uart_dma_tx()
645 if (sport->dma_is_txing) in imx_uart_dma_tx()
652 sport->tx_bytes = uart_circ_chars_pending(xmit); in imx_uart_dma_tx()
654 if (xmit->tail < xmit->head || xmit->head == 0) { in imx_uart_dma_tx()
655 sport->dma_tx_nents = 1; in imx_uart_dma_tx()
656 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); in imx_uart_dma_tx()
658 sport->dma_tx_nents = 2; in imx_uart_dma_tx()
660 sg_set_buf(sgl, xmit->buf + xmit->tail, in imx_uart_dma_tx()
661 UART_XMIT_SIZE - xmit->tail); in imx_uart_dma_tx()
662 sg_set_buf(sgl + 1, xmit->buf, xmit->head); in imx_uart_dma_tx()
665 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
673 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
678 desc->callback = imx_uart_dma_tx_callback; in imx_uart_dma_tx()
679 desc->callback_param = sport; in imx_uart_dma_tx()
689 sport->dma_is_txing = 1; in imx_uart_dma_tx()
701 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) in imx_uart_start_tx()
705 * We cannot simply do nothing here if sport->tx_state == SEND already in imx_uart_start_tx()
710 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_start_tx()
711 if (sport->tx_state == OFF) { in imx_uart_start_tx()
713 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in imx_uart_start_tx()
719 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) in imx_uart_start_tx()
722 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
723 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
724 port->rs485.delay_rts_before_send); in imx_uart_start_tx()
728 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
729 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
731 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
736 * tx-callback. in imx_uart_start_tx()
738 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
744 sport->tx_state = SEND; in imx_uart_start_tx()
747 sport->tx_state = SEND; in imx_uart_start_tx()
750 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
755 if (sport->dma_is_enabled) { in imx_uart_start_tx()
756 if (sport->port.x_char) { in imx_uart_start_tx()
757 /* We have X-char to send, so enable TX IRQ and in imx_uart_start_tx()
758 * disable TX DMA to let TX interrupt to send X-char */ in imx_uart_start_tx()
766 if (!uart_circ_empty(&port->state->xmit) && in imx_uart_start_tx()
773 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id) in __imx_uart_rtsint()
780 uart_handle_cts_change(&sport->port, !!usr1); in __imx_uart_rtsint()
781 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
786 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) in imx_uart_rtsint()
791 spin_lock(&sport->port.lock); in imx_uart_rtsint()
795 spin_unlock(&sport->port.lock); in imx_uart_rtsint()
800 static irqreturn_t imx_uart_txint(int irq, void *dev_id) in imx_uart_txint()
804 spin_lock(&sport->port.lock); in imx_uart_txint()
806 spin_unlock(&sport->port.lock); in imx_uart_txint()
810 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) in __imx_uart_rxint()
813 unsigned int rx, flg, ignored = 0; in __imx_uart_rxint() local
814 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
820 sport->port.icount.rx++; in __imx_uart_rxint()
822 rx = imx_uart_readl(sport, URXD0); in __imx_uart_rxint()
827 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
831 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) in __imx_uart_rxint()
834 if (unlikely(rx & URXD_ERR)) { in __imx_uart_rxint()
835 if (rx & URXD_BRK) in __imx_uart_rxint()
836 sport->port.icount.brk++; in __imx_uart_rxint()
837 else if (rx & URXD_PRERR) in __imx_uart_rxint()
838 sport->port.icount.parity++; in __imx_uart_rxint()
839 else if (rx & URXD_FRMERR) in __imx_uart_rxint()
840 sport->port.icount.frame++; in __imx_uart_rxint()
841 if (rx & URXD_OVRRUN) in __imx_uart_rxint()
842 sport->port.icount.overrun++; in __imx_uart_rxint()
844 if (rx & sport->port.ignore_status_mask) { in __imx_uart_rxint()
850 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
852 if (rx & URXD_BRK) in __imx_uart_rxint()
854 else if (rx & URXD_PRERR) in __imx_uart_rxint()
856 else if (rx & URXD_FRMERR) in __imx_uart_rxint()
858 if (rx & URXD_OVRRUN) in __imx_uart_rxint()
861 sport->port.sysrq = 0; in __imx_uart_rxint()
864 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
867 if (tty_insert_flip_char(port, rx, flg) == 0) in __imx_uart_rxint()
868 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
877 static irqreturn_t imx_uart_rxint(int irq, void *dev_id) in imx_uart_rxint()
882 spin_lock(&sport->port.lock); in imx_uart_rxint()
886 spin_unlock(&sport->port.lock); in imx_uart_rxint()
896 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) in imx_uart_get_hwmctrl()
898 unsigned int tmp = TIOCM_DSR; in imx_uart_get_hwmctrl()
909 if (sport->dte_mode) in imx_uart_get_hwmctrl()
921 unsigned int status, changed; in imx_uart_mctrl_check()
924 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
929 sport->old_status = status; in imx_uart_mctrl_check()
932 sport->port.icount.rng++; in imx_uart_mctrl_check()
934 sport->port.icount.dsr++; in imx_uart_mctrl_check()
936 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
938 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
940 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
943 static irqreturn_t imx_uart_int(int irq, void *dev_id) in imx_uart_int()
946 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; in imx_uart_int()
955 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_int()
967 * actions, for example if a character that sits in the RX FIFO and that in imx_uart_int()
1020 sport->port.icount.overrun++; in imx_uart_int()
1025 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_int()
1033 static unsigned int imx_uart_tx_empty(struct uart_port *port) in imx_uart_tx_empty()
1036 unsigned int ret; in imx_uart_tx_empty()
1041 if (sport->dma_is_txing) in imx_uart_tx_empty()
1048 static unsigned int imx_uart_get_mctrl(struct uart_port *port) in imx_uart_get_mctrl()
1051 unsigned int ret = imx_uart_get_hwmctrl(sport); in imx_uart_get_mctrl()
1053 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1059 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) in imx_uart_set_mctrl()
1064 if (!(port->rs485.flags & SER_RS485_ENABLED)) { in imx_uart_set_mctrl()
1096 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1102 static void imx_uart_break_ctl(struct uart_port *port, int break_state) in imx_uart_break_ctl()
1108 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_break_ctl()
1117 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_break_ctl()
1121 * This is our per-port timeout handler, for checking the
1129 if (sport->port.state) { in imx_uart_timeout()
1130 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_timeout()
1132 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_timeout()
1134 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1139 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1140 * [1] the RX DMA buffer is full.
1149 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1150 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1151 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1153 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1155 unsigned int w_bytes = 0; in imx_uart_dma_rx_callback()
1156 unsigned int r_bytes; in imx_uart_dma_rx_callback()
1157 unsigned int bd_size; in imx_uart_dma_rx_callback()
1159 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1166 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1169 * The state-residue variable represents the empty space in imx_uart_dma_rx_callback()
1172 * length - DMA transaction residue. The UART script from the in imx_uart_dma_rx_callback()
1174 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). in imx_uart_dma_rx_callback()
1180 rx_ring->head = sg_dma_len(sgl) - state.residue; in imx_uart_dma_rx_callback()
1183 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1184 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; in imx_uart_dma_rx_callback()
1186 if (rx_ring->head <= sg_dma_len(sgl) && in imx_uart_dma_rx_callback()
1187 rx_ring->head > rx_ring->tail) { in imx_uart_dma_rx_callback()
1190 r_bytes = rx_ring->head - rx_ring->tail; in imx_uart_dma_rx_callback()
1192 /* CPU claims ownership of RX DMA buffer */ in imx_uart_dma_rx_callback()
1193 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1197 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1199 /* UART retrieves ownership of RX DMA buffer */ in imx_uart_dma_rx_callback()
1200 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1204 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1206 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1208 WARN_ON(rx_ring->head > sg_dma_len(sgl)); in imx_uart_dma_rx_callback()
1209 WARN_ON(rx_ring->head <= rx_ring->tail); in imx_uart_dma_rx_callback()
1215 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1219 /* RX DMA buffer periods */
1223 static int imx_uart_start_rx_dma(struct imx_port *sport) in imx_uart_start_rx_dma()
1225 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1226 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1227 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1229 int ret; in imx_uart_start_rx_dma()
1231 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1232 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1233 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_start_rx_dma()
1235 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); in imx_uart_start_rx_dma()
1238 dev_err(dev, "DMA mapping error for RX.\n"); in imx_uart_start_rx_dma()
1239 return -EINVAL; in imx_uart_start_rx_dma()
1243 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1248 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); in imx_uart_start_rx_dma()
1249 return -EINVAL; in imx_uart_start_rx_dma()
1251 desc->callback = imx_uart_dma_rx_callback; in imx_uart_start_rx_dma()
1252 desc->callback_param = sport; in imx_uart_start_rx_dma()
1254 dev_dbg(dev, "RX: prepare for the DMA.\n"); in imx_uart_start_rx_dma()
1255 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1256 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1263 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1270 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1272 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1274 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1278 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1281 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1287 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1301 unsigned int val; in imx_uart_setup_ufcr()
1311 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1312 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1313 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1314 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1315 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1316 kfree(sport->rx_buf); in imx_uart_dma_exit()
1317 sport->rx_buf = NULL; in imx_uart_dma_exit()
1320 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1321 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1322 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1323 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1327 static int imx_uart_dma_init(struct imx_port *sport) in imx_uart_dma_init()
1330 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1331 int ret; in imx_uart_dma_init()
1333 /* Prepare for RX : */ in imx_uart_dma_init()
1334 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); in imx_uart_dma_init()
1335 if (!sport->dma_chan_rx) { in imx_uart_dma_init()
1337 ret = -EINVAL; in imx_uart_dma_init()
1342 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1345 slave_config.src_maxburst = RXTL_DMA - 1; in imx_uart_dma_init()
1346 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1348 dev_err(dev, "error in RX dma configuration.\n"); in imx_uart_dma_init()
1352 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); in imx_uart_dma_init()
1353 if (!sport->rx_buf) { in imx_uart_dma_init()
1354 ret = -ENOMEM; in imx_uart_dma_init()
1357 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1360 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); in imx_uart_dma_init()
1361 if (!sport->dma_chan_tx) { in imx_uart_dma_init()
1363 ret = -EINVAL; in imx_uart_dma_init()
1368 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1371 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1394 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1408 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1411 /* half the RX buffer size */
1414 static int imx_uart_startup(struct uart_port *port) in imx_uart_startup()
1417 int retval, i; in imx_uart_startup()
1419 int dma_is_inited = 0; in imx_uart_startup()
1422 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1425 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1427 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1448 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_startup()
1456 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_startup()
1467 if (sport->have_rtscts) in imx_uart_startup()
1473 if (!sport->dma_is_enabled) in imx_uart_startup()
1475 if (sport->inverted_rx) in imx_uart_startup()
1483 if (sport->inverted_tx) in imx_uart_startup()
1489 if (sport->dte_mode) in imx_uart_startup()
1497 if (!sport->have_rtscts) in imx_uart_startup()
1500 * make sure the edge sensitive RTS-irq is disabled, in imx_uart_startup()
1510 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1525 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_startup()
1536 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1537 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1538 if (sport->dma_is_txing) { in imx_uart_shutdown()
1539 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1540 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1541 sport->dma_is_txing = 0; in imx_uart_shutdown()
1543 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1544 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1545 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1547 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1550 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1554 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1558 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1560 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1564 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1569 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1575 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1585 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1587 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1588 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1595 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1597 int i = 100, ubir, ubmr, uts; in imx_uart_flush_buffer()
1599 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1602 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1603 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1604 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1607 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1612 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1620 * and UTS[6-3]". in imx_uart_flush_buffer()
1634 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_flush_buffer()
1650 unsigned int baud, quot; in imx_uart_set_termios()
1651 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in imx_uart_set_termios()
1659 while ((termios->c_cflag & CSIZE) != CS7 && in imx_uart_set_termios()
1660 (termios->c_cflag & CSIZE) != CS8) { in imx_uart_set_termios()
1661 termios->c_cflag &= ~CSIZE; in imx_uart_set_termios()
1662 termios->c_cflag |= old_csize; in imx_uart_set_termios()
1666 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1671 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in imx_uart_set_termios()
1674 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_set_termios()
1684 if ((termios->c_cflag & CSIZE) == CS8) in imx_uart_set_termios()
1687 if (!sport->have_rtscts) in imx_uart_set_termios()
1688 termios->c_cflag &= ~CRTSCTS; in imx_uart_set_termios()
1690 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_set_termios()
1696 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_set_termios()
1701 } else if (termios->c_cflag & CRTSCTS) { in imx_uart_set_termios()
1710 if (termios->c_cflag & CRTSCTS) in imx_uart_set_termios()
1712 if (termios->c_cflag & CSTOPB) in imx_uart_set_termios()
1714 if (termios->c_cflag & PARENB) { in imx_uart_set_termios()
1716 if (termios->c_cflag & PARODD) in imx_uart_set_termios()
1720 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1721 if (termios->c_iflag & INPCK) in imx_uart_set_termios()
1722 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1723 if (termios->c_iflag & (BRKINT | PARMRK)) in imx_uart_set_termios()
1724 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1729 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1730 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1731 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1732 if (termios->c_iflag & IGNBRK) { in imx_uart_set_termios()
1733 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1738 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1739 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1742 if ((termios->c_cflag & CREAD) == 0) in imx_uart_set_termios()
1743 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1746 * Update the per-port timeout. in imx_uart_set_termios()
1748 uart_update_timeout(port, termios->c_cflag, baud); in imx_uart_set_termios()
1750 /* custom-baudrate handling */ in imx_uart_set_termios()
1751 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1753 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1755 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1761 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1764 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1770 num -= 1; in imx_uart_set_termios()
1771 denom -= 1; in imx_uart_set_termios()
1794 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1799 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1800 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1802 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_set_termios()
1809 return sport->port.type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1815 static void imx_uart_config_port(struct uart_port *port, int flags) in imx_uart_config_port()
1820 sport->port.type = PORT_IMX; in imx_uart_config_port()
1828 static int
1832 int ret = 0; in imx_uart_verify_port()
1834 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) in imx_uart_verify_port()
1835 ret = -EINVAL; in imx_uart_verify_port()
1836 if (sport->port.irq != ser->irq) in imx_uart_verify_port()
1837 ret = -EINVAL; in imx_uart_verify_port()
1838 if (ser->io_type != UPIO_MEM) in imx_uart_verify_port()
1839 ret = -EINVAL; in imx_uart_verify_port()
1840 if (sport->port.uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1841 ret = -EINVAL; in imx_uart_verify_port()
1842 if (sport->port.mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1843 ret = -EINVAL; in imx_uart_verify_port()
1844 if (sport->port.iobase != ser->port) in imx_uart_verify_port()
1845 ret = -EINVAL; in imx_uart_verify_port()
1846 if (ser->hub6 != 0) in imx_uart_verify_port()
1847 ret = -EINVAL; in imx_uart_verify_port()
1853 static int imx_uart_poll_init(struct uart_port *port) in imx_uart_poll_init()
1858 int retval; in imx_uart_poll_init()
1860 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1863 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1865 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1869 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_poll_init()
1874 * This prevents that a character that already sits in the RX fifo is in imx_uart_poll_init()
1897 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_poll_init()
1902 static int imx_uart_poll_get_char(struct uart_port *port) in imx_uart_poll_get_char()
1914 unsigned int status; in imx_uart_poll_put_char()
1932 static int imx_uart_rs485_config(struct uart_port *port, in imx_uart_rs485_config()
1939 if (!sport->have_rtscts && !sport->have_rtsgpio) in imx_uart_rs485_config()
1940 rs485conf->flags &= ~SER_RS485_ENABLED; in imx_uart_rs485_config()
1942 if (rs485conf->flags & SER_RS485_ENABLED) { in imx_uart_rs485_config()
1943 /* Enable receiver if low-active RTS signal is requested */ in imx_uart_rs485_config()
1944 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
1945 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) in imx_uart_rs485_config()
1946 rs485conf->flags |= SER_RS485_RX_DURING_TX; in imx_uart_rs485_config()
1950 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_rs485_config()
1957 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ in imx_uart_rs485_config()
1958 if (!(rs485conf->flags & SER_RS485_ENABLED) || in imx_uart_rs485_config()
1959 rs485conf->flags & SER_RS485_RX_DURING_TX) in imx_uart_rs485_config()
1962 port->rs485 = *rs485conf; in imx_uart_rs485_config()
1993 static void imx_uart_console_putchar(struct uart_port *port, int ch) in imx_uart_console_putchar()
2007 imx_uart_console_write(struct console *co, const char *s, unsigned int count) in imx_uart_console_write()
2009 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write()
2011 unsigned int ucr1; in imx_uart_console_write()
2013 int locked = 1; in imx_uart_console_write()
2015 if (sport->port.sysrq) in imx_uart_console_write()
2018 locked = spin_trylock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2020 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2037 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); in imx_uart_console_write()
2048 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_console_write()
2056 imx_uart_console_get_options(struct imx_port *sport, int *baud, in imx_uart_console_get_options()
2057 int *parity, int *bits) in imx_uart_console_get_options()
2062 unsigned int ucr2, ubir, ubmr, uartclk; in imx_uart_console_get_options()
2063 unsigned int baud_raw; in imx_uart_console_get_options()
2064 unsigned int ucfr_rfdiv; in imx_uart_console_get_options()
2088 ucfr_rfdiv = 6 - ucfr_rfdiv; in imx_uart_console_get_options()
2090 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2099 unsigned int mul = ubir + 1; in imx_uart_console_get_options()
2100 unsigned int div = 16 * (ubmr + 1); in imx_uart_console_get_options()
2101 unsigned int rem = uartclk % div; in imx_uart_console_get_options()
2109 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2114 static int
2118 int baud = 9600; in imx_uart_console_setup()
2119 int bits = 8; in imx_uart_console_setup()
2120 int parity = 'n'; in imx_uart_console_setup()
2121 int flow = 'n'; in imx_uart_console_setup()
2122 int retval; in imx_uart_console_setup()
2129 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) in imx_uart_console_setup()
2130 co->index = 0; in imx_uart_console_setup()
2131 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2133 return -ENODEV; in imx_uart_console_setup()
2136 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2147 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2150 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2154 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2156 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2169 .index = -1,
2194 static int imx_uart_probe_dt(struct imx_port *sport, in imx_uart_probe_dt()
2197 struct device_node *np = pdev->dev.of_node; in imx_uart_probe_dt()
2198 int ret; in imx_uart_probe_dt()
2200 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe_dt()
2201 if (!sport->devdata) in imx_uart_probe_dt()
2207 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in imx_uart_probe_dt()
2210 sport->port.line = ret; in imx_uart_probe_dt()
2212 if (of_get_property(np, "uart-has-rtscts", NULL) || in imx_uart_probe_dt()
2213 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) in imx_uart_probe_dt()
2214 sport->have_rtscts = 1; in imx_uart_probe_dt()
2216 if (of_get_property(np, "fsl,dte-mode", NULL)) in imx_uart_probe_dt()
2217 sport->dte_mode = 1; in imx_uart_probe_dt()
2219 if (of_get_property(np, "rts-gpios", NULL)) in imx_uart_probe_dt()
2220 sport->have_rtsgpio = 1; in imx_uart_probe_dt()
2222 if (of_get_property(np, "fsl,inverted-tx", NULL)) in imx_uart_probe_dt()
2223 sport->inverted_tx = 1; in imx_uart_probe_dt()
2225 if (of_get_property(np, "fsl,inverted-rx", NULL)) in imx_uart_probe_dt()
2226 sport->inverted_rx = 1; in imx_uart_probe_dt()
2231 static inline int imx_uart_probe_dt(struct imx_port *sport, in imx_uart_probe_dt()
2241 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); in imx_uart_probe_pdata()
2243 sport->port.line = pdev->id; in imx_uart_probe_pdata()
2244 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; in imx_uart_probe_pdata()
2249 if (pdata->flags & IMXUART_HAVE_RTSCTS) in imx_uart_probe_pdata()
2250 sport->have_rtscts = 1; in imx_uart_probe_pdata()
2258 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_start_tx()
2259 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2260 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2261 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_start_tx()
2271 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_stop_tx()
2272 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2273 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2274 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_stop_tx()
2279 static int imx_uart_probe(struct platform_device *pdev) in imx_uart_probe()
2283 int ret = 0; in imx_uart_probe()
2286 int txirq, rxirq, rtsirq; in imx_uart_probe()
2288 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2290 return -ENOMEM; in imx_uart_probe()
2298 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2299 dev_err(&pdev->dev, "serial%d out of range\n", in imx_uart_probe()
2300 sport->port.line); in imx_uart_probe()
2301 return -EINVAL; in imx_uart_probe()
2305 base = devm_ioremap_resource(&pdev->dev, res); in imx_uart_probe()
2315 sport->port.dev = &pdev->dev; in imx_uart_probe()
2316 sport->port.mapbase = res->start; in imx_uart_probe()
2317 sport->port.membase = base; in imx_uart_probe()
2318 sport->port.type = PORT_IMX, in imx_uart_probe()
2319 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2320 sport->port.irq = rxirq; in imx_uart_probe()
2321 sport->port.fifosize = 32; in imx_uart_probe()
2322 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2323 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2324 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2325 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2326 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2328 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2329 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2330 return PTR_ERR(sport->gpios); in imx_uart_probe()
2332 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2333 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2334 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2335 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); in imx_uart_probe()
2339 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2340 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2341 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2342 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); in imx_uart_probe()
2346 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2349 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2351 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); in imx_uart_probe()
2356 sport->ucr1 = readl(sport->port.membase + UCR1); in imx_uart_probe()
2357 sport->ucr2 = readl(sport->port.membase + UCR2); in imx_uart_probe()
2358 sport->ucr3 = readl(sport->port.membase + UCR3); in imx_uart_probe()
2359 sport->ucr4 = readl(sport->port.membase + UCR4); in imx_uart_probe()
2360 sport->ufcr = readl(sport->port.membase + UFCR); in imx_uart_probe()
2362 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2364 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2368 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2369 (!sport->have_rtscts && !sport->have_rtsgpio)) in imx_uart_probe()
2370 dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); in imx_uart_probe()
2377 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2378 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2379 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2380 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2381 dev_err(&pdev->dev, in imx_uart_probe()
2382 "low-active RTS not possible when receiver is off, enabling receiver\n"); in imx_uart_probe()
2384 imx_uart_rs485_config(&sport->port, &sport->port.rs485); in imx_uart_probe()
2391 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2422 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2424 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2425 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2426 sport->trigger_start_tx.function = imx_trigger_start_tx; in imx_uart_probe()
2427 sport->trigger_stop_tx.function = imx_trigger_stop_tx; in imx_uart_probe()
2434 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, in imx_uart_probe()
2435 dev_name(&pdev->dev), sport); in imx_uart_probe()
2437 dev_err(&pdev->dev, "failed to request rx irq: %d\n", in imx_uart_probe()
2442 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, in imx_uart_probe()
2443 dev_name(&pdev->dev), sport); in imx_uart_probe()
2445 dev_err(&pdev->dev, "failed to request tx irq: %d\n", in imx_uart_probe()
2450 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, in imx_uart_probe()
2451 dev_name(&pdev->dev), sport); in imx_uart_probe()
2453 dev_err(&pdev->dev, "failed to request rts irq: %d\n", in imx_uart_probe()
2458 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, in imx_uart_probe()
2459 dev_name(&pdev->dev), sport); in imx_uart_probe()
2461 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); in imx_uart_probe()
2466 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2470 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2473 static int imx_uart_remove(struct platform_device *pdev) in imx_uart_remove()
2477 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2484 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_restore_context()
2485 if (!sport->context_saved) { in imx_uart_restore_context()
2486 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2490 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2491 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2492 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2493 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2494 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2495 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2496 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2497 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2498 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2499 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2500 sport->context_saved = false; in imx_uart_restore_context()
2501 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2509 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_save_context()
2510 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2511 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2512 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2513 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2514 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2515 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2516 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2517 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2518 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2519 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2520 sport->context_saved = true; in imx_uart_save_context()
2521 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_save_context()
2537 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2547 static int imx_uart_suspend_noirq(struct device *dev) in imx_uart_suspend_noirq()
2553 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2560 static int imx_uart_resume_noirq(struct device *dev) in imx_uart_resume_noirq()
2563 int ret; in imx_uart_resume_noirq()
2567 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2576 static int imx_uart_suspend(struct device *dev) in imx_uart_suspend()
2579 int ret; in imx_uart_suspend()
2581 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2582 disable_irq(sport->port.irq); in imx_uart_suspend()
2584 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2594 static int imx_uart_resume(struct device *dev) in imx_uart_resume()
2601 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2602 enable_irq(sport->port.irq); in imx_uart_resume()
2604 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2609 static int imx_uart_freeze(struct device *dev) in imx_uart_freeze()
2613 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2615 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2618 static int imx_uart_thaw(struct device *dev) in imx_uart_thaw()
2622 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2624 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()
2647 .name = "imx-uart",
2653 static int __init imx_uart_init(void) in imx_uart_init()
2655 int ret = uart_register_driver(&imx_uart_uart_driver); in imx_uart_init()
2679 MODULE_ALIAS("platform:imx-uart");