Lines Matching +full:port +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
46 * - only on 75x/76x
49 * - only on 75x/76x
52 * - only on 75x/76x
55 * - only on 75x/76x
59 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
63 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
75 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
76 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
78 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
80 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
83 /* IER register bits - write only if (EFR[4] == 1) */
84 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
85 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
86 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
87 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
90 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
91 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
92 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
93 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
94 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
96 /* FCR register bits - write only if (EFR[4] == 1) */
97 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
98 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
101 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
106 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
108 * - only on 75x/76x
111 * - only on 75x/76x
119 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
120 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
123 * 00 -> 5 bit words
124 * 01 -> 6 bit words
125 * 10 -> 7 bit words
126 * 11 -> 8 bit words
128 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
131 * 0 -> 1 stop bit
132 * 1 -> 1-1.5 stop bits if
136 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
137 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
138 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
139 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
140 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
151 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
152 * - only on 75x/76x
154 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
155 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
156 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
157 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
158 * - write enabled
159 * if (EFR[4] == 1)
161 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
162 * - write enabled
163 * if (EFR[4] == 1)
165 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
166 * - write enabled
167 * if (EFR[4] == 1)
171 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
172 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
173 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
174 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
175 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
177 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
178 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
179 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
182 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
183 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
185 * - only on 75x/76x
187 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
189 * - only on 75x/76x
191 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
193 * - only on 75x/76x
195 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */
196 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4)
197 * - only on 75x/76x
199 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7)
200 * - only on 75x/76x
202 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6)
203 * - only on 75x/76x
212 * no built-in hardware check to make sure this condition is met. Also, the TCR
227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
238 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
239 #define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */
240 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
243 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
245 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
246 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
247 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
248 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
249 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
251 * - Only 750/760
252 * 1 = rate upto 1.152 Mbit/s
253 * - Only 760
257 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
258 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
259 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
260 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
264 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
265 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
268 * 00 -> no transmitter flow
270 * 01 -> transmitter generates
272 * 10 -> transmitter generates
274 * 11 -> transmitter generates
278 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
279 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
282 * 00 -> no received flow
284 * 01 -> receiver compares
286 * 10 -> receiver compares
288 * 11 -> receiver compares
303 #define SC16IS7XX_RECONF_MD (1 << 0)
304 #define SC16IS7XX_RECONF_IER (1 << 1)
305 #define SC16IS7XX_RECONF_RS485 (1 << 2)
313 struct uart_port port; member
346 static int sc16is7xx_line(struct uart_port *port) in sc16is7xx_line() argument
348 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); in sc16is7xx_line()
350 return one->line; in sc16is7xx_line()
353 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) in sc16is7xx_port_read() argument
355 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_port_read()
357 const u8 line = sc16is7xx_line(port); in sc16is7xx_port_read()
359 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val); in sc16is7xx_port_read()
364 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) in sc16is7xx_port_write() argument
366 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_port_write()
367 const u8 line = sc16is7xx_line(port); in sc16is7xx_port_write()
369 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val); in sc16is7xx_port_write()
372 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen) in sc16is7xx_fifo_read() argument
374 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_fifo_read()
375 const u8 line = sc16is7xx_line(port); in sc16is7xx_fifo_read()
378 regcache_cache_bypass(s->regmap, true); in sc16is7xx_fifo_read()
379 regmap_raw_read(s->regmap, addr, s->buf, rxlen); in sc16is7xx_fifo_read()
380 regcache_cache_bypass(s->regmap, false); in sc16is7xx_fifo_read()
383 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send) in sc16is7xx_fifo_write() argument
385 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_fifo_write()
386 const u8 line = sc16is7xx_line(port); in sc16is7xx_fifo_write()
390 * Don't send zero-length data, at least on SPI it confuses the chip in sc16is7xx_fifo_write()
396 regcache_cache_bypass(s->regmap, true); in sc16is7xx_fifo_write()
397 regmap_raw_write(s->regmap, addr, s->buf, to_send); in sc16is7xx_fifo_write()
398 regcache_cache_bypass(s->regmap, false); in sc16is7xx_fifo_write()
401 static void sc16is7xx_port_update(struct uart_port *port, u8 reg, in sc16is7xx_port_update() argument
404 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_port_update()
405 const u8 line = sc16is7xx_line(port); in sc16is7xx_port_update()
407 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, in sc16is7xx_port_update()
424 static void sc16is7xx_power(struct uart_port *port, int on) in sc16is7xx_power() argument
426 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, in sc16is7xx_power()
434 .nr_uart = 1,
440 .nr_uart = 1,
452 .nr_uart = 1,
491 static int sc16is7xx_set_baud(struct uart_port *port, int baud) in sc16is7xx_set_baud() argument
493 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_set_baud()
496 unsigned long clk = port->uartclk, div = clk / 16 / baud; in sc16is7xx_set_baud()
516 mutex_lock(&s->efr_lock); in sc16is7xx_set_baud()
518 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); in sc16is7xx_set_baud()
521 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, in sc16is7xx_set_baud()
525 regcache_cache_bypass(s->regmap, true); in sc16is7xx_set_baud()
526 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, in sc16is7xx_set_baud()
528 regcache_cache_bypass(s->regmap, false); in sc16is7xx_set_baud()
531 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); in sc16is7xx_set_baud()
533 mutex_unlock(&s->efr_lock); in sc16is7xx_set_baud()
535 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, in sc16is7xx_set_baud()
540 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, in sc16is7xx_set_baud()
544 regcache_cache_bypass(s->regmap, true); in sc16is7xx_set_baud()
545 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); in sc16is7xx_set_baud()
546 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); in sc16is7xx_set_baud()
547 regcache_cache_bypass(s->regmap, false); in sc16is7xx_set_baud()
550 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); in sc16is7xx_set_baud()
555 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, in sc16is7xx_handle_rx() argument
558 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_handle_rx()
562 if (unlikely(rxlen >= sizeof(s->buf))) { in sc16is7xx_handle_rx()
563 dev_warn_ratelimited(port->dev, in sc16is7xx_handle_rx()
565 port->line, rxlen); in sc16is7xx_handle_rx()
566 port->icount.buf_overrun++; in sc16is7xx_handle_rx()
568 rxlen = sizeof(s->buf); in sc16is7xx_handle_rx()
574 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); in sc16is7xx_handle_rx()
581 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); in sc16is7xx_handle_rx()
582 bytes_read = 1; in sc16is7xx_handle_rx()
584 sc16is7xx_fifo_read(port, rxlen); in sc16is7xx_handle_rx()
590 port->icount.rx++; in sc16is7xx_handle_rx()
595 port->icount.brk++; in sc16is7xx_handle_rx()
596 if (uart_handle_break(port)) in sc16is7xx_handle_rx()
599 port->icount.parity++; in sc16is7xx_handle_rx()
601 port->icount.frame++; in sc16is7xx_handle_rx()
603 port->icount.overrun++; in sc16is7xx_handle_rx()
605 lsr &= port->read_status_mask; in sc16is7xx_handle_rx()
617 ch = s->buf[i]; in sc16is7xx_handle_rx()
618 if (uart_handle_sysrq_char(port, ch)) in sc16is7xx_handle_rx()
621 if (lsr & port->ignore_status_mask) in sc16is7xx_handle_rx()
624 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, in sc16is7xx_handle_rx()
627 rxlen -= bytes_read; in sc16is7xx_handle_rx()
630 tty_flip_buffer_push(&port->state->port); in sc16is7xx_handle_rx()
633 static void sc16is7xx_handle_tx(struct uart_port *port) in sc16is7xx_handle_tx() argument
635 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_handle_tx()
636 struct circ_buf *xmit = &port->state->xmit; in sc16is7xx_handle_tx()
639 if (unlikely(port->x_char)) { in sc16is7xx_handle_tx()
640 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); in sc16is7xx_handle_tx()
641 port->icount.tx++; in sc16is7xx_handle_tx()
642 port->x_char = 0; in sc16is7xx_handle_tx()
646 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) in sc16is7xx_handle_tx()
653 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); in sc16is7xx_handle_tx()
655 dev_err_ratelimited(port->dev, in sc16is7xx_handle_tx()
663 port->icount.tx += to_send; in sc16is7xx_handle_tx()
667 s->buf[i] = xmit->buf[xmit->tail]; in sc16is7xx_handle_tx()
668 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in sc16is7xx_handle_tx()
671 sc16is7xx_fifo_write(port, to_send); in sc16is7xx_handle_tx()
675 uart_write_wakeup(port); in sc16is7xx_handle_tx()
680 struct uart_port *port = &s->p[portno].port; in sc16is7xx_port_irq() local
685 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); in sc16is7xx_port_irq()
696 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); in sc16is7xx_port_irq()
698 sc16is7xx_handle_rx(port, rxlen, iir); in sc16is7xx_port_irq()
701 sc16is7xx_handle_tx(port); in sc16is7xx_port_irq()
704 dev_err_ratelimited(port->dev, in sc16is7xx_port_irq()
706 port->line, iir); in sc16is7xx_port_irq()
717 mutex_lock(&s->efr_lock); in sc16is7xx_irq()
719 while (1) { in sc16is7xx_irq()
723 for (i = 0; i < s->devtype->nr_uart; ++i) in sc16is7xx_irq()
729 mutex_unlock(&s->efr_lock); in sc16is7xx_irq()
736 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); in sc16is7xx_tx_proc() local
738 if ((port->rs485.flags & SER_RS485_ENABLED) && in sc16is7xx_tx_proc()
739 (port->rs485.delay_rts_before_send > 0)) in sc16is7xx_tx_proc()
740 msleep(port->rs485.delay_rts_before_send); in sc16is7xx_tx_proc()
742 sc16is7xx_handle_tx(port); in sc16is7xx_tx_proc()
745 static void sc16is7xx_reconf_rs485(struct uart_port *port) in sc16is7xx_reconf_rs485() argument
750 struct serial_rs485 *rs485 = &port->rs485; in sc16is7xx_reconf_rs485()
753 spin_lock_irqsave(&port->lock, irqflags); in sc16is7xx_reconf_rs485()
754 if (rs485->flags & SER_RS485_ENABLED) { in sc16is7xx_reconf_rs485()
757 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in sc16is7xx_reconf_rs485()
760 spin_unlock_irqrestore(&port->lock, irqflags); in sc16is7xx_reconf_rs485()
762 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); in sc16is7xx_reconf_rs485()
771 spin_lock_irqsave(&one->port.lock, irqflags); in sc16is7xx_reg_proc()
772 config = one->config; in sc16is7xx_reg_proc()
773 memset(&one->config, 0, sizeof(one->config)); in sc16is7xx_reg_proc()
774 spin_unlock_irqrestore(&one->port.lock, irqflags); in sc16is7xx_reg_proc()
777 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, in sc16is7xx_reg_proc()
779 (one->port.mctrl & TIOCM_LOOP) ? in sc16is7xx_reg_proc()
781 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, in sc16is7xx_reg_proc()
783 (one->port.mctrl & TIOCM_RTS) ? in sc16is7xx_reg_proc()
785 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, in sc16is7xx_reg_proc()
787 (one->port.mctrl & TIOCM_DTR) ? in sc16is7xx_reg_proc()
791 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, in sc16is7xx_reg_proc()
795 sc16is7xx_reconf_rs485(&one->port); in sc16is7xx_reg_proc()
798 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) in sc16is7xx_ier_clear() argument
800 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_ier_clear()
801 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); in sc16is7xx_ier_clear()
803 one->config.flags |= SC16IS7XX_RECONF_IER; in sc16is7xx_ier_clear()
804 one->config.ier_clear |= bit; in sc16is7xx_ier_clear()
805 kthread_queue_work(&s->kworker, &one->reg_work); in sc16is7xx_ier_clear()
808 static void sc16is7xx_stop_tx(struct uart_port *port) in sc16is7xx_stop_tx() argument
810 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); in sc16is7xx_stop_tx()
813 static void sc16is7xx_stop_rx(struct uart_port *port) in sc16is7xx_stop_rx() argument
815 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); in sc16is7xx_stop_rx()
818 static void sc16is7xx_start_tx(struct uart_port *port) in sc16is7xx_start_tx() argument
820 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_start_tx()
821 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); in sc16is7xx_start_tx()
823 kthread_queue_work(&s->kworker, &one->tx_work); in sc16is7xx_start_tx()
826 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) in sc16is7xx_tx_empty() argument
830 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); in sc16is7xx_tx_empty()
835 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) in sc16is7xx_get_mctrl() argument
843 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) in sc16is7xx_set_mctrl() argument
845 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_set_mctrl()
846 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); in sc16is7xx_set_mctrl()
848 one->config.flags |= SC16IS7XX_RECONF_MD; in sc16is7xx_set_mctrl()
849 kthread_queue_work(&s->kworker, &one->reg_work); in sc16is7xx_set_mctrl()
852 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) in sc16is7xx_break_ctl() argument
854 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, in sc16is7xx_break_ctl()
859 static void sc16is7xx_set_termios(struct uart_port *port, in sc16is7xx_set_termios() argument
863 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_set_termios()
868 termios->c_cflag &= ~CMSPAR; in sc16is7xx_set_termios()
871 switch (termios->c_cflag & CSIZE) { in sc16is7xx_set_termios()
886 termios->c_cflag &= ~CSIZE; in sc16is7xx_set_termios()
887 termios->c_cflag |= CS8; in sc16is7xx_set_termios()
892 if (termios->c_cflag & PARENB) { in sc16is7xx_set_termios()
894 if (!(termios->c_cflag & PARODD)) in sc16is7xx_set_termios()
899 if (termios->c_cflag & CSTOPB) in sc16is7xx_set_termios()
903 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; in sc16is7xx_set_termios()
904 if (termios->c_iflag & INPCK) in sc16is7xx_set_termios()
905 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | in sc16is7xx_set_termios()
907 if (termios->c_iflag & (BRKINT | PARMRK)) in sc16is7xx_set_termios()
908 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; in sc16is7xx_set_termios()
911 port->ignore_status_mask = 0; in sc16is7xx_set_termios()
912 if (termios->c_iflag & IGNBRK) in sc16is7xx_set_termios()
913 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; in sc16is7xx_set_termios()
914 if (!(termios->c_cflag & CREAD)) in sc16is7xx_set_termios()
915 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; in sc16is7xx_set_termios()
918 mutex_lock(&s->efr_lock); in sc16is7xx_set_termios()
920 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, in sc16is7xx_set_termios()
924 regcache_cache_bypass(s->regmap, true); in sc16is7xx_set_termios()
925 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); in sc16is7xx_set_termios()
926 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); in sc16is7xx_set_termios()
927 if (termios->c_cflag & CRTSCTS) in sc16is7xx_set_termios()
930 if (termios->c_iflag & IXON) in sc16is7xx_set_termios()
932 if (termios->c_iflag & IXOFF) in sc16is7xx_set_termios()
935 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow); in sc16is7xx_set_termios()
936 regcache_cache_bypass(s->regmap, false); in sc16is7xx_set_termios()
939 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); in sc16is7xx_set_termios()
941 mutex_unlock(&s->efr_lock); in sc16is7xx_set_termios()
944 baud = uart_get_baud_rate(port, termios, old, in sc16is7xx_set_termios()
945 port->uartclk / 16 / 4 / 0xffff, in sc16is7xx_set_termios()
946 port->uartclk / 16); in sc16is7xx_set_termios()
949 baud = sc16is7xx_set_baud(port, baud); in sc16is7xx_set_termios()
952 uart_update_timeout(port, termios->c_cflag, baud); in sc16is7xx_set_termios()
955 static int sc16is7xx_config_rs485(struct uart_port *port, in sc16is7xx_config_rs485() argument
958 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_config_rs485()
959 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); in sc16is7xx_config_rs485()
961 if (rs485->flags & SER_RS485_ENABLED) { in sc16is7xx_config_rs485()
964 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND; in sc16is7xx_config_rs485()
965 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND; in sc16is7xx_config_rs485()
968 dev_err(port->dev, in sc16is7xx_config_rs485()
969 …"unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be se… in sc16is7xx_config_rs485()
977 if (rs485->delay_rts_after_send) in sc16is7xx_config_rs485()
978 return -EINVAL; in sc16is7xx_config_rs485()
981 port->rs485 = *rs485; in sc16is7xx_config_rs485()
982 one->config.flags |= SC16IS7XX_RECONF_RS485; in sc16is7xx_config_rs485()
983 kthread_queue_work(&s->kworker, &one->reg_work); in sc16is7xx_config_rs485()
988 static int sc16is7xx_startup(struct uart_port *port) in sc16is7xx_startup() argument
990 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); in sc16is7xx_startup()
991 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_startup()
994 sc16is7xx_power(port, 1); in sc16is7xx_startup()
998 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); in sc16is7xx_startup()
1000 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, in sc16is7xx_startup()
1004 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, in sc16is7xx_startup()
1007 regcache_cache_bypass(s->regmap, true); in sc16is7xx_startup()
1010 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, in sc16is7xx_startup()
1014 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, in sc16is7xx_startup()
1020 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, in sc16is7xx_startup()
1024 regcache_cache_bypass(s->regmap, false); in sc16is7xx_startup()
1027 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); in sc16is7xx_startup()
1031 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, in sc16is7xx_startup()
1033 one->irda_mode ? in sc16is7xx_startup()
1037 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, in sc16is7xx_startup()
1044 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); in sc16is7xx_startup()
1049 static void sc16is7xx_shutdown(struct uart_port *port) in sc16is7xx_shutdown() argument
1051 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_shutdown()
1054 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); in sc16is7xx_shutdown()
1056 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, in sc16is7xx_shutdown()
1062 sc16is7xx_power(port, 0); in sc16is7xx_shutdown()
1064 kthread_flush_worker(&s->kworker); in sc16is7xx_shutdown()
1067 static const char *sc16is7xx_type(struct uart_port *port) in sc16is7xx_type() argument
1069 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); in sc16is7xx_type()
1071 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; in sc16is7xx_type()
1074 static int sc16is7xx_request_port(struct uart_port *port) in sc16is7xx_request_port() argument
1080 static void sc16is7xx_config_port(struct uart_port *port, int flags) in sc16is7xx_config_port() argument
1083 port->type = PORT_SC16IS7XX; in sc16is7xx_config_port()
1086 static int sc16is7xx_verify_port(struct uart_port *port, in sc16is7xx_verify_port() argument
1089 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) in sc16is7xx_verify_port()
1090 return -EINVAL; in sc16is7xx_verify_port()
1091 if (s->irq != port->irq) in sc16is7xx_verify_port()
1092 return -EINVAL; in sc16is7xx_verify_port()
1097 static void sc16is7xx_pm(struct uart_port *port, unsigned int state, in sc16is7xx_pm() argument
1100 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); in sc16is7xx_pm()
1103 static void sc16is7xx_null_void(struct uart_port *port) in sc16is7xx_null_void() argument
1132 struct uart_port *port = &s->p[0].port; in sc16is7xx_gpio_get() local
1134 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); in sc16is7xx_gpio_get()
1142 struct uart_port *port = &s->p[0].port; in sc16is7xx_gpio_set() local
1144 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), in sc16is7xx_gpio_set()
1152 struct uart_port *port = &s->p[0].port; in sc16is7xx_gpio_direction_input() local
1154 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); in sc16is7xx_gpio_direction_input()
1163 struct uart_port *port = &s->p[0].port; in sc16is7xx_gpio_direction_output() local
1164 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); in sc16is7xx_gpio_direction_output()
1170 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); in sc16is7xx_gpio_direction_output()
1171 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), in sc16is7xx_gpio_direction_output()
1199 return -EPROBE_DEFER; in sc16is7xx_probe()
1201 /* Alloc port structure */ in sc16is7xx_probe()
1202 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); in sc16is7xx_probe()
1204 dev_err(dev, "Error allocating port structure\n"); in sc16is7xx_probe()
1205 return -ENOMEM; in sc16is7xx_probe()
1209 device_property_read_u32(dev, "clock-frequency", &uartclk); in sc16is7xx_probe()
1211 s->clk = devm_clk_get(dev, NULL); in sc16is7xx_probe()
1212 if (IS_ERR(s->clk)) { in sc16is7xx_probe()
1220 return PTR_ERR(s->clk); in sc16is7xx_probe()
1222 ret = clk_prepare_enable(s->clk); in sc16is7xx_probe()
1226 freq = clk_get_rate(s->clk); in sc16is7xx_probe()
1229 s->regmap = regmap; in sc16is7xx_probe()
1230 s->devtype = devtype; in sc16is7xx_probe()
1232 mutex_init(&s->efr_lock); in sc16is7xx_probe()
1234 kthread_init_worker(&s->kworker); in sc16is7xx_probe()
1235 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, in sc16is7xx_probe()
1237 if (IS_ERR(s->kworker_task)) { in sc16is7xx_probe()
1238 ret = PTR_ERR(s->kworker_task); in sc16is7xx_probe()
1241 sched_set_fifo(s->kworker_task); in sc16is7xx_probe()
1244 if (devtype->nr_gpio) { in sc16is7xx_probe()
1246 s->gpio.owner = THIS_MODULE; in sc16is7xx_probe()
1247 s->gpio.parent = dev; in sc16is7xx_probe()
1248 s->gpio.label = dev_name(dev); in sc16is7xx_probe()
1249 s->gpio.direction_input = sc16is7xx_gpio_direction_input; in sc16is7xx_probe()
1250 s->gpio.get = sc16is7xx_gpio_get; in sc16is7xx_probe()
1251 s->gpio.direction_output = sc16is7xx_gpio_direction_output; in sc16is7xx_probe()
1252 s->gpio.set = sc16is7xx_gpio_set; in sc16is7xx_probe()
1253 s->gpio.base = -1; in sc16is7xx_probe()
1254 s->gpio.ngpio = devtype->nr_gpio; in sc16is7xx_probe()
1255 s->gpio.can_sleep = 1; in sc16is7xx_probe()
1256 ret = gpiochip_add_data(&s->gpio, s); in sc16is7xx_probe()
1263 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT, in sc16is7xx_probe()
1266 for (i = 0; i < devtype->nr_uart; ++i) { in sc16is7xx_probe()
1267 s->p[i].line = i; in sc16is7xx_probe()
1268 /* Initialize port data */ in sc16is7xx_probe()
1269 s->p[i].port.dev = dev; in sc16is7xx_probe()
1270 s->p[i].port.irq = irq; in sc16is7xx_probe()
1271 s->p[i].port.type = PORT_SC16IS7XX; in sc16is7xx_probe()
1272 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; in sc16is7xx_probe()
1273 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; in sc16is7xx_probe()
1274 s->p[i].port.iobase = i; in sc16is7xx_probe()
1275 s->p[i].port.iotype = UPIO_PORT; in sc16is7xx_probe()
1276 s->p[i].port.uartclk = freq; in sc16is7xx_probe()
1277 s->p[i].port.rs485_config = sc16is7xx_config_rs485; in sc16is7xx_probe()
1278 s->p[i].port.ops = &sc16is7xx_ops; in sc16is7xx_probe()
1279 s->p[i].port.line = sc16is7xx_alloc_line(); in sc16is7xx_probe()
1280 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) { in sc16is7xx_probe()
1281 ret = -ENOMEM; in sc16is7xx_probe()
1286 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); in sc16is7xx_probe()
1288 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, in sc16is7xx_probe()
1292 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); in sc16is7xx_probe()
1293 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); in sc16is7xx_probe()
1294 /* Register port */ in sc16is7xx_probe()
1295 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port); in sc16is7xx_probe()
1298 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, in sc16is7xx_probe()
1301 regcache_cache_bypass(s->regmap, true); in sc16is7xx_probe()
1304 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG, in sc16is7xx_probe()
1307 regcache_cache_bypass(s->regmap, false); in sc16is7xx_probe()
1310 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00); in sc16is7xx_probe()
1313 sc16is7xx_power(&s->p[i].port, 0); in sc16is7xx_probe()
1316 if (dev->of_node) { in sc16is7xx_probe()
1321 of_property_for_each_u32(dev->of_node, "irda-mode-ports", in sc16is7xx_probe()
1323 if (u < devtype->nr_uart) in sc16is7xx_probe()
1324 s->p[u].irda_mode = true; in sc16is7xx_probe()
1331 * back to a non-shared falling-edge trigger. in sc16is7xx_probe()
1347 for (i--; i >= 0; i--) { in sc16is7xx_probe()
1348 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); in sc16is7xx_probe()
1349 clear_bit(s->p[i].port.line, &sc16is7xx_lines); in sc16is7xx_probe()
1353 if (devtype->nr_gpio) in sc16is7xx_probe()
1354 gpiochip_remove(&s->gpio); in sc16is7xx_probe()
1358 kthread_stop(s->kworker_task); in sc16is7xx_probe()
1361 if (!IS_ERR(s->clk)) in sc16is7xx_probe()
1362 clk_disable_unprepare(s->clk); in sc16is7xx_probe()
1373 if (s->devtype->nr_gpio) in sc16is7xx_remove()
1374 gpiochip_remove(&s->gpio); in sc16is7xx_remove()
1377 for (i = 0; i < s->devtype->nr_uart; i++) { in sc16is7xx_remove()
1378 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); in sc16is7xx_remove()
1379 clear_bit(s->p[i].port.line, &sc16is7xx_lines); in sc16is7xx_remove()
1380 sc16is7xx_power(&s->p[i].port, 0); in sc16is7xx_remove()
1383 kthread_flush_worker(&s->kworker); in sc16is7xx_remove()
1384 kthread_stop(s->kworker_task); in sc16is7xx_remove()
1386 if (!IS_ERR(s->clk)) in sc16is7xx_remove()
1387 clk_disable_unprepare(s->clk); in sc16is7xx_remove()
1405 .pad_bits = 1,
1420 spi->bits_per_word = 8; in sc16is7xx_spi_probe()
1422 spi->mode = spi->mode ? : SPI_MODE_0; in sc16is7xx_spi_probe()
1423 spi->max_speed_hz = spi->max_speed_hz ? : 15000000; in sc16is7xx_spi_probe()
1428 if (spi->dev.of_node) { in sc16is7xx_spi_probe()
1429 devtype = device_get_match_data(&spi->dev); in sc16is7xx_spi_probe()
1431 return -ENODEV; in sc16is7xx_spi_probe()
1435 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data; in sc16is7xx_spi_probe()
1439 (devtype->nr_uart - 1); in sc16is7xx_spi_probe()
1442 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq); in sc16is7xx_spi_probe()
1447 return sc16is7xx_remove(&spi->dev); in sc16is7xx_spi_remove()
1483 if (i2c->dev.of_node) { in sc16is7xx_i2c_probe()
1484 devtype = device_get_match_data(&i2c->dev); in sc16is7xx_i2c_probe()
1486 return -ENODEV; in sc16is7xx_i2c_probe()
1488 devtype = (struct sc16is7xx_devtype *)id->driver_data; in sc16is7xx_i2c_probe()
1492 (devtype->nr_uart - 1); in sc16is7xx_i2c_probe()
1495 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq); in sc16is7xx_i2c_probe()
1500 return sc16is7xx_remove(&client->dev); in sc16is7xx_i2c_remove()
1540 pr_err("failed to init sc16is7xx i2c --> %d\n", ret); in sc16is7xx_init()
1548 pr_err("failed to init sc16is7xx spi --> %d\n", ret); in sc16is7xx_init()