1 // SPDX-License-Identifier: GPL-2.0
14  *			----		-----
15  * Registers:		32-bit		16-bit
34 #define DRIVER_NAME "imx2-wdt"
37 #define IMX2_WDT_WCR_WT		(0xFF << 8)	/* -> Watchdog Timeout Field */
38 #define IMX2_WDT_WCR_WDA	BIT(5)		/* -> External Reset WDOG_B */
39 #define IMX2_WDT_WCR_SRS	BIT(4)		/* -> Software Reset Signal */
40 #define IMX2_WDT_WCR_WRE	BIT(3)		/* -> WDOG Reset Enable */
41 #define IMX2_WDT_WCR_WDE	BIT(2)		/* -> Watchdog Enable */
42 #define IMX2_WDT_WCR_WDZST	BIT(0)		/* -> Watchdog timer Suspend */
45 #define IMX2_WDT_SEQ1		0x5555		/* -> service sequence 1 */
46 #define IMX2_WDT_SEQ2		0xAAAA		/* -> service sequence 2 */
48 #define IMX2_WDT_WRSR		0x04		/* Reset Status Register */
49 #define IMX2_WDT_WRSR_TOUT	BIT(1)		/* -> Reset due to Timeout */
52 #define IMX2_WDT_WICR_WIE	BIT(15)		/* -> Interrupt Enable */
53 #define IMX2_WDT_WICR_WTIS	BIT(14)		/* -> Interrupt Status */
54 #define IMX2_WDT_WICR_WICT	0xFF		/* -> Interrupt Count Timeout */
61 #define WDOG_SEC_TO_COUNT(s)	((s * 2 - 1) << 8)
97 	/* Use internal reset or external - not both */  in imx2_wdt_restart()
98 	if (wdev->ext_reset)  in imx2_wdt_restart()
99 		wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */  in imx2_wdt_restart()
101 		wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */  in imx2_wdt_restart()
104 	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);  in imx2_wdt_restart()
112 	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);  in imx2_wdt_restart()
113 	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);  in imx2_wdt_restart()
115 	/* wait for reset to assert... */  in imx2_wdt_restart()
126 	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);  in imx2_wdt_setup()
128 	/* Suspend timer in low power mode, write once-only */  in imx2_wdt_setup()
130 	/* Strip the old watchdog Time-Out value */  in imx2_wdt_setup()
132 	/* Generate internal chip-level reset if WDOG times out */  in imx2_wdt_setup()
133 	if (!wdev->ext_reset)  in imx2_wdt_setup()
135 	/* Or if external-reset assert WDOG_B reset only on time-out */  in imx2_wdt_setup()
140 	/* Set the watchdog's Time-Out value */  in imx2_wdt_setup()
141 	val |= WDOG_SEC_TO_COUNT(wdog->timeout);  in imx2_wdt_setup()
143 	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);  in imx2_wdt_setup()
147 	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);  in imx2_wdt_setup()
154 	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);  in imx2_wdt_is_running()
163 	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);  in imx2_wdt_ping()
164 	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);  in imx2_wdt_ping()
173 	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,  in __imx2_wdt_set_timeout()
184 	wdog->timeout = new_timeout;  in imx2_wdt_set_timeout()
194 		return -EINVAL;  in imx2_wdt_set_pretimeout()
196 	wdog->pretimeout = new_pretimeout;  in imx2_wdt_set_pretimeout()
198 	regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,  in imx2_wdt_set_pretimeout()
209 	regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,  in imx2_wdt_isr()
222 		imx2_wdt_set_timeout(wdog, wdog->timeout);  in imx2_wdt_start()
226 	set_bit(WDOG_HW_RUNNING, &wdog->status);  in imx2_wdt_start()
254 	struct device *dev = &pdev->dev;  in imx2_wdt_probe()
263 		return -ENOMEM;  in imx2_wdt_probe()
269 	wdev->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,  in imx2_wdt_probe()
271 	if (IS_ERR(wdev->regmap)) {  in imx2_wdt_probe()
273 		return PTR_ERR(wdev->regmap);  in imx2_wdt_probe()
276 	wdev->clk = devm_clk_get(dev, NULL);  in imx2_wdt_probe()
277 	if (IS_ERR(wdev->clk)) {  in imx2_wdt_probe()
279 		return PTR_ERR(wdev->clk);  in imx2_wdt_probe()
282 	wdog			= &wdev->wdog;  in imx2_wdt_probe()
283 	wdog->info		= &imx2_wdt_info;  in imx2_wdt_probe()
284 	wdog->ops		= &imx2_wdt_ops;  in imx2_wdt_probe()
285 	wdog->min_timeout	= 1;  in imx2_wdt_probe()
286 	wdog->timeout		= IMX2_WDT_DEFAULT_TIME;  in imx2_wdt_probe()
287 	wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;  in imx2_wdt_probe()
288 	wdog->parent		= dev;  in imx2_wdt_probe()
294 			wdog->info = &imx2_wdt_pretimeout_info;  in imx2_wdt_probe()
296 	ret = clk_prepare_enable(wdev->clk);  in imx2_wdt_probe()
300 	ret = devm_add_action_or_reset(dev, imx2_wdt_action, wdev->clk);  in imx2_wdt_probe()
304 	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);  in imx2_wdt_probe()
305 	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;  in imx2_wdt_probe()
307 	wdev->ext_reset = of_property_read_bool(dev->of_node,  in imx2_wdt_probe()
308 						"fsl,ext-reset-output");  in imx2_wdt_probe()
316 		imx2_wdt_set_timeout(wdog, wdog->timeout);  in imx2_wdt_probe()
317 		set_bit(WDOG_HW_RUNNING, &wdog->status);  in imx2_wdt_probe()
325 	regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);  in imx2_wdt_probe()
342 		dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");  in imx2_wdt_shutdown()
346 /* Disable watchdog if it is active or non-active but still running */
355 		 * Don't update wdog->timeout, we'll restore the current value  in imx2_wdt_suspend()
362 	clk_disable_unprepare(wdev->clk);  in imx2_wdt_suspend()
374 	ret = clk_prepare_enable(wdev->clk);  in imx2_wdt_resume()
387 		imx2_wdt_set_timeout(wdog, wdog->timeout);  in imx2_wdt_resume()
398 	{ .compatible = "fsl,imx21-wdt", },