Lines Matching +full:buffer +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
138 #define XTAL 0xC000 /* b15-14: Crystal selection */
142 #define XCKE 0x2000 /* b13: External clock enable */
144 #define SCKE 0x0400 /* b10: USB clock enable */
147 #define HSE 0x0080 /* b7: Hi-speed enable */
149 #define DRPD 0x0020 /* b5: D+/- pull down control */
151 #define USBE 0x0001 /* b0: USB module operation enable */
154 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
155 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
157 #define IDMON 0x0004 /* b3: ID-pin monitor */
158 #define LNST 0x0003 /* b1-0: D+, D- line status */
160 #define FS_KSTS 0x0002 /* Full-Speed K State */
161 #define FS_JSTS 0x0001 /* Full-Speed J State */
162 #define LS_JSTS 0x0002 /* Low-Speed J State */
163 #define LS_KSTS 0x0001 /* Low-Speed K State */
171 #define USBRST 0x0040 /* b6: USB reset enable */
172 #define RESUME 0x0020 /* b5: Resume enable */
173 #define UACT 0x0010 /* b4: USB bus enable */
174 #define RHST 0x0007 /* b1-0: Reset handshake status */
176 #define HSMODE 0x0003 /* Hi-Speed mode */
177 #define FSMODE 0x0002 /* Full-Speed mode */
178 #define LSMODE 0x0001 /* Low-Speed mode */
182 #define UTST 0x000F /* b3-0: Test select */
198 #define INTA 0x0001 /* b1: USB INT-pin active */
204 #define DFORM 0x0380 /* b9-7: DMA mode select */
211 #define DENDE 0x0010 /* b4: Dend enable */
216 #define REW 0x4000 /* b14: Buffer rewind */
217 #define DCLRM 0x2000 /* b13: DMA buffer clear mode */
218 #define DREQE 0x1000 /* b12: DREQ output enable */
226 #define CURPIPE 0x000F /* b2-0: PIPE select */
229 #define BVAL 0x8000 /* b15: Buffer valid flag */
230 #define BCLR 0x4000 /* b14: Buffer clear */
232 #define DTLN 0x0FFF /* b11-0: FIFO received data length */
234 /* Interrupt Enable Register 0 */
240 #define BEMPE 0x0400 /* b10: Buffer empty interrupt */
241 #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
242 #define BRDYE 0x0100 /* b8: Buffer ready interrupt */
244 /* Interrupt Enable Register 1 */
245 #define OVRCRE 0x8000 /* b15: Over-current interrupt */
253 /* BRDY Interrupt Enable/Status Register */
265 /* NRDY Interrupt Enable/Status Register */
277 /* BEMP Interrupt Enable/Status Register */
290 #define TRNENSEL 0x0100 /* b8: Select transaction enable period */
294 #define SOFMODE 0x000C /* b3-2: SOF pin select */
305 #define BEMP 0x0400 /* b10: Buffer empty interrupt */
306 #define NRDY 0x0200 /* b9: Buffer not ready interrupt */
307 #define BRDY 0x0100 /* b8: Buffer ready interrupt */
309 #define DVSQ 0x0070 /* b6-4: Device state */
319 #define DVSQS 0x0030 /* b5-4: Device state */
321 #define CTSQ 0x0007 /* b2-0: Control transfer stage */
331 #define OVRCR 0x8000 /* b15: Over-current interrupt */
335 #define EOFERR 0x0040 /* b6: EOF-error interrupt */
342 #define FRNM 0x07FF /* b10-0: Frame number */
345 #define UFRNM 0x0007 /* b2-0: Micro frame number */
349 #define DEVSEL 0xF000 /* b15-14: Device address select */
350 #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
353 #define BSTS 0x8000 /* b15: Buffer status */
355 #define CSCLR 0x2000 /* b13: complete-split status clear */
356 #define CSSTS 0x1000 /* b12: complete-split status */
362 #define PINGE 0x0010 /* b4: ping enable */
363 #define CCPL 0x0004 /* b2: Enable control transfer complete */
364 #define PID 0x0003 /* b1-0: Response PID */
371 #define PIPENM 0x0007 /* b2-0: Pipe select */
374 #define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
378 #define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
379 #define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
383 #define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
385 /* Pipe Buffer Configuration Register */
386 #define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
387 #define BUFNMB 0x007F /* b6-0: Pipe buffer number */
392 #define MXPS 0x07FF /* b10-0: Maxpacket size */
395 #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
396 #define IITV 0x0007 /* b2-0: Isochronous interval */
399 #define BSTS 0x8000 /* b15: Buffer status */
400 #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
401 #define CSCLR 0x2000 /* b13: complete-split status clear */
402 #define CSSTS 0x1000 /* b12: complete-split status */
404 #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
409 #define PID 0x0003 /* b1-0: Response PID */
412 #define TRENB 0x0200 /* b9: Transaction counter enable */
416 #define TRNCNT 0xFFFF /* b15-0: Transaction counter */
446 #define SENDBUFM 0x1000 /* b12: Transmit Buffer Mode */
448 #define LBA_WAIT 0x0030 /* b5-4: Local Bus Access Wait */
450 /* DMA Enable Registers */
451 #define DEN 0x0001 /* b1: DMA Transfer Enable */
457 /* DMA Buffer Control Register */
458 #define CH1BUFW 0x0200 /* b9: Ch1 DMA Buffer Data Transfer Enable */
459 #define CH0BUFW 0x0100 /* b8: Ch0 DMA Buffer Data Transfer Enable */
460 #define CH1BUFS 0x0002 /* b2: Ch1 DMA Buffer Data Status */
461 #define CH0BUFS 0x0001 /* b1: Ch0 DMA Buffer Data Status */
464 #define CH1ERRE 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Enable */
465 #define CH0ERRE 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Enable */
466 #define CH1ENDE 0x0002 /* b2: Ch1 DMA Transfer End Int Enable */
467 #define CH0ENDE 0x0001 /* b1: Ch0 DMA Transfer End Int Enable */