Lines Matching +full:1 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5651.h -- RT5651 ALSA SoC audio driver
12 #include <dt-bindings/sound/rt5651.h>
19 /* I/O - Output */
23 /* I/O - Input */
28 /* I/O - ADC/DAC/DMIC */
35 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
72 /* Format - ADC/DAC */
82 /* Function - Analog */
99 /* Function - Digital */
176 #define RT5651_L_MUTE (0x1 << 15)
177 #define RT5651_L_MUTE_SFT 15
190 #define RT5651_EN_DFO (0x1 << 15)
205 #define RT5651_INL_SEL_MASK (0x1 << 15)
206 #define RT5651_INL_SEL_SFT 15
207 #define RT5651_INL_SEL_IN4P (0x0 << 15)
208 #define RT5651_INL_SEL_MONOP (0x1 << 15)
251 #define RT5651_M_MONO_ADC_L (0x1 << 15)
252 #define RT5651_M_MONO_ADC_L_SFT 15
313 #define RT5651_M_ADCMIX_L (0x1 << 15)
314 #define RT5651_M_ADCMIX_L_SFT 15
343 #define RT5651_M_DAC_L1_MIXR (0x1 << 1)
344 #define RT5651_M_DAC_L1_MIXR_SFT 1
371 #define RT5651_STO_DD_L2_R_VOL_MASK (0x1 << 1)
372 #define RT5651_STO_DD_L2_R_VOL_SFT 1
375 #define RT5651_M_STO_L_DAC_L (0x1 << 15)
376 #define RT5651_M_STO_L_DAC_L_SFT 15
392 /* DSP Path Control 1 (0x2d) */
393 #define RT5651_RXDP_SRC_MASK (0x1 << 15)
394 #define RT5651_RXDP_SRC_SFT 15
395 #define RT5651_RXDP_SRC_NOR (0x0 << 15)
396 #define RT5651_RXDP_SRC_DIV3 (0x1 << 15)
466 #define RT5651_PDM_L_SEL_MASK (0x1 << 15)
467 #define RT5651_PDM_L_SEL_SFT 15
468 #define RT5651_PDM_L_SEL_DD_L (0x0 << 15)
469 #define RT5651_PDM_L_SEL_STO_L (0x1 << 15)
488 #define RT5651_PDM_DIV_2 1
492 /* PDM I2C/Data Control 1 (0x31) */
507 /* REC Left Mixer Control 1 (0x3b) */
514 #define RT5651_G_BST2_RM_L_MASK (0x7 << 1)
515 #define RT5651_G_BST2_RM_L_SFT 1
530 #define RT5651_M_BST1_RM_L (0x1 << 1)
531 #define RT5651_M_BST1_RM_L_SFT 1
535 /* REC Right Mixer Control 1 (0x3d) */
542 #define RT5651_G_BST2_RM_R_MASK (0x7 << 1)
543 #define RT5651_G_BST2_RM_R_SFT 1
558 #define RT5651_M_BST1_RM_R (0x1 << 1)
559 #define RT5651_M_BST1_RM_R_SFT 1
590 #define RT5651_M_OM_L_SM_L (0x1 << 1)
591 #define RT5651_M_OM_L_SM_L_SFT 1
612 #define RT5651_M_OM_R_SM_R (0x1 << 1)
613 #define RT5651_M_OM_R_SM_R_SFT 1
616 #define RT5651_M_DAC_R1_SPM_L (0x1 << 15)
617 #define RT5651_M_DAC_R1_SPM_L_SFT 15
640 #define RT5651_M_DAC_R2_MM (0x1 << 15)
641 #define RT5651_M_DAC_R2_MM_SFT 15
653 /* Output Left Mixer Control 1 (0x4d) */
660 #define RT5651_G_RM_L_OM_L_MASK (0x7 << 1)
661 #define RT5651_G_RM_L_OM_L_SFT 1
683 /* Output Right Mixer Control 1 (0x50) */
690 #define RT5651_G_RM_R_OM_R_MASK (0x7 << 1)
691 #define RT5651_G_RM_R_OM_R_SFT 1
714 #define RT5651_M_DAC_L1_LM (0x1 << 15)
715 #define RT5651_M_DAC_L1_LM_SFT 15
725 /* Power Management for Digital 1 (0x61) */
726 #define RT5651_PWR_I2S1 (0x1 << 15)
727 #define RT5651_PWR_I2S1_BIT 15
736 #define RT5651_PWR_ADC_R (0x1 << 1)
737 #define RT5651_PWR_ADC_R_BIT 1
740 #define RT5651_PWR_ADC_STO1_F (0x1 << 15)
741 #define RT5651_PWR_ADC_STO1_F_BIT 15
751 /* Power Management for Analog 1 (0x63) */
752 #define RT5651_PWR_VREF1 (0x1 << 15)
753 #define RT5651_PWR_VREF1_BIT 15
776 #define RT5651_PWR_LDO_DVO_1_1V 1
781 #define RT5651_PWR_BST1 (0x1 << 15)
782 #define RT5651_PWR_BST1_BIT 15
799 #define RT5651_PWR_JD2 (0x1 << 1)
800 #define RT5651_PWM_JD2_BIT 1
805 #define RT5651_PWR_OM_L (0x1 << 15)
806 #define RT5651_PWR_OM_L_BIT 15
833 #define RT5651_I2S_MS_MASK (0x1 << 15)
834 #define RT5651_I2S_MS_SFT 15
835 #define RT5651_I2S_MS_M (0x0 << 15)
836 #define RT5651_I2S_MS_S (0x1 << 15)
864 /* ADC/DAC Clock Control 1 (0x73) */
909 #define RT5651_DMIC_1_EN_MASK (0x1 << 15)
910 #define RT5651_DMIC_1_EN_SFT 15
911 #define RT5651_DMIC_1_DIS (0x0 << 15)
912 #define RT5651_DMIC_1_EN (0x1 << 15)
929 /* TDM Control 1 (0x77) */
930 #define RT5651_TDM_INTEL_SEL_MASK (0x1 << 15)
931 #define RT5651_TDM_INTEL_SEL_SFT 15
932 #define RT5651_TDM_INTEL_SEL_64 (0x0 << 15)
933 #define RT5651_TDM_INTEL_SEL_50 (0x1 << 15)
984 #define RT5651_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
985 #define RT5651_TDM_LRCK_POL_SEL_SFT 15
986 #define RT5651_TDM_LRCK_POL_SEL_NOR (0x0 << 15)
987 #define RT5651_TDM_LRCK_POL_SEL_INV (0x1 << 15)
1079 /* PLL M/N/K Code Control 1 (0x81) */
1094 /* PLL tracking mode 1 (0x83) */
1095 #define RT5651_STO1_T_MASK (0x1 << 15)
1096 #define RT5651_STO1_T_SFT 15
1097 #define RT5651_STO1_T_SCLK (0x0 << 15)
1098 #define RT5651_STO1_T_LRCK1 (0x1 << 15)
1113 #define RT5651_STO1_ASRC_EN (0x1 << 15)
1114 #define RT5651_STO1_ASRC_EN_SFT 15
1185 /* Depop Mode Control 1 (0x8e) */
1186 #define RT5651_SMT_TRIG_MASK (0x1 << 15)
1187 #define RT5651_SMT_TRIG_SFT 15
1188 #define RT5651_SMT_TRIG_DIS (0x0 << 15)
1189 #define RT5651_SMT_TRIG_EN (0x1 << 15)
1222 #define RT5651_HP_DP_MASK (0x1 << 1)
1223 #define RT5651_HP_DP_SFT 1
1224 #define RT5651_HP_DP_PD (0x0 << 1)
1225 #define RT5651_HP_DP_PU (0x1 << 1)
1275 #define RT5651_CP_FQ_3_KHZ 1
1305 #define RT5651_MIC1_BS_MASK (0x1 << 15)
1306 #define RT5651_MIC1_BS_SFT 15
1307 #define RT5651_MIC1_BS_9AV (0x0 << 15)
1308 #define RT5651_MIC1_BS_75AV (0x1 << 15)
1331 /* Analog JD Control 1 (0x94) */
1359 /* EQ Control 1 (0xb0) */
1360 #define RT5651_EQ_SRC_MASK (0x1 << 15)
1361 #define RT5651_EQ_SRC_SFT 15
1362 #define RT5651_EQ_SRC_DAC (0x0 << 15)
1363 #define RT5651_EQ_SRC_ADC (0x1 << 15)
1388 #define RT5651_EQ_STA_BP1 (0x1 << 1)
1389 #define RT5651_EQ_STA_BP1_BIT 1
1422 #define RT5651_EQ_BPF1_MASK (0x1 << 1)
1423 #define RT5651_EQ_BPF1_SFT 1
1424 #define RT5651_EQ_BPF1_DIS (0x0 << 1)
1425 #define RT5651_EQ_BPF1_EN (0x1 << 1)
1433 #define RT5651_MT_MASK (0x1 << 15)
1434 #define RT5651_MT_SFT 15
1435 #define RT5651_MT_DIS (0x0 << 15)
1436 #define RT5651_MT_EN (0x1 << 15)
1438 /* ALC Control 1 (0xb4) */
1439 #define RT5651_ALC_P_MASK (0x1 << 15)
1440 #define RT5651_ALC_P_SFT 15
1441 #define RT5651_ALC_P_DAC (0x0 << 15)
1442 #define RT5651_ALC_P_ADC (0x1 << 15)
1494 /* Jack Detect Control 1 (0xbb) */
1552 /* IRQ Control 1 (0xbd) */
1553 #define RT5651_IRQ_JD_MASK (0x1 << 15)
1554 #define RT5651_IRQ_JD_SFT 15
1555 #define RT5651_IRQ_JD_BP (0x0 << 15)
1556 #define RT5651_IRQ_JD_NOR (0x1 << 15)
1581 #define RT5651_JD2_INV (0x1 << 1)
1582 #define RT5651_JD2_INV_SFT 1
1585 #define RT5651_IRQ_MB1_OC_MASK (0x1 << 15)
1586 #define RT5651_IRQ_MB1_OC_SFT 15
1587 #define RT5651_IRQ_MB1_OC_BP (0x0 << 15)
1588 #define RT5651_IRQ_MB1_OC_NOR (0x1 << 15)
1604 #define RT5651_STA_JD3 (0x1 << 15)
1605 #define RT5651_STA_JD3_BIT 15
1629 /* GPIO Control 1 (0xc0) */
1630 #define RT5651_GP1_PIN_MASK (0x1 << 15)
1631 #define RT5651_GP1_PIN_SFT 15
1632 #define RT5651_GP1_PIN_GPIO1 (0x0 << 15)
1633 #define RT5651_GP1_PIN_IRQ (0x1 << 15)
1720 #define RT5651_GP1_OUT_MASK (0x1 << 1)
1721 #define RT5651_GP1_OUT_SFT 1
1722 #define RT5651_GP1_OUT_LO (0x0 << 1)
1723 #define RT5651_GP1_OUT_HI (0x1 << 1)
1758 #define RT5651_GP6_OUT_MASK (0x1 << 1)
1759 #define RT5651_GP6_OUT_SFT 1
1760 #define RT5651_GP6_OUT_LO (0x0 << 1)
1761 #define RT5651_GP6_OUT_HI (0x1 << 1)
1768 #define RT5651_SCB_SWAP_MASK (0x1 << 15)
1769 #define RT5651_SCB_SWAP_SFT 15
1770 #define RT5651_SCB_SWAP_DIS (0x0 << 15)
1771 #define RT5651_SCB_SWAP_EN (0x1 << 15)
1778 #define RT5651_BB_MASK (0x1 << 15)
1779 #define RT5651_BB_SFT 15
1780 #define RT5651_BB_DIS (0x0 << 15)
1781 #define RT5651_BB_EN (0x1 << 15)
1799 /* MP3 Plus Control 1 (0xd0) */
1800 #define RT5651_M_MP3_L_MASK (0x1 << 15)
1801 #define RT5651_M_MP3_L_SFT 15
1829 /* 3D HP Control 1 (0xd2) */
1830 #define RT5651_3D_CF_MASK (0x1 << 15)
1831 #define RT5651_3D_CF_SFT 15
1832 #define RT5651_3D_CF_DIS (0x0 << 15)
1833 #define RT5651_3D_CF_EN (0x1 << 15)
1857 /* Adjustable high pass filter control 1 (0xd3) */
1858 #define RT5651_2ND_HPF_MASK (0x1 << 15)
1859 #define RT5651_2ND_HPF_SFT 15
1860 #define RT5651_2ND_HPF_DIS (0x0 << 15)
1861 #define RT5651_2ND_HPF_EN (0x1 << 15)
1918 /* Soft volume and zero cross control 1 (0xd9) */
1919 #define RT5651_SV_MASK (0x1 << 15)
1920 #define RT5651_SV_SFT 15
1921 #define RT5651_SV_DIS (0x0 << 15)
1922 #define RT5651_SV_EN (0x1 << 15)
1949 #define RT5651_ZCD_HP_MASK (0x1 << 15)
1950 #define RT5651_ZCD_HP_SFT 15
1951 #define RT5651_ZCD_HP_DIS (0x0 << 15)
1952 #define RT5651_ZCD_HP_EN (0x1 << 15)
1961 #define RT5651_AMP_DET_EN (0x1 << 1)
1962 #define RT5651_AMP_DET_EN_SFT 1
1977 #define RT5651_3D_SPK_MASK (0x1 << 15)
1978 #define RT5651_3D_SPK_SFT 15
1979 #define RT5651_3D_SPK_DIS (0x0 << 15)
1980 #define RT5651_3D_SPK_EN (0x1 << 15)
1988 /* Wind Noise Detection Control 1 (0x6c) */
1989 #define RT5651_WND_MASK (0x1 << 15)
1990 #define RT5651_WND_SFT 15
1991 #define RT5651_WND_DIS (0x0 << 15)
1992 #define RT5651_WND_EN (0x1 << 15)
2015 #define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2017 #define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */