Lines Matching +full:5 +full:gbit
690 + dmas = <&hiedmacv310_0 5 5>, <&hiedmacv310_0 4 4>;
1272 + interrupts = <0 5 4>;
2740 +CONFIG_DMA_MSG_MIN_LEN=5
5847 +CONFIG_DMA_MSG_MIN_LEN=5
9055 +CONFIG_DMA_MSG_MIN_LEN=5
11244 index 000000000..5e41d2696
12286 @@ -30,3 +30,5 @@ subdir-y += ti
12691 + (tmp >> 5) & 0x1, (tmp >> 6) & 0x1);
13399 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
13724 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6};
13729 +static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
13896 + CLK_SET_RATE_PARENT, 0x0174, 5, 0,
13965 + CLK_SET_RATE_PARENT, 0x16c, 5, 0,
13977 + CLK_SET_RATE_PARENT, 0x14c, 5, 0,
14367 +#define TIMER_CTRL_IE (1 << 5) /* VR */
14790 + u32 reserved[5];
16374 @@ -5,3 +5,4 @@
16383 @@ -5,3 +5,4 @@
17842 + .vsync_end = 960 + 3 + 5, /* 960 3 5 alg data */
17843 + .vtotal = 960 + 3 + 5 + 6, /* 960 3 5 6 alg data */
19527 index 000000000..5f247a1a9
20287 +#define DMAC_MEMORY_ADDRESS_INVALID (DMAC_ERROR_BASE + 5)
21830 +#define DMAC_MEMORY_ADDRESS_INVALID (DMAC_ERROR_BASE+5)
22901 +#define HIEDMACV310_TRACE_LEVEL 5
23212 + hisi_zone[num_zones].block_align = (uintptr_t)memparse(argv[5], NULL);
23348 + default 5
23552 + udelay(5);
23558 + udelay(5);
25052 reg_w(sd, R51x_FIFO_PSIZE, packet_size >> 5);
25272 + err = mmc_wait_for_cmd(card->host, &mmc_cmd, 5);
25496 @@ -112,3 +127,5 @@ endif
25952 + himci_trace(5, "Other CMD is running,"
26059 + himci_trace(5, "set card clk divider is failed!");
26135 + unsigned int i, curr_status, status[5];
26141 + for (i = 0; i < 5; i++) {
26466 + himci_trace(5, "The status of the card is abnormal, cmd->resp[0]: %x",
26477 + himci_trace(5, "The status of the card is abnormal, cmd->resp[0]: %x",
26646 + himci_trace(5, "wait data request complete is timeout! 0x%08X",
26882 + /* Wait for 5ms */
26885 + /* 3.3V regulator output should be stable within 5 ms */
26908 + /* Wait for 5ms */
26945 + /* Wait for 5ms */
27018 + himci_trace(5, "Devid error, host->devid: %x", host->devid);
27041 + himci_trace(5, "Devid error, host->devid: %x", host->devid);
27117 + himci_trace(5, "Devid error, host->devid: %x", host->devid);
27137 + himci_trace(5, "Devid error, host->devid: %x", host->devid);
27443 + himci_trace(5, "%s: no valid phase shift! use default",
27487 + * 5.increase the phase shift value of cclk_in_sample until the host
27577 + himci_trace(5, "%s: no valid phase shift! use default",
28177 + himci_trace(5, "mmc%d: invalid slot!\n", slot);
28287 +#define HIMCI_TRACE_LEVEL 5
28420 + unsigned int card_number : 5;
28887 +#define MAX_SPEED_MODE 5
28979 +#define CES (0x1 << 5)
29080 +/* bit 5: receive FIFO data request interrupt status */
29081 +#define RXDR_INT_STATUS (0x1<<5)
29141 +#define FOUND_EDGE (0x1 << 5)
29484 +#define MAX_SPEED_MODE 5
31164 index 4a9aed4f0..5c3e95668 100644
31215 index 000000000..5b15bc8b9
33551 + * 1.0 ESMT F50L512M41A 64MB Add 5 chip
33552 + * GD 5F1GQ4UAYIG 128MB
33553 + * GD 5F2GQ4UAYIG 256MB
33555 + * GD 5F4GQ4UAYIG 512MB
33556 + * GD 5F4GQ4UBYIG 512MB
33557 + * GD 5F1GQ4RB9IG 128MB
33558 + * GD 5F1GQ4UEYIHY 128MB
33562 + * 1.2 GD 5F1GQ4UBYIG 128MB Add 2 chip
33563 + * GD 5F2GQ4U9IGR/BYIG 256MB
33564 + * GD 1.8V 5F4GQ6RE9IG 512MB
33578 + * 2.1 Micron MT29F1G01ABA 128MB Add 5 chip
33585 + * 2.4 GD 1.8V 5F4GQ4RAYIG 512MB Add 1 chip
33586 + * 2.5 GD 1.8V 5F2GQ4RB9IGR 256MB Add 1 chip
33593 + * GD 5F1GQ4RB9IGR 128MB
33595 + * GD 1.8V 5F4GQ4RBYIG 512MB Add 1 chip
33598 + * XTX 3.3V XT26G01B 1Gbit 128MB
33604 + /* Micron MT29F1G01ABA 1GBit */
33635 + /* Micron MT29F1G01ABB 1GBit 1.8V */
33666 + /* Micron MT29F2G01ABA 2GBit */
33697 + /* Micron MT29F2G01ABB 2GBit 1.8V */
33728 + /* Micron MT29F4G01ADAG 4GBit 3.3V */
33788 + /* ESMT F50L1G41A 1Gbit */
33817 + /* GD 3.3v GD5F1GQ5UEYIGY/GD5F1GQ5UEYIGR 1Gbit */
33846 + /* ESMT F50L1G41LB-104YG2ME 1Gbit */
33875 + /* GD 3.3v GD5F1GQ4UAYIG 1Gbit */
33906 + /* GD 1.8v GD5F1GQ5REYIG 1Gbit */
33935 + /* GD 3.3v GD5F1GQ4UEYIHY 1Gbit */
33966 + /* GD 1.8v GD5F1GQ4RB9IG 1Gbit */
33997 + /* GD 3.3v GD5F1GQ4UBYIG 1Gbit */
34028 + /* GD 3.3v GD5F2GQ4UAYIG 2Gbit */
34059 + /* GD 3.3v GD5F2GQ4U9IGR/BYIG 2Gbit */
34090 + /* GD 3.3v GD5F2GQ5UEYIG 2Gbit */
34121 + /* GD 1.8v GD5F2GQ5REYIG 2Gbit */
34152 + /* GD 3.3v GD5F4GQ4UAYIG 4Gbit */
34183 + /* GD 3.3v GD5F4GQ4UBYIG 4Gbit */
34214 + /* GD 3.3v GD5F4GQ6UEYIG 4Gbit */
34245 + /* GD 1.8V GD5F1GQ4RB9IGR 1Gbit */
34276 + /* GD 1.8V GD5F2GQ4RB9IGR 2Gbit */
34306 + /* GD 1.8V 5F4GQ6RE9IG 4Gbit */
34336 + /* GD 1.8V GD5F4GQ4RAYIG 4Gbit */
34367 + /* Winbond 1.8V W25N02JWZEIF 2Gbit */
34398 + /* GD 1.8V 5F4GQ4RBYIG 4Gbit */
34400 + .name = "5F4GQ4RBYIG",
34429 + /* Winbond W25N01GV 1Gbit 3.3V */
34460 + /* Winbond W25N01GWZEIG 1Gbit 1.8V */
34491 + /* ATO ATO25D1GA 1Gbit */
34519 + /* MXIC MX35LF1GE4AB 1Gbit */
34547 + /* MXIC MX35UF1G14AC 1Gbit 1.8V */
34575 + /* MXIC MX35LF2GE4AB 2Gbit SOP-16Pin */
34603 + /* MXIC MX35LF2G14AC 2GBit */
34631 + /* MXIC MX35UF2G14AC 2Gbit 1.8V */
34659 + /* Paragon PN26G01A 1Gbit */
34690 + /* Paragon PN26G02A 2Gbit */
34721 + /* All-flash AFS1GQ4UAC 1Gbit */
34752 + /* All-flash AFS2GQ4UAD 2Gbit */
34783 + /* TOSHIBA TC58CVG0S3H 1Gbit */
34838 + /* TOSHIBA TC58CYG0S3H 1.8V 1Gbit */
34866 + /* TOSHIBA TC58CYG0S3HRAIJ 1.8V 1Gbit */
34895 + /* TOSHIBA TC58CVG1S3H 2Gbit */
34923 + /* TOSHIBA TC58CVG1S3HRAIJ 2Gbit */
34952 + /* TOSHIBA TC58CYG1S3H 1.8V 2Gbit */
34980 + /* TOSHIBA TC58CYG1S3HRAIJ 1.8V 2Gbit */
35009 + /* TOSHIBA TC58CVG2S0H 4Gbit */
35037 + /* TOSHIBA TC58CVG2S0HRAIJ 4Gbit */
35066 + /* TOSHIBA TC58CYG2S0H 1.8V 4Gbit */
35094 + /* KIOXIA TH58CYG2S0HRAIJ 1.8V 4Gbit */
35123 + /* KIOXIA TH58CYG3S0H 1.8V 8Gbit */
35152 + /* HeYangTek HYF1GQ4UAACAE 1Gbit */
35183 + /* HeYangTek HYF2GQ4UAACAE 2Gbit */
35214 + /* HeYangTek HYF4GQ4UAACBE 4Gbit */
35245 + /* Dosilicon 3.3V DS35Q1GA-IB 1Gbit */
35274 + /* XTX 3.3V XT26G01B 1Gbit */
35305 + /* Etron 1.8V EM78F044VCA-H 8Gbit */
35336 + /* Etron 1.8V EM78E044VCA-H 4Gbit */
35367 + /* Etron 1.8V EM78D044VCF-H 2Gbit */
35398 + /* Etron 3.3V EM73C044VCC-H 1Gbit */
35429 + /* Micron MT29F4G01ABBFDWB 4GBit 1.8V */
35487 + /* FM 3.3v FM25S01-DND-A-G 1Gbit */
35518 + /* FM 3.3v FM25S01A 1Gbit */
35918 + 10 nanoseconds per cycle,increasing computer performance by about 5
35977 index 000000000..5c08d4beb
37543 +#if (KERNEL_VERSION(3, 4, 5) <= LINUX_VERSION_CODE)
37641 + int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
37661 + int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
37745 + .length = 5,
37762 + .length = 5,
37777 + .length = 5,
37792 + .length = 5,
37807 + .length = 5,
37950 + .length = 5,
37964 + .length = 5,
37978 + .length = 5,
37992 + .length = 5,
38006 + .length = 5,
38065 + .length = 5,
38107 + .length = 5,
38210 + .length = 5,
38323 + .length = 5,
38500 + id[2], id[3], id[4], id[5], id[6], id[7]);
38866 +#define NAND_PAGE_16K 5
38880 +#define NAND_ECC_16BIT 5
39168 + int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
39190 + int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
39274 + .length = 5,
39289 + .length = 5,
39431 + .length = 5,
39445 + .length = 5,
39459 + .length = 5,
39473 + .length = 5,
39487 + .length = 5,
39546 + .length = 5,
39588 + .length = 5,
39691 + .length = 5,
39803 + .length = 5,
39987 + byte[4], byte[5], byte[6], byte[7]);
40397 index 5c0e0ec2e..bffa9c1a6 100644
40464 @@ -8,4 +8,5 @@ obj-$(CONFIG_HIP04_ETH) += hip04_eth.o
41547 + (ha->addr[4] << 8) | (ha->addr[5]); /* a4 << 8 | a5 */
41647 + /* mac 2 3 4 5 shift left 24 16 8 0 bits */
41648 + val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
41783 + mdelay(5); /* wait 5ms */
43834 +#define BIT_CRC_ERR_PASS BIT(5)
43860 +#define BIT_COE_PAYLOAD_DROP BIT(5)
43992 + ERR_DESC_MTU = (1 << 5), /* bit5 */
44153 + unsigned int reserve2 : 5;
44177 + unsigned int nfrags_num : 5;
44201 + unsigned int reserve2 : 5;
44230 + unsigned int nfrags_num : 5;
44535 + v |= 0x3 << 5; /* set bit5 bit6, clear irq status */
44579 + v |= 0x3 << 5; /* set bit5 bit6, clear irq status */
44602 + v |= 0x3 << 5; /* set bit5 bit6, clear irq status */
44948 +#define SIOCSETSUSPEND (SIOCDEVPRIVATE + 5) /* call dev->suspend, debug */
46043 +#define UDPV4_L4_HASH_EN BIT(5)
47244 + reg = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
47458 + val = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
48055 index 000000000..5e260ad18
48092 +#define FC_DEACTIVE_THR_MASK GENMASK(5, 0)
48109 +#define TX_CNT_INUSE_MASK GENMASK(5, 0)
48132 +#define FWCTRL_FW2CPU_ENA BIT(5)
48137 +#define MACTCTRL_BROAD2CPU BIT(5)
48208 +#define TX_FLOW_CTRL_DEACTIVE_THRESHOLD 5
48213 +#define FC_DEACTIVE_DEFAULT 5
48930 index 5c498dde4..67b74ed9d 100644
48986 +#define BIT_FEPHY_SEL BIT(5)
48990 +#define BIT_OFFSET_LDO_SET 5
49012 +#define BIT_MASK_R_TUNING GENMASK(5, 0)
49168 + /* delay 5ms after enable MDCK to make sure FEPHY trim safe */
49169 + mdelay(5);
49211 + mdelay(5);
49276 + mdelay(5);
49703 index 000000000..5eefc01e5
49816 @@ -256,5 +256,6 @@ source "drivers/pci/hotplug/Kconfig"
49827 @@ -36,5 +36,6 @@ obj-$(CONFIG_PCI_ENDPOINT) += endpoint/
51000 @@ -83,5 +83,6 @@ source "drivers/phy/tegra/Kconfig"
51053 @@ -0,0 +1,5 @@
51872 index 000000000..5e20e6e4a
51929 +#define M_LEVEL2 5
53002 +#define RTC_RW_RETRY_CNT 5
55792 index e65f474ad..5bb7ce3eb 100644
55956 + ctl_cls[5] = NULL; /* NULL-terminate */
55986 - struct uvc_descriptor_header *uvc_fs_control_cls[5];
55987 - struct uvc_descriptor_header *uvc_ss_control_cls[5];
57081 @@ -689,5 +691,19 @@ int vfio_pci_set_irqs_ioctl(struct vfio_pci_device *vdev, uint32_t flags,
57103 index fe888b5dc..5a0791e56 100644
57155 index 0791480bf..5a195dd31 100644
58051 + month = max(1, (date >> 5) & 0xf);
58058 + d_createtime[4] = ((time >> 5) & 0x3f); /*min*/
58059 + d_createtime[5] = (time & 0x1f); /*second 2s*/
58067 + d_createtime[5] += (time_cs / 100); /*second 1s*/
58076 index 5e91d578f..01116b8ea 100644
58143 +#define HI3516DV300_FIXED_50M 5
58384 + unsigned int reserved[5];
58483 +#define FMC_CFG_ECC_TYPE(_type) (((_type) & 0x7) << 5)
58517 +#define ECC_TYPE_SHIFT 5
58564 +#define FMC_INT_DMA_ERR BIT(5)
58576 +#define FMC_INT_EN_DMA_ERR BIT(5)
58586 +#define FMC_INT_CLR_DMA_ERR BIT(5)
58638 +#define PROTECT_BP2_MASK BIT(5)
58659 +#define FMC_OP_WRITE_DATA_EN BIT(5)
58904 index 40d7e98fc..5b77c8cda 100644
59263 @@ -227,5 +227,8 @@ typedef void (*swap_func_t)(void *a, void *b, int size);
59393 @@ -567,5 +569,63 @@ struct UVC_FRAME_MJPEG(n) { \
59869 index 8fb047888..5ea56bc2a 100644