35 radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned needed)  in radeon_check_space()  argument
37    if (cs->max_dw - cs->cdw < needed)  in radeon_check_space()
38       ws->cs_grow(cs, needed);  in radeon_check_space()
39    return cs->cdw + needed;  in radeon_check_space()
43 radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)  in radeon_set_config_reg_seq()  argument
46    assert(cs->cdw + 2 + num <= cs->max_dw);  in radeon_set_config_reg_seq()
48    radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));  in radeon_set_config_reg_seq()
49    radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);  in radeon_set_config_reg_seq()
53 radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)  in radeon_set_config_reg()  argument
55    radeon_set_config_reg_seq(cs, reg, 1);  in radeon_set_config_reg()
56    radeon_emit(cs, value);  in radeon_set_config_reg()
60 radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)  in radeon_set_context_reg_seq()  argument
63    assert(cs->cdw + 2 + num <= cs->max_dw);  in radeon_set_context_reg_seq()
65    radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));  in radeon_set_context_reg_seq()
66    radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);  in radeon_set_context_reg_seq()
70 radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)  in radeon_set_context_reg()  argument
72    radeon_set_context_reg_seq(cs, reg, 1);  in radeon_set_context_reg()
73    radeon_emit(cs, value);  in radeon_set_context_reg()
77 radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value)  in radeon_set_context_reg_idx()  argument
80    assert(cs->cdw + 3 <= cs->max_dw);  in radeon_set_context_reg_idx()
81    radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));  in radeon_set_context_reg_idx()
82    radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));  in radeon_set_context_reg_idx()
83    radeon_emit(cs, value);  in radeon_set_context_reg_idx()
87 radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned mask)  in radeon_set_context_reg_rmw()  argument
90    assert(cs->cdw + 4 <= cs->max_dw);  in radeon_set_context_reg_rmw()
91    radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0));  in radeon_set_context_reg_rmw()
92    radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);  in radeon_set_context_reg_rmw()
93    radeon_emit(cs, mask);  in radeon_set_context_reg_rmw()
94    radeon_emit(cs, value);  in radeon_set_context_reg_rmw()
98 radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)  in radeon_set_sh_reg_seq()  argument
101    assert(cs->cdw + 2 + num <= cs->max_dw);  in radeon_set_sh_reg_seq()
103    radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));  in radeon_set_sh_reg_seq()
104    radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);  in radeon_set_sh_reg_seq()
108 radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)  in radeon_set_sh_reg()  argument
110    radeon_set_sh_reg_seq(cs, reg, 1);  in radeon_set_sh_reg()
111    radeon_emit(cs, value);  in radeon_set_sh_reg()
115 radeon_set_sh_reg_idx(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs,  in radeon_set_sh_reg_idx()  argument
119    assert(cs->cdw + 3 <= cs->max_dw);  in radeon_set_sh_reg_idx()
126    radeon_emit(cs, PKT3(opcode, 1, 0));  in radeon_set_sh_reg_idx()
127    radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (idx << 28));  in radeon_set_sh_reg_idx()
128    radeon_emit(cs, value);  in radeon_set_sh_reg_idx()
132 radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)  in radeon_set_uconfig_reg_seq()  argument
135    assert(cs->cdw + 2 + num <= cs->max_dw);  in radeon_set_uconfig_reg_seq()
137    radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));  in radeon_set_uconfig_reg_seq()
138    radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);  in radeon_set_uconfig_reg_seq()
142 radeon_set_uconfig_reg_seq_perfctr(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)  in radeon_set_uconfig_reg_seq_perfctr()  argument
145    assert(cs->cdw + 2 + num <= cs->max_dw);  in radeon_set_uconfig_reg_seq_perfctr()
147    radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 1));  in radeon_set_uconfig_reg_seq_perfctr()
148    radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);  in radeon_set_uconfig_reg_seq_perfctr()
152 radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)  in radeon_set_uconfig_reg()  argument
154    radeon_set_uconfig_reg_seq(cs, reg, 1);  in radeon_set_uconfig_reg()
155    radeon_emit(cs, value);  in radeon_set_uconfig_reg()
159 radeon_set_uconfig_reg_idx(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs,  in radeon_set_uconfig_reg_idx()  argument
163    assert(cs->cdw + 3 <= cs->max_dw);  in radeon_set_uconfig_reg_idx()
171    radeon_emit(cs, PKT3(opcode, 1, 0));  in radeon_set_uconfig_reg_idx()
172    radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));  in radeon_set_uconfig_reg_idx()
173    radeon_emit(cs, value);  in radeon_set_uconfig_reg_idx()
177 radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)  in radeon_set_privileged_config_reg()  argument
180    assert(cs->cdw + 6 <= cs->max_dw);  in radeon_set_privileged_config_reg()
182    radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));  in radeon_set_privileged_config_reg()
183    radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) | COPY_DATA_DST_SEL(COPY_DATA_PERF));  in radeon_set_privileged_config_reg()
184    radeon_emit(cs, value);  in radeon_set_privileged_config_reg()
185    radeon_emit(cs, 0); /* unused */  in radeon_set_privileged_config_reg()
186    radeon_emit(cs, reg >> 2);  in radeon_set_privileged_config_reg()
187    radeon_emit(cs, 0); /* unused */  in radeon_set_privileged_config_reg()