Lines Matching full:image
86 /* Do not enable TC-compatible HTILE if the image isn't readable by a in radv_use_tc_compat_htile_for_image()
128 const struct radv_image *image) in radv_image_use_fast_clear_for_image_early() argument
133 if (image->info.samples <= 1 && image->info.width * image->info.height <= 512 * 512) { in radv_image_use_fast_clear_for_image_early()
136 * clear. RadeonSI does this, but the image threshold is in radv_image_use_fast_clear_for_image_early()
142 return !!(image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT); in radv_image_use_fast_clear_for_image_early()
147 const struct radv_image *image) in radv_image_use_fast_clear_for_image() argument
152 return radv_image_use_fast_clear_for_image_early(device, image) && in radv_image_use_fast_clear_for_image()
153 (image->exclusive || in radv_image_use_fast_clear_for_image()
158 radv_image_use_dcc_image_stores(device, image)); in radv_image_use_fast_clear_for_image()
232 radv_use_dcc_for_image_early(struct radv_device *device, struct radv_image *image, in radv_use_dcc_for_image_early() argument
243 if (image->shareable && image->tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) in radv_use_dcc_for_image_early()
268 if (!radv_image_use_fast_clear_for_image_early(device, image) && in radv_use_dcc_for_image_early()
269 image->tiling != VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) in radv_use_dcc_for_image_early()
292 radv_use_dcc_for_image_late(struct radv_device *device, struct radv_image *image) in radv_use_dcc_for_image_late() argument
294 if (!radv_image_has_dcc(image)) in radv_use_dcc_for_image_late()
297 if (image->tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) in radv_use_dcc_for_image_late()
300 if (!radv_image_use_fast_clear_for_image(device, image)) in radv_use_dcc_for_image_late()
303 /* TODO: Fix storage images with DCC without DCC image stores. in radv_use_dcc_for_image_late()
305 …if ((image->usage & VK_IMAGE_USAGE_STORAGE_BIT) && !radv_image_use_dcc_image_stores(device, image)) in radv_use_dcc_for_image_late()
312 * Whether to enable image stores with DCC compression for this image. If
313 * this function returns false the image subresource should be decompressed
314 * before using it with image stores.
319 * This function assumes the image uses DCC compression.
322 radv_image_use_dcc_image_stores(const struct radv_device *device, const struct radv_image *image) in radv_image_use_dcc_image_stores() argument
325 &image->planes[0].surface); in radv_image_use_dcc_image_stores()
330 * state. This can be used to avoid decompressing an image multiple times.
333 radv_image_use_dcc_predication(const struct radv_device *device, const struct radv_image *image) in radv_image_use_dcc_predication() argument
335 return radv_image_has_dcc(image) && !radv_image_use_dcc_image_stores(device, image); in radv_image_use_dcc_predication()
339 radv_use_fmask_for_image(const struct radv_device *device, const struct radv_image *image) in radv_use_fmask_for_image() argument
341 return image->info.samples > 1 && ((image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) || in radv_use_fmask_for_image()
346 radv_use_htile_for_image(const struct radv_device *device, const struct radv_image *image) in radv_use_htile_for_image() argument
353 image->info.array_size == 1 && device->physical_device->rad_info.chip_class >= GFX10; in radv_use_htile_for_image()
357 image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT && image->info.levels > 1) in radv_use_htile_for_image()
363 if (image->info.width * image->info.height < 8 * 8 && in radv_use_htile_for_image()
368 return (image->info.levels == 1 || use_htile_for_mips) && !image->shareable; in radv_use_htile_for_image()
372 radv_use_tc_compat_cmask_for_image(struct radv_device *device, struct radv_image *image) in radv_use_tc_compat_cmask_for_image() argument
381 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT) in radv_use_tc_compat_cmask_for_image()
384 /* Do not enable TC-compatible if the image isn't readable by a shader in radv_use_tc_compat_cmask_for_image()
387 if (!(image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT | in radv_use_tc_compat_cmask_for_image()
391 /* If the image doesn't have FMASK, it can't be fetchable. */ in radv_use_tc_compat_cmask_for_image()
392 if (!radv_image_has_fmask(image)) in radv_use_tc_compat_cmask_for_image()
447 radv_patch_image_dimensions(struct radv_device *device, struct radv_image *image, in radv_patch_image_dimensions() argument
451 unsigned width = image->info.width; in radv_patch_image_dimensions()
452 unsigned height = image->info.height; in radv_patch_image_dimensions()
474 if (image->info.width == width && image->info.height == height) in radv_patch_image_dimensions()
477 if (width < image->info.width || height < image->info.height) { in radv_patch_image_dimensions()
479 "The imported image has smaller dimensions than the internal\n" in radv_patch_image_dimensions()
483 image->info.width, image->info.height, width, height); in radv_patch_image_dimensions()
487 "Tried to import an image with inconsistent width on GFX10.\n" in radv_patch_image_dimensions()
491 image->info.width, image->info.height, width, height); in radv_patch_image_dimensions()
495 "Tried to import an image with inconsistent width on pre-GFX10.\n" in radv_patch_image_dimensions()
499 image->info.width, image->info.height, width, height); in radv_patch_image_dimensions()
508 radv_patch_image_from_extra_info(struct radv_device *device, struct radv_image *image, in radv_patch_image_from_extra_info() argument
512 VkResult result = radv_patch_image_dimensions(device, image, create_info, image_info); in radv_patch_image_from_extra_info()
516 for (unsigned plane = 0; plane < image->plane_count; ++plane) { in radv_patch_image_from_extra_info()
518 radv_patch_surface_from_metadata(device, &image->planes[plane].surface, in radv_patch_image_from_extra_info()
523 image->planes[plane].surface.flags |= RADEON_SURF_SCANOUT; in radv_patch_image_from_extra_info()
525 image->planes[plane].surface.flags |= RADEON_SURF_DISABLE_DCC; in radv_patch_image_from_extra_info()
527 image->info.surf_index = NULL; in radv_patch_image_from_extra_info()
534 radv_get_surface_flags(struct radv_device *device, struct radv_image *image, unsigned plane_id, in radv_get_surface_flags() argument
565 unreachable("unhandled image type"); in radv_get_surface_flags()
574 if (radv_use_htile_for_image(device, image) && in radv_get_surface_flags()
591 if (!radv_use_dcc_for_image_early(device, image, pCreateInfo, image_format, in radv_get_surface_flags()
592 &image->dcc_sign_reinterpret)) in radv_get_surface_flags()
595 if (!radv_use_fmask_for_image(device, image)) in radv_get_surface_flags()
720 si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *image, in si_set_mutable_tex_desc_fields() argument
726 struct radv_image_plane *plane = &image->planes[plane_id]; in si_set_mutable_tex_desc_fields()
727 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0; in si_set_mutable_tex_desc_fields()
748 if (!disable_compression && radv_dcc_enabled(image, first_level)) { in si_set_mutable_tex_desc_fields()
756 } else if (!disable_compression && radv_image_is_tc_compat_htile(image)) { in si_set_mutable_tex_desc_fields()
787 if (radv_dcc_enabled(image, first_level) && is_storage_image && enable_write_compression) in si_set_mutable_tex_desc_fields()
858 unreachable("illegal image type"); in radv_tex_dim()
906 gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *image, in gfx10_make_texture_descriptor() argument
923 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples, in gfx10_make_texture_descriptor()
927 depth = image->info.array_size; in gfx10_make_texture_descriptor()
930 depth = image->info.array_size; in gfx10_make_texture_descriptor()
932 depth = image->info.array_size / 6; in gfx10_make_texture_descriptor()
942 S_00A00C_BASE_LEVEL(image->info.samples > 1 ? 0 : first_level) | in gfx10_make_texture_descriptor()
943 S_00A00C_LAST_LEVEL(image->info.samples > 1 ? util_logbase2(image->info.samples) in gfx10_make_texture_descriptor()
952 S_00A014_MAX_MIP(image->info.samples > 1 ? util_logbase2(image->info.samples) in gfx10_make_texture_descriptor()
953 : image->info.levels - 1) | in gfx10_make_texture_descriptor()
958 if (radv_dcc_enabled(image, first_level)) { in gfx10_make_texture_descriptor()
961 image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size) | in gfx10_make_texture_descriptor()
965 if (radv_image_get_iterate256(device, image)) { in gfx10_make_texture_descriptor()
971 if (radv_image_has_fmask(image)) { in gfx10_make_texture_descriptor()
972 uint64_t gpu_address = radv_buffer_get_va(image->bo); in gfx10_make_texture_descriptor()
976 assert(image->plane_count == 1); in gfx10_make_texture_descriptor()
978 va = gpu_address + image->offset + image->planes[0].surface.fmask_offset; in gfx10_make_texture_descriptor()
980 switch (image->info.samples) { in gfx10_make_texture_descriptor()
994 fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle; in gfx10_make_texture_descriptor()
1002 S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode) | in gfx10_make_texture_descriptor()
1004 radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false)); in gfx10_make_texture_descriptor()
1010 if (radv_image_is_tc_compat_cmask(image)) { in gfx10_make_texture_descriptor()
1011 va = gpu_address + image->offset + image->planes[0].surface.cmask_offset; in gfx10_make_texture_descriptor()
1026 si_make_texture_descriptor(struct radv_device *device, struct radv_image *image, in si_make_texture_descriptor() argument
1056 radv_image_is_tc_compat_htile(image)) { in si_make_texture_descriptor()
1057 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT) in si_make_texture_descriptor()
1059 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT) in si_make_texture_descriptor()
1062 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples, in si_make_texture_descriptor()
1066 depth = image->info.array_size; in si_make_texture_descriptor()
1069 depth = image->info.array_size; in si_make_texture_descriptor()
1071 depth = image->info.array_size / 6; in si_make_texture_descriptor()
1080 S_008F1C_BASE_LEVEL(image->info.samples > 1 ? 0 : first_level) | in si_make_texture_descriptor()
1081 S_008F1C_LAST_LEVEL(image->info.samples > 1 ? util_logbase2(image->info.samples) in si_make_texture_descriptor()
1101 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ? util_logbase2(image->info.samples) in si_make_texture_descriptor()
1102 : image->info.levels - 1); in si_make_texture_descriptor()
1104 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1); in si_make_texture_descriptor()
1108 if (!(image->planes[0].surface.flags & RADEON_SURF_Z_OR_SBUFFER) && in si_make_texture_descriptor()
1109 image->planes[0].surface.meta_offset) { in si_make_texture_descriptor()
1115 if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) { in si_make_texture_descriptor()
1125 if (radv_image_has_fmask(image)) { in si_make_texture_descriptor()
1127 uint64_t gpu_address = radv_buffer_get_va(image->bo); in si_make_texture_descriptor()
1130 assert(image->plane_count == 1); in si_make_texture_descriptor()
1132 va = gpu_address + image->offset + image->planes[0].surface.fmask_offset; in si_make_texture_descriptor()
1136 switch (image->info.samples) { in si_make_texture_descriptor()
1150 switch (image->info.samples) { in si_make_texture_descriptor()
1168 fmask_state[0] |= image->planes[0].surface.fmask_tile_swizzle; in si_make_texture_descriptor()
1176 radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false)); in si_make_texture_descriptor()
1183 … fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode); in si_make_texture_descriptor()
1185 S_008F20_PITCH(image->planes[0].surface.u.gfx9.color.fmask_epitch); in si_make_texture_descriptor()
1188 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1189 va = gpu_address + image->offset + image->planes[0].surface.cmask_offset; in si_make_texture_descriptor()
1197 S_008F1C_TILING_INDEX(image->planes[0].surface.u.legacy.color.fmask.tiling_index); in si_make_texture_descriptor()
1200 S_008F20_PITCH(image->planes[0].surface.u.legacy.color.fmask.pitch_in_pixels - 1); in si_make_texture_descriptor()
1203 if (radv_image_is_tc_compat_cmask(image)) { in si_make_texture_descriptor()
1204 va = gpu_address + image->offset + image->planes[0].surface.cmask_offset; in si_make_texture_descriptor()
1216 radv_make_texture_descriptor(struct radv_device *device, struct radv_image *image, in radv_make_texture_descriptor() argument
1224 gfx10_make_texture_descriptor(device, image, is_storage_image, view_type, vk_format, mapping, in radv_make_texture_descriptor()
1228 si_make_texture_descriptor(device, image, is_storage_image, view_type, vk_format, mapping, in radv_make_texture_descriptor()
1235 radv_query_opaque_metadata(struct radv_device *device, struct radv_image *image, in radv_query_opaque_metadata() argument
1241 assert(image->plane_count == 1); in radv_query_opaque_metadata()
1243 radv_make_texture_descriptor(device, image, false, (VkImageViewType)image->type, in radv_query_opaque_metadata()
1244 image->vk_format, &fixedmapping, 0, image->info.levels - 1, 0, in radv_query_opaque_metadata()
1245 image->info.array_size - 1, image->info.width, image->info.height, in radv_query_opaque_metadata()
1246 image->info.depth, desc, NULL); in radv_query_opaque_metadata()
1248 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, in radv_query_opaque_metadata()
1249 0, image->planes[0].surface.blk_w, false, false, false, false, in radv_query_opaque_metadata()
1252 ac_surface_get_umd_metadata(&device->physical_device->rad_info, &image->planes[0].surface, in radv_query_opaque_metadata()
1253 image->info.levels, desc, &md->size_metadata, md->metadata); in radv_query_opaque_metadata()
1257 radv_init_metadata(struct radv_device *device, struct radv_image *image, in radv_init_metadata() argument
1260 struct radeon_surf *surface = &image->planes[0].surface; in radv_init_metadata()
1266 image->offset + in radv_init_metadata()
1292 radv_query_opaque_metadata(device, image, metadata); in radv_init_metadata()
1296 radv_image_override_offset_stride(struct radv_device *device, struct radv_image *image, in radv_image_override_offset_stride() argument
1299 ac_surface_override_offset_stride(&device->physical_device->rad_info, &image->planes[0].surface, in radv_image_override_offset_stride()
1300 image->info.levels, offset, stride); in radv_image_override_offset_stride()
1305 const struct radv_image *image, struct radeon_surf *surf) in radv_image_alloc_single_sample_cmask() argument
1307 if (!surf->cmask_size || surf->cmask_offset || surf->bpe > 8 || image->info.levels > 1 || in radv_image_alloc_single_sample_cmask()
1308 image->info.depth > 1 || radv_image_has_dcc(image) || in radv_image_alloc_single_sample_cmask()
1309 !radv_image_use_fast_clear_for_image(device, image) || in radv_image_alloc_single_sample_cmask()
1310 (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)) in radv_image_alloc_single_sample_cmask()
1313 assert(image->info.storage_samples == 1); in radv_image_alloc_single_sample_cmask()
1321 radv_image_alloc_values(const struct radv_device *device, struct radv_image *image) in radv_image_alloc_values() argument
1324 if (image->tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) in radv_image_alloc_values()
1327 …if (radv_image_has_cmask(image) || (radv_image_has_dcc(image) && !image->support_comp_to_single)) { in radv_image_alloc_values()
1328 image->fce_pred_offset = image->size; in radv_image_alloc_values()
1329 image->size += 8 * image->info.levels; in radv_image_alloc_values()
1332 if (radv_image_use_dcc_predication(device, image)) { in radv_image_alloc_values()
1333 image->dcc_pred_offset = image->size; in radv_image_alloc_values()
1334 image->size += 8 * image->info.levels; in radv_image_alloc_values()
1337 if ((radv_image_has_dcc(image) && !image->support_comp_to_single) || in radv_image_alloc_values()
1338 radv_image_has_cmask(image) || radv_image_has_htile(image)) { in radv_image_alloc_values()
1339 image->clear_value_offset = image->size; in radv_image_alloc_values()
1340 image->size += 8 * image->info.levels; in radv_image_alloc_values()
1343 if (radv_image_is_tc_compat_htile(image) && in radv_image_alloc_values()
1349 image->tc_compat_zrange_offset = image->size; in radv_image_alloc_values()
1350 image->size += image->info.levels * 4; in radv_image_alloc_values()
1354 /* Determine if the image is affected by the pipe misaligned metadata issue
1358 radv_image_is_pipe_misaligned(const struct radv_device *device, const struct radv_image *image) in radv_image_is_pipe_misaligned() argument
1361 int log2_samples = util_logbase2(image->info.samples); in radv_image_is_pipe_misaligned()
1365 for (unsigned i = 0; i < image->plane_count; ++i) { in radv_image_is_pipe_misaligned()
1366 VkFormat fmt = vk_format_get_plane_format(image->vk_format, i); in radv_image_is_pipe_misaligned()
1373 if (vk_format_has_depth(image->vk_format) && image->info.array_size >= 8) { in radv_image_is_pipe_misaligned()
1383 if (vk_format_has_depth(image->vk_format)) { in radv_image_is_pipe_misaligned()
1384 if (radv_image_is_tc_compat_htile(image) && overlap) { in radv_image_is_pipe_misaligned()
1392 /* TODO: It shouldn't be necessary if the image has DCC but in radv_image_is_pipe_misaligned()
1395 if ((radv_image_has_dcc(image) || radv_image_is_tc_compat_cmask(image)) && in radv_image_is_pipe_misaligned()
1406 radv_image_is_l2_coherent(const struct radv_device *device, const struct radv_image *image) in radv_image_is_l2_coherent() argument
1410 !radv_image_is_pipe_misaligned(device, image); in radv_image_is_l2_coherent()
1412 if (image->info.samples == 1 && in radv_image_is_l2_coherent()
1413 (image->usage & in radv_image_is_l2_coherent()
1415 !vk_format_has_stencil(image->vk_format)) { in radv_image_is_l2_coherent()
1428 * Determine if the given image can be fast cleared.
1431 radv_image_can_fast_clear(const struct radv_device *device, const struct radv_image *image) in radv_image_can_fast_clear() argument
1436 if (vk_format_is_color(image->vk_format)) { in radv_image_can_fast_clear()
1437 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image)) in radv_image_can_fast_clear()
1441 if (!radv_image_has_dcc(image) && device->physical_device->rad_info.family == CHIP_STONEY) in radv_image_can_fast_clear()
1444 if (!radv_image_has_htile(image)) in radv_image_can_fast_clear()
1449 if (image->type == VK_IMAGE_TYPE_3D) in radv_image_can_fast_clear()
1456 * Determine if the given image can be fast cleared using comp-to-single.
1459 radv_image_use_comp_to_single(const struct radv_device *device, const struct radv_image *image) in radv_image_use_comp_to_single() argument
1465 /* If the image can't be fast cleared, comp-to-single can't be used. */ in radv_image_use_comp_to_single()
1466 if (!radv_image_can_fast_clear(device, image)) in radv_image_use_comp_to_single()
1469 /* If the image doesn't have DCC, it can't be fast cleared using comp-to-single */ in radv_image_use_comp_to_single()
1470 if (!radv_image_has_dcc(image)) in radv_image_use_comp_to_single()
1474 unsigned bytes_per_pixel = vk_format_get_blocksize(image->vk_format); in radv_image_use_comp_to_single()
1482 radv_image_reset_layout(struct radv_image *image) in radv_image_reset_layout() argument
1484 image->size = 0; in radv_image_reset_layout()
1485 image->alignment = 1; in radv_image_reset_layout()
1487 image->tc_compatible_cmask = 0; in radv_image_reset_layout()
1488 image->fce_pred_offset = image->dcc_pred_offset = 0; in radv_image_reset_layout()
1489 image->clear_value_offset = image->tc_compat_zrange_offset = 0; in radv_image_reset_layout()
1491 for (unsigned i = 0; i < image->plane_count; ++i) { in radv_image_reset_layout()
1492 VkFormat format = vk_format_get_plane_format(image->vk_format, i); in radv_image_reset_layout()
1496 uint64_t flags = image->planes[i].surface.flags; in radv_image_reset_layout()
1497 uint64_t modifier = image->planes[i].surface.modifier; in radv_image_reset_layout()
1498 memset(image->planes + i, 0, sizeof(image->planes[i])); in radv_image_reset_layout()
1500 image->planes[i].surface.flags = flags; in radv_image_reset_layout()
1501 image->planes[i].surface.modifier = modifier; in radv_image_reset_layout()
1502 image->planes[i].surface.blk_w = vk_format_get_blockwidth(format); in radv_image_reset_layout()
1503 image->planes[i].surface.blk_h = vk_format_get_blockheight(format); in radv_image_reset_layout()
1504 image->planes[i].surface.bpe = vk_format_get_blocksize(format); in radv_image_reset_layout()
1507 if (image->planes[i].surface.bpe == 3) { in radv_image_reset_layout()
1508 image->planes[i].surface.bpe = 4; in radv_image_reset_layout()
1516 struct radv_image *image) in radv_image_create_layout() argument
1522 struct ac_surf_info image_info = image->info; in radv_image_create_layout()
1523 VkResult result = radv_patch_image_from_extra_info(device, image, &create_info, &image_info); in radv_image_create_layout()
1527 assert(!mod_info || mod_info->drmFormatModifierPlaneCount >= image->plane_count); in radv_image_create_layout()
1529 radv_image_reset_layout(image); in radv_image_create_layout()
1531 for (unsigned plane = 0; plane < image->plane_count; ++plane) { in radv_image_create_layout()
1536 info.width = vk_format_get_plane_width(image->vk_format, plane, info.width); in radv_image_create_layout()
1537 info.height = vk_format_get_plane_height(image->vk_format, plane, info.height); in radv_image_create_layout()
1539 if (create_info.no_metadata_planes || image->plane_count > 1) { in radv_image_create_layout()
1540 image->planes[plane].surface.flags |= in radv_image_create_layout()
1544 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface); in radv_image_create_layout()
1547 if (!radv_use_dcc_for_image_late(device, image)) in radv_image_create_layout()
1548 ac_surface_zero_dcc_fields(&image->planes[0].surface); in radv_image_create_layout()
1553 &image->planes[plane].surface, image_info.storage_samples, in radv_image_create_layout()
1558 if (!create_info.no_metadata_planes && !create_info.bo_metadata && image->plane_count == 1 && in radv_image_create_layout()
1560 radv_image_alloc_single_sample_cmask(device, image, &image->planes[plane].surface); in radv_image_create_layout()
1563 if (mod_info->pPlaneLayouts[plane].rowPitch % image->planes[plane].surface.bpe || in radv_image_create_layout()
1568 stride = mod_info->pPlaneLayouts[plane].rowPitch / image->planes[plane].surface.bpe; in radv_image_create_layout()
1570 offset = align64(image->size, 1 << image->planes[plane].surface.alignment_log2); in radv_image_create_layout()
1575 &image->planes[plane].surface, image->info.levels, in radv_image_create_layout()
1580 if (image->plane_count == 1 && mod_info) { in radv_image_create_layout()
1581 unsigned mem_planes = ac_surface_get_nplanes(&image->planes[plane].surface); in radv_image_create_layout()
1587 &image->planes[plane].surface, i, in radv_image_create_layout()
1593 image->size = MAX2(image->size, offset + image->planes[plane].surface.total_size); in radv_image_create_layout()
1594 image->alignment = MAX2(image->alignment, 1 << image->planes[plane].surface.alignment_log2); in radv_image_create_layout()
1596 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane); in radv_image_create_layout()
1599 image->tc_compatible_cmask = in radv_image_create_layout()
1600 radv_image_has_cmask(image) && radv_use_tc_compat_cmask_for_image(device, image); in radv_image_create_layout()
1602 image->l2_coherent = radv_image_is_l2_coherent(device, image); in radv_image_create_layout()
1604 image->support_comp_to_single = radv_image_use_comp_to_single(device, image); in radv_image_create_layout()
1606 radv_image_alloc_values(device, image); in radv_image_create_layout()
1608 assert(image->planes[0].surface.surf_size); in radv_image_create_layout()
1609 assert(image->planes[0].surface.modifier == DRM_FORMAT_MOD_INVALID || in radv_image_create_layout()
1610 ac_modifier_has_dcc(image->planes[0].surface.modifier) == radv_image_has_dcc(image)); in radv_image_create_layout()
1616 struct radv_image *image) in radv_destroy_image() argument
1618 if ((image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) && image->bo) in radv_destroy_image()
1619 device->ws->buffer_destroy(device->ws, image->bo); in radv_destroy_image()
1621 if (image->owned_memory != VK_NULL_HANDLE) { in radv_destroy_image()
1622 RADV_FROM_HANDLE(radv_device_memory, mem, image->owned_memory); in radv_destroy_image()
1626 vk_object_base_finish(&image->base); in radv_destroy_image()
1627 vk_free2(&device->vk.alloc, pAllocator, image); in radv_destroy_image()
1631 radv_image_print_info(struct radv_device *device, struct radv_image *image) in radv_image_print_info() argument
1633 fprintf(stderr, "Image:\n"); in radv_image_print_info()
1638 image->size, image->alignment, image->info.width, image->info.height, image->offset, in radv_image_print_info()
1639 image->info.array_size); in radv_image_print_info()
1640 for (unsigned i = 0; i < image->plane_count; ++i) { in radv_image_print_info()
1641 const struct radv_image_plane *plane = &image->planes[i]; in radv_image_print_info()
1699 struct radv_image *image = NULL; in radv_image_create() local
1708 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count; in radv_image_create()
1717 image = in radv_image_create()
1719 if (!image) in radv_image_create()
1722 vk_object_base_init(&device->vk, &image->base, VK_OBJECT_TYPE_IMAGE); in radv_image_create()
1724 image->type = pCreateInfo->imageType; in radv_image_create()
1725 image->info.width = pCreateInfo->extent.width; in radv_image_create()
1726 image->info.height = pCreateInfo->extent.height; in radv_image_create()
1727 image->info.depth = pCreateInfo->extent.depth; in radv_image_create()
1728 image->info.samples = pCreateInfo->samples; in radv_image_create()
1729 image->info.storage_samples = pCreateInfo->samples; in radv_image_create()
1730 image->info.array_size = pCreateInfo->arrayLayers; in radv_image_create()
1731 image->info.levels = pCreateInfo->mipLevels; in radv_image_create()
1732 image->info.num_channels = vk_format_get_nr_components(format); in radv_image_create()
1734 image->vk_format = format; in radv_image_create()
1735 image->tiling = pCreateInfo->tiling; in radv_image_create()
1736 image->usage = pCreateInfo->usage; in radv_image_create()
1737 image->flags = pCreateInfo->flags; in radv_image_create()
1738 image->plane_count = plane_count; in radv_image_create()
1740 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE; in radv_image_create()
1745 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u; in radv_image_create()
1747 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i]; in radv_image_create()
1753 image->shareable = external_info; in radv_image_create()
1754 if (!vk_format_is_depth_or_stencil(format) && !image->shareable && in radv_image_create()
1755 !(image->flags & VK_IMAGE_CREATE_SPARSE_ALIASED_BIT) && in radv_image_create()
1757 image->info.surf_index = &device->image_mrt_offset_counter; in radv_image_create()
1765 for (unsigned plane = 0; plane < image->plane_count; ++plane) { in radv_image_create()
1766 image->planes[plane].surface.flags = in radv_image_create()
1767 radv_get_surface_flags(device, image, plane, pCreateInfo, format); in radv_image_create()
1768 image->planes[plane].surface.modifier = modifier; in radv_image_create()
1776 *pImage = radv_image_to_handle(image); in radv_image_create()
1777 assert(!(image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)); in radv_image_create()
1781 VkResult result = radv_image_create_layout(device, *create_info, explicit_mod, image); in radv_image_create()
1783 radv_destroy_image(device, alloc, image); in radv_image_create()
1787 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) { in radv_image_create()
1788 image->alignment = MAX2(image->alignment, 4096); in radv_image_create()
1789 image->size = align64(image->size, image->alignment); in radv_image_create()
1790 image->offset = 0; in radv_image_create()
1793 device->ws->buffer_create(device->ws, image->size, image->alignment, 0, in radv_image_create()
1794 RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL, 0, &image->bo); in radv_image_create()
1796 radv_destroy_image(device, alloc, image); in radv_image_create()
1802 radv_image_print_info(device, image); in radv_image_create()
1805 *pImage = radv_image_to_handle(image); in radv_image_create()
1817 struct radv_image *image = iview->image; in radv_image_view_make_descriptor() local
1818 struct radv_image_plane *plane = &image->planes[plane_id]; in radv_image_view_make_descriptor()
1838 device, image, is_storage_image, iview->type, vk_format, components, hw_level, in radv_image_view_make_descriptor()
1841 vk_format_get_plane_width(image->vk_format, plane_id, iview->extent.width), in radv_image_view_make_descriptor()
1842 vk_format_get_plane_height(image->vk_format, plane_id, iview->extent.height), in radv_image_view_make_descriptor()
1854 bool enable_write_compression = radv_image_use_dcc_image_stores(device, image); in radv_image_view_make_descriptor()
1857 si_set_mutable_tex_desc_fields(device, image, base_level_info, plane_id, iview->base_mip, in radv_image_view_make_descriptor()
1881 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask) in radv_get_aspect_format() argument
1885 return image->planes[0].format; in radv_get_aspect_format()
1887 return image->planes[1].format; in radv_get_aspect_format()
1889 return image->planes[2].format; in radv_get_aspect_format()
1891 return vk_format_stencil_only(image->vk_format); in radv_get_aspect_format()
1893 return vk_format_depth_only(image->vk_format); in radv_get_aspect_format()
1895 return vk_format_depth_only(image->vk_format); in radv_get_aspect_format()
1897 return image->vk_format; in radv_get_aspect_format()
1902 * Determine if the given image view can be fast cleared.
1908 struct radv_image *image; in radv_image_view_can_fast_clear() local
1912 image = iview->image; in radv_image_view_can_fast_clear()
1914 /* Only fast clear if the image itself can be fast cleared. */ in radv_image_view_can_fast_clear()
1915 if (!radv_image_can_fast_clear(device, image)) in radv_image_view_can_fast_clear()
1919 if (iview->base_layer > 0 || iview->layer_count != image->info.array_size) in radv_image_view_can_fast_clear()
1922 /* Only fast clear if the view covers the whole image. */ in radv_image_view_can_fast_clear()
1923 if (!radv_image_extent_compare(image, &iview->extent)) in radv_image_view_can_fast_clear()
1934 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image); in radv_image_view_init()
1940 switch (image->type) { in radv_image_view_init()
1943 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= in radv_image_view_init()
1944 image->info.array_size); in radv_image_view_init()
1947 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= in radv_image_view_init()
1948 radv_minify(image->info.depth, range->baseMipLevel)); in radv_image_view_init()
1953 iview->image = image; in radv_image_view_init()
1958 iview->layer_count = radv_get_layerCount(image, range); in radv_image_view_init()
1960 iview->level_count = radv_get_levelCount(image, range); in radv_image_view_init()
1964 /* If the image has an Android external format, pCreateInfo->format will be in radv_image_view_init()
1967 iview->vk_format = image->vk_format; in radv_image_view_init()
1982 .width = image->info.width, in radv_image_view_init()
1983 .height = image->info.height, in radv_image_view_init()
1984 .depth = image->info.depth, in radv_image_view_init()
1988 .width = radv_minify(image->info.width, range->baseMipLevel), in radv_image_view_init()
1989 .height = radv_minify(image->info.height, range->baseMipLevel), in radv_image_view_init()
1990 .depth = radv_minify(image->info.depth, range->baseMipLevel), in radv_image_view_init()
1994 if (iview->vk_format != image->planes[iview->plane_id].format) { in radv_image_view_init()
1997 unsigned img_bw = vk_format_get_blockwidth(image->vk_format); in radv_image_view_init()
1998 unsigned img_bh = vk_format_get_blockheight(image->vk_format); in radv_image_view_init()
2004 * If we have the following image: in radv_image_view_init()
2030 vk_format_is_compressed(image->vk_format) && !vk_format_is_compressed(iview->vk_format)) { in radv_image_view_init()
2035 iview->extent.width = iview->image->planes[0].surface.u.gfx9.base_mip_width; in radv_image_view_init()
2036 iview->extent.height = iview->image->planes[0].surface.u.gfx9.base_mip_height; in radv_image_view_init()
2038 unsigned lvl_width = radv_minify(image->info.width, range->baseMipLevel); in radv_image_view_init()
2039 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel); in radv_image_view_init()
2048 iview->image->planes[0].surface.u.gfx9.base_mip_width); in radv_image_view_init()
2050 iview->image->planes[0].surface.u.gfx9.base_mip_height); in radv_image_view_init()
2057 if (vk_format_get_plane_count(image->vk_format) > 1 && in radv_image_view_init()
2082 radv_layout_is_htile_compressed(const struct radv_device *device, const struct radv_image *image, in radv_layout_is_htile_compressed() argument
2089 return radv_image_has_htile(image); in radv_layout_is_htile_compressed()
2091 return radv_image_is_tc_compat_htile(image) || in radv_layout_is_htile_compressed()
2092 (radv_image_has_htile(image) && queue_mask == (1u << RADV_QUEUE_GENERAL)); in radv_layout_is_htile_compressed()
2097 * if the image doesn't have the storage bit set. This in radv_layout_is_htile_compressed()
2105 if (radv_image_is_tc_compat_htile(image) && queue_mask & (1u << RADV_QUEUE_GENERAL) && in radv_layout_is_htile_compressed()
2112 if (radv_image_is_tc_compat_htile(image) || in radv_layout_is_htile_compressed()
2113 (radv_image_has_htile(image) && in radv_layout_is_htile_compressed()
2114 !(image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)))) { in radv_layout_is_htile_compressed()
2115 /* Keep HTILE compressed if the image is only going to in radv_layout_is_htile_compressed()
2124 return radv_image_is_tc_compat_htile(image); in radv_layout_is_htile_compressed()
2129 radv_layout_can_fast_clear(const struct radv_device *device, const struct radv_image *image, in radv_layout_can_fast_clear() argument
2133 if (radv_dcc_enabled(image, level) && in radv_layout_can_fast_clear()
2134 !radv_layout_dcc_compressed(device, image, level, layout, in_render_loop, queue_mask)) in radv_layout_can_fast_clear()
2137 if (!(image->usage & RADV_IMAGE_USAGE_WRITE_BITS)) in radv_layout_can_fast_clear()
2147 return queue_mask == (1u << RADV_QUEUE_GENERAL) || radv_image_use_comp_to_single(device, image); in radv_layout_can_fast_clear()
2151 radv_layout_dcc_compressed(const struct radv_device *device, const struct radv_image *image, in radv_layout_dcc_compressed() argument
2155 if (!radv_dcc_enabled(image, level)) in radv_layout_dcc_compressed()
2158 …if (image->tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT && queue_mask & (1u << RADV_QUEUE_FOR… in radv_layout_dcc_compressed()
2161 /* If the image is read-only, we can always just keep it compressed */ in radv_layout_dcc_compressed()
2162 if (!(image->usage & RADV_IMAGE_USAGE_WRITE_BITS)) in radv_layout_dcc_compressed()
2165 /* Don't compress compute transfer dst when image stores are not supported. */ in radv_layout_dcc_compressed()
2167 (queue_mask & (1u << RADV_QUEUE_COMPUTE)) && !radv_image_use_dcc_image_stores(device, image)) in radv_layout_dcc_compressed()
2174 radv_layout_fmask_compressed(const struct radv_device *device, const struct radv_image *image, in radv_layout_fmask_compressed() argument
2177 if (!radv_image_has_fmask(image)) in radv_layout_fmask_compressed()
2180 /* Don't compress compute transfer dst because image stores ignore FMASK and it needs to be in radv_layout_fmask_compressed()
2189 (queue_mask == (1u << RADV_QUEUE_GENERAL) || radv_image_is_tc_compat_cmask(image)); in radv_layout_fmask_compressed()
2193 radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family) in radv_image_queue_family_mask() argument
2195 if (!image->exclusive) in radv_image_queue_family_mask()
2196 return image->queue_family_mask; in radv_image_queue_family_mask()
2232 RADV_FROM_HANDLE(radv_image, image, _image); in radv_DestroyImage()
2234 if (!image) in radv_DestroyImage()
2237 radv_destroy_image(device, pAllocator, image); in radv_DestroyImage()
2244 RADV_FROM_HANDLE(radv_image, image, _image); in radv_GetImageSubresourceLayout()
2250 if (vk_format_get_plane_count(image->vk_format) > 1) in radv_GetImageSubresourceLayout()
2253 struct radv_image_plane *plane = &image->planes[plane_id]; in radv_GetImageSubresourceLayout()
2256 if (image->tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) { in radv_GetImageSubresourceLayout()
2275 if (image->vk_format == VK_FORMAT_R32G32B32_UINT || in radv_GetImageSubresourceLayout()
2276 image->vk_format == VK_FORMAT_R32G32B32_SINT || in radv_GetImageSubresourceLayout()
2277 image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) { in radv_GetImageSubresourceLayout()
2294 if (image->type == VK_IMAGE_TYPE_3D) in radv_GetImageSubresourceLayout()
2295 pLayout->size *= u_minify(image->info.depth, level); in radv_GetImageSubresourceLayout()
2303 if (image->type == VK_IMAGE_TYPE_3D) in radv_GetImageSubresourceLayout()
2304 pLayout->size *= u_minify(image->info.depth, level); in radv_GetImageSubresourceLayout()
2312 RADV_FROM_HANDLE(radv_image, image, _image); in radv_GetImageDrmFormatModifierPropertiesEXT()
2314 pProperties->drmFormatModifier = image->planes[0].surface.modifier; in radv_GetImageDrmFormatModifierPropertiesEXT()