Lines Matching refs:cs
37 struct radeon_cmdbuf *cs, unsigned raster_config, in si_write_harvested_raster_configs() argument
50 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
54 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
57 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]); in si_write_harvested_raster_configs()
62 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
66 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
71 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); in si_write_harvested_raster_configs()
75 si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs) in si_emit_compute() argument
77 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3); in si_emit_compute()
78 radeon_emit(cs, 0); in si_emit_compute()
79 radeon_emit(cs, 0); in si_emit_compute()
80 radeon_emit(cs, 0); in si_emit_compute()
82 radeon_set_sh_reg(cs, R_00B834_COMPUTE_PGM_HI, in si_emit_compute()
85 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2); in si_emit_compute()
88 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); in si_emit_compute()
89 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); in si_emit_compute()
93 radeon_set_sh_reg_seq(cs, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2); in si_emit_compute()
94 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); in si_emit_compute()
95 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); in si_emit_compute()
100 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2); in si_emit_compute()
101 radeon_emit(cs, bc_va >> 8); in si_emit_compute()
102 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); in si_emit_compute()
107 radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY, in si_emit_compute()
112 radeon_set_sh_reg_seq(cs, R_00B890_COMPUTE_USER_ACCUM_0, 5); in si_emit_compute()
113 radeon_emit(cs, 0); /* R_00B890_COMPUTE_USER_ACCUM_0 */ in si_emit_compute()
114 radeon_emit(cs, 0); /* R_00B894_COMPUTE_USER_ACCUM_1 */ in si_emit_compute()
115 radeon_emit(cs, 0); /* R_00B898_COMPUTE_USER_ACCUM_2 */ in si_emit_compute()
116 radeon_emit(cs, 0); /* R_00B89C_COMPUTE_USER_ACCUM_3 */ in si_emit_compute()
117 radeon_emit(cs, 0); /* R_00B8A0_COMPUTE_PGM_RSRC3 */ in si_emit_compute()
129 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */); in si_emit_compute()
133 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8); in si_emit_compute()
145 radeon_set_sh_reg_seq(cs, R_00B838_COMPUTE_TBA_LO, 4); in si_emit_compute()
146 radeon_emit(cs, tba_va >> 8); in si_emit_compute()
147 radeon_emit(cs, tba_va >> 40); in si_emit_compute()
148 radeon_emit(cs, tma_va >> 8); in si_emit_compute()
149 radeon_emit(cs, tma_va >> 40); in si_emit_compute()
161 si_set_raster_config(struct radv_physical_device *physical_device, struct radeon_cmdbuf *cs) in si_set_raster_config() argument
173 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config); in si_set_raster_config()
175 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); in si_set_raster_config()
177 si_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1); in si_set_raster_config()
182 si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) in si_emit_graphics() argument
189 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in si_emit_graphics()
190 radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1)); in si_emit_graphics()
191 radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1)); in si_emit_graphics()
194 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0)); in si_emit_graphics()
195 radeon_emit(cs, 0); in si_emit_graphics()
199 si_set_raster_config(physical_device, cs); in si_emit_graphics()
201 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64)); in si_emit_graphics()
203 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0)); in si_emit_graphics()
207 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES); in si_emit_graphics()
208 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40); in si_emit_graphics()
212 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2); in si_emit_graphics()
213 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); in si_emit_graphics()
214 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); in si_emit_graphics()
218 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1); in si_emit_graphics()
220 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0); in si_emit_graphics()
222 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, in si_emit_graphics()
226 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0); in si_emit_graphics()
232 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); in si_emit_graphics()
233 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, in si_emit_graphics()
235 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL, in si_emit_graphics()
237 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR, in si_emit_graphics()
239 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0); in si_emit_graphics()
240 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR, in si_emit_graphics()
246 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i * 8, 0); in si_emit_graphics()
247 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i * 8, fui(1.0)); in si_emit_graphics()
252 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); in si_emit_graphics()
253 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); in si_emit_graphics()
255 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0); in si_emit_graphics()
256 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0); in si_emit_graphics()
257 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); in si_emit_graphics()
258 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); in si_emit_graphics()
259 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0); in si_emit_graphics()
262 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, in si_emit_graphics()
267 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0); in si_emit_graphics()
268 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0); in si_emit_graphics()
269 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0); in si_emit_graphics()
270 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0); in si_emit_graphics()
271 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0); in si_emit_graphics()
272 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0); in si_emit_graphics()
274 radeon_set_context_reg(cs, R_028038_DB_DFSM_CONTROL, in si_emit_graphics()
278 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0); in si_emit_graphics()
279 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0); in si_emit_graphics()
280 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0); in si_emit_graphics()
282 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL, in si_emit_graphics()
291 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0); in si_emit_graphics()
292 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0); in si_emit_graphics()
293 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0); in si_emit_graphics()
297 radeon_set_sh_reg(cs, R_00B524_SPI_SHADER_PGM_HI_LS, in si_emit_graphics()
299 radeon_set_sh_reg(cs, R_00B324_SPI_SHADER_PGM_HI_ES, in si_emit_graphics()
302 radeon_set_sh_reg(cs, R_00B414_SPI_SHADER_PGM_HI_LS, in si_emit_graphics()
304 radeon_set_sh_reg(cs, R_00B214_SPI_SHADER_PGM_HI_ES, in si_emit_graphics()
307 radeon_set_sh_reg(cs, R_00B524_SPI_SHADER_PGM_HI_LS, in si_emit_graphics()
309 radeon_set_sh_reg(cs, R_00B324_SPI_SHADER_PGM_HI_ES, in si_emit_graphics()
329 radeon_set_sh_reg_idx(physical_device, cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS, 3, in si_emit_graphics()
331 radeon_set_sh_reg_idx(physical_device, cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS, 3, in si_emit_graphics()
333 radeon_set_sh_reg_idx(physical_device, cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS, 3, in si_emit_graphics()
338 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 3, in si_emit_graphics()
341 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, in si_emit_graphics()
343 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_WAVE_LIMIT(0x3F)); in si_emit_graphics()
344 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, in si_emit_graphics()
350 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, in si_emit_graphics()
354 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, 3, in si_emit_graphics()
368 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL, S_028C50_MAX_DEALLOCS_IN_WAVE(512)); in si_emit_graphics()
369 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14); in si_emit_graphics()
376 radeon_set_context_reg(cs, R_028838_PA_CL_NGG_CNTL, in si_emit_graphics()
393 cs, R_02807C_DB_RMI_L2_CACHE_CONTROL, in si_emit_graphics()
401 cs, R_028410_CB_RMI_GL2_CACHE_CONTROL, in si_emit_graphics()
408 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0); in si_emit_graphics()
410 radeon_set_sh_reg_seq(cs, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 4); in si_emit_graphics()
411 radeon_emit(cs, 0); /* R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0 */ in si_emit_graphics()
412 radeon_emit(cs, 0); /* R_00B0CC_SPI_SHADER_USER_ACCUM_PS_1 */ in si_emit_graphics()
413 radeon_emit(cs, 0); /* R_00B0D0_SPI_SHADER_USER_ACCUM_PS_2 */ in si_emit_graphics()
414 radeon_emit(cs, 0); /* R_00B0D4_SPI_SHADER_USER_ACCUM_PS_3 */ in si_emit_graphics()
415 radeon_set_sh_reg_seq(cs, R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0, 4); in si_emit_graphics()
416 radeon_emit(cs, 0); /* R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0 */ in si_emit_graphics()
417 radeon_emit(cs, 0); /* R_00B1CC_SPI_SHADER_USER_ACCUM_VS_1 */ in si_emit_graphics()
418 radeon_emit(cs, 0); /* R_00B1D0_SPI_SHADER_USER_ACCUM_VS_2 */ in si_emit_graphics()
419 radeon_emit(cs, 0); /* R_00B1D4_SPI_SHADER_USER_ACCUM_VS_3 */ in si_emit_graphics()
420 radeon_set_sh_reg_seq(cs, R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0, 4); in si_emit_graphics()
421 radeon_emit(cs, 0); /* R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0 */ in si_emit_graphics()
422 radeon_emit(cs, 0); /* R_00B2CC_SPI_SHADER_USER_ACCUM_ESGS_1 */ in si_emit_graphics()
423 radeon_emit(cs, 0); /* R_00B2D0_SPI_SHADER_USER_ACCUM_ESGS_2 */ in si_emit_graphics()
424 radeon_emit(cs, 0); /* R_00B2D4_SPI_SHADER_USER_ACCUM_ESGS_3 */ in si_emit_graphics()
425 radeon_set_sh_reg_seq(cs, R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0, 4); in si_emit_graphics()
426 radeon_emit(cs, 0); /* R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0 */ in si_emit_graphics()
427 radeon_emit(cs, 0); /* R_00B4CC_SPI_SHADER_USER_ACCUM_LSHS_1 */ in si_emit_graphics()
428 radeon_emit(cs, 0); /* R_00B4D0_SPI_SHADER_USER_ACCUM_LSHS_2 */ in si_emit_graphics()
429 radeon_emit(cs, 0); /* R_00B4D4_SPI_SHADER_USER_ACCUM_LSHS_3 */ in si_emit_graphics()
431 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS, in si_emit_graphics()
433 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0); in si_emit_graphics()
436 radeon_set_context_reg(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff); in si_emit_graphics()
439 cs, R_028848_PA_CL_VRS_CNTL, in si_emit_graphics()
445 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION, in si_emit_graphics()
459 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution); in si_emit_graphics()
461 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14); in si_emit_graphics()
462 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16); in si_emit_graphics()
468 radeon_set_context_reg(cs, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8); in si_emit_graphics()
470 radeon_set_context_reg(cs, R_028084_TA_BC_BASE_ADDR_HI, in si_emit_graphics()
477 cs, R_028C48_PA_SC_BINNER_CNTL_1, in si_emit_graphics()
480 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, in si_emit_graphics()
482 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0); in si_emit_graphics()
486 radeon_set_context_reg(cs, R_028A00_PA_SU_POINT_SIZE, in si_emit_graphics()
488 radeon_set_context_reg(cs, R_028A04_PA_SU_POINT_MINMAX, in si_emit_graphics()
493 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL, S_028004_ZPASS_INCREMENT_DISABLE(1)); in si_emit_graphics()
507 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL, small_prim_filter_cntl); in si_emit_graphics()
511 cs, R_0286D4_SPI_INTERP_CONTROL_0, in si_emit_graphics()
519 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL, in si_emit_graphics()
523 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL, in si_emit_graphics()
542 radeon_set_sh_reg_seq(cs, regs[i], 4); in si_emit_graphics()
543 radeon_emit(cs, tba_va >> 8); in si_emit_graphics()
544 radeon_emit(cs, tba_va >> 40); in si_emit_graphics()
545 radeon_emit(cs, tma_va >> 8); in si_emit_graphics()
546 radeon_emit(cs, tma_va >> 40); in si_emit_graphics()
553 radeon_set_context_reg(cs, R_028BDC_PA_SC_LINE_CNTL, 0); in si_emit_graphics()
555 si_emit_compute(device, cs); in si_emit_graphics()
561 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX); in cik_create_gfx_config() local
562 if (!cs) in cik_create_gfx_config()
565 si_emit_graphics(device, cs); in cik_create_gfx_config()
567 while (cs->cdw & 7) { in cik_create_gfx_config()
569 radeon_emit(cs, PKT2_NOP_PAD); in cik_create_gfx_config()
571 radeon_emit(cs, PKT3_NOP_PAD); in cik_create_gfx_config()
575 device->ws->buffer_create(device->ws, cs->cdw * 4, 4096, device->ws->cs_domain(device->ws), in cik_create_gfx_config()
588 memcpy(map, cs->buf, cs->cdw * 4); in cik_create_gfx_config()
591 device->gfx_init_size_dw = cs->cdw; in cik_create_gfx_config()
593 device->ws->cs_destroy(cs); in cik_create_gfx_config()
645 si_write_scissors(struct radeon_cmdbuf *cs, int first, int count, const VkRect2D *scissors, in si_write_scissors() argument
654 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2); in si_write_scissors()
671 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) | S_028250_TL_Y(scissor.offset.y) | in si_write_scissors()
673 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) | in si_write_scissors()
681 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4); in si_write_scissors()
682 radeon_emit(cs, fui(guardband_y)); in si_write_scissors()
683 radeon_emit(cs, fui(1.0)); in si_write_scissors()
684 radeon_emit(cs, fui(guardband_x)); in si_write_scissors()
685 radeon_emit(cs, fui(1.0)); in si_write_scissors()
838 si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum chip_class chip_class, bool is_mec, in si_cs_emit_write_event_eop() argument
860 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_cs_emit_write_event_eop()
861 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1)); in si_cs_emit_write_event_eop()
862 radeon_emit(cs, gfx9_eop_bug_va); in si_cs_emit_write_event_eop()
863 radeon_emit(cs, gfx9_eop_bug_va >> 32); in si_cs_emit_write_event_eop()
866 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false)); in si_cs_emit_write_event_eop()
867 radeon_emit(cs, op); in si_cs_emit_write_event_eop()
868 radeon_emit(cs, sel); in si_cs_emit_write_event_eop()
869 radeon_emit(cs, va); /* address lo */ in si_cs_emit_write_event_eop()
870 radeon_emit(cs, va >> 32); /* address hi */ in si_cs_emit_write_event_eop()
871 radeon_emit(cs, new_fence); /* immediate data lo */ in si_cs_emit_write_event_eop()
872 radeon_emit(cs, 0); /* immediate data hi */ in si_cs_emit_write_event_eop()
874 radeon_emit(cs, 0); /* unused */ in si_cs_emit_write_event_eop()
886 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, false)); in si_cs_emit_write_event_eop()
887 radeon_emit(cs, op); in si_cs_emit_write_event_eop()
888 radeon_emit(cs, sel); in si_cs_emit_write_event_eop()
889 radeon_emit(cs, va); /* address lo */ in si_cs_emit_write_event_eop()
890 radeon_emit(cs, va >> 32); /* address hi */ in si_cs_emit_write_event_eop()
891 radeon_emit(cs, new_fence); /* immediate data lo */ in si_cs_emit_write_event_eop()
892 radeon_emit(cs, 0); /* immediate data hi */ in si_cs_emit_write_event_eop()
894 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, false)); in si_cs_emit_write_event_eop()
895 radeon_emit(cs, op); in si_cs_emit_write_event_eop()
896 radeon_emit(cs, va); in si_cs_emit_write_event_eop()
897 radeon_emit(cs, ((va >> 32) & 0xffff) | EOS_DATA_SEL(EOS_DATA_SEL_VALUE_32BIT)); in si_cs_emit_write_event_eop()
898 radeon_emit(cs, new_fence); in si_cs_emit_write_event_eop()
906 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false)); in si_cs_emit_write_event_eop()
907 radeon_emit(cs, op); in si_cs_emit_write_event_eop()
908 radeon_emit(cs, va); in si_cs_emit_write_event_eop()
909 radeon_emit(cs, ((va >> 32) & 0xffff) | sel); in si_cs_emit_write_event_eop()
910 radeon_emit(cs, 0); /* immediate data */ in si_cs_emit_write_event_eop()
911 radeon_emit(cs, 0); /* unused */ in si_cs_emit_write_event_eop()
914 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false)); in si_cs_emit_write_event_eop()
915 radeon_emit(cs, op); in si_cs_emit_write_event_eop()
916 radeon_emit(cs, va); in si_cs_emit_write_event_eop()
917 radeon_emit(cs, ((va >> 32) & 0xffff) | sel); in si_cs_emit_write_event_eop()
918 radeon_emit(cs, new_fence); /* immediate data */ in si_cs_emit_write_event_eop()
919 radeon_emit(cs, 0); /* unused */ in si_cs_emit_write_event_eop()
925 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va, uint32_t ref, uint32_t mask) in radv_cp_wait_mem() argument
930 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false)); in radv_cp_wait_mem()
931 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1)); in radv_cp_wait_mem()
932 radeon_emit(cs, va); in radv_cp_wait_mem()
933 radeon_emit(cs, va >> 32); in radv_cp_wait_mem()
934 radeon_emit(cs, ref); /* reference value */ in radv_cp_wait_mem()
935 radeon_emit(cs, mask); /* mask */ in radv_cp_wait_mem()
936 radeon_emit(cs, 4); /* poll interval */ in radv_cp_wait_mem()
940 si_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool is_gfx9, unsigned cp_coher_cntl) in si_emit_acquire_mem() argument
944 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) | PKT3_SHADER_TYPE_S(is_mec)); in si_emit_acquire_mem()
945 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ in si_emit_acquire_mem()
946 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ in si_emit_acquire_mem()
947 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */ in si_emit_acquire_mem()
948 radeon_emit(cs, 0); /* CP_COHER_BASE */ in si_emit_acquire_mem()
949 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */ in si_emit_acquire_mem()
950 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ in si_emit_acquire_mem()
953 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false)); in si_emit_acquire_mem()
954 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ in si_emit_acquire_mem()
955 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ in si_emit_acquire_mem()
956 radeon_emit(cs, 0); /* CP_COHER_BASE */ in si_emit_acquire_mem()
957 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ in si_emit_acquire_mem()
962 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uint32_t *flush_cnt, in gfx10_cs_emit_cache_flush() argument
1010 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1011 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); in gfx10_cs_emit_cache_flush()
1019 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1020 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); in gfx10_cs_emit_cache_flush()
1041 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1042 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in gfx10_cs_emit_cache_flush()
1046 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1047 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in gfx10_cs_emit_cache_flush()
1054 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1055 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4))); in gfx10_cs_emit_cache_flush()
1088 cs, chip_class, false, cb_db_event, in gfx10_cs_emit_cache_flush()
1094 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff); in gfx10_cs_emit_cache_flush()
1099 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1100 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); in gfx10_cs_emit_cache_flush()
1109 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0)); in gfx10_cs_emit_cache_flush()
1110 radeon_emit(cs, 0); /* CP_COHER_CNTL */ in gfx10_cs_emit_cache_flush()
1111 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ in gfx10_cs_emit_cache_flush()
1112 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */ in gfx10_cs_emit_cache_flush()
1113 radeon_emit(cs, 0); /* CP_COHER_BASE */ in gfx10_cs_emit_cache_flush()
1114 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */ in gfx10_cs_emit_cache_flush()
1115 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ in gfx10_cs_emit_cache_flush()
1116 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */ in gfx10_cs_emit_cache_flush()
1122 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in gfx10_cs_emit_cache_flush()
1123 radeon_emit(cs, 0); in gfx10_cs_emit_cache_flush()
1129 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1130 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); in gfx10_cs_emit_cache_flush()
1132 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1133 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); in gfx10_cs_emit_cache_flush()
1138 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uint32_t *flush_cnt, in si_cs_emit_cache_flush() argument
1148 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va, is_mec, flush_bits, in si_cs_emit_cache_flush()
1172 si_cs_emit_write_event_eop(cs, chip_class, is_mec, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, in si_cs_emit_cache_flush()
1187 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1188 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); in si_cs_emit_cache_flush()
1194 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1195 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); in si_cs_emit_cache_flush()
1201 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1202 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in si_cs_emit_cache_flush()
1206 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1207 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in si_cs_emit_cache_flush()
1213 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1214 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in si_cs_emit_cache_flush()
1256 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags, EOP_DST_SEL_MEM, in si_cs_emit_cache_flush()
1258 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff); in si_cs_emit_cache_flush()
1263 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1264 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); in si_cs_emit_cache_flush()
1269 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1270 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0)); in si_cs_emit_cache_flush()
1279 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in si_cs_emit_cache_flush()
1280 radeon_emit(cs, 0); in si_cs_emit_cache_flush()
1287 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, in si_cs_emit_cache_flush()
1302 cs, is_mec, chip_class == GFX9, in si_cs_emit_cache_flush()
1309 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, in si_cs_emit_cache_flush()
1321 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl); in si_cs_emit_cache_flush()
1324 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1325 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); in si_cs_emit_cache_flush()
1327 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1328 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); in si_cs_emit_cache_flush()
1350 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128); in si_emit_cache_flush()
1352 si_cs_emit_cache_flush(cmd_buffer->cs, cmd_buffer->device->physical_device->rad_info.chip_class, in si_emit_cache_flush()
1397 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0)); in si_emit_set_predication_state()
1398 radeon_emit(cmd_buffer->cs, op); in si_emit_set_predication_state()
1399 radeon_emit(cmd_buffer->cs, va); in si_emit_set_predication_state()
1400 radeon_emit(cmd_buffer->cs, va >> 32); in si_emit_set_predication_state()
1402 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0)); in si_emit_set_predication_state()
1403 radeon_emit(cmd_buffer->cs, va); in si_emit_set_predication_state()
1404 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF)); in si_emit_set_predication_state()
1442 struct radeon_cmdbuf *cs = cmd_buffer->cs; in si_emit_cp_dma() local
1447 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9); in si_emit_cp_dma()
1479 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating)); in si_emit_cp_dma()
1480 radeon_emit(cs, header); in si_emit_cp_dma()
1481 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */ in si_emit_cp_dma()
1482 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */ in si_emit_cp_dma()
1483 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */ in si_emit_cp_dma()
1484 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */ in si_emit_cp_dma()
1485 radeon_emit(cs, command); in si_emit_cp_dma()
1489 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating)); in si_emit_cp_dma()
1490 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */ in si_emit_cp_dma()
1491 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */ in si_emit_cp_dma()
1492 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */ in si_emit_cp_dma()
1493 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */ in si_emit_cp_dma()
1494 radeon_emit(cs, command); in si_emit_cp_dma()
1504 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating)); in si_emit_cp_dma()
1505 radeon_emit(cs, 0); in si_emit_cp_dma()
1750 radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples) in radv_emit_default_sample_locations() argument
1755 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2); in radv_emit_default_sample_locations()
1756 radeon_emit(cs, (uint32_t)centroid_priority_1x); in radv_emit_default_sample_locations()
1757 radeon_emit(cs, centroid_priority_1x >> 32); in radv_emit_default_sample_locations()
1758 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x); in radv_emit_default_sample_locations()
1759 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x); in radv_emit_default_sample_locations()
1760 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x); in radv_emit_default_sample_locations()
1761 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x); in radv_emit_default_sample_locations()
1764 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2); in radv_emit_default_sample_locations()
1765 radeon_emit(cs, (uint32_t)centroid_priority_2x); in radv_emit_default_sample_locations()
1766 radeon_emit(cs, centroid_priority_2x >> 32); in radv_emit_default_sample_locations()
1767 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x); in radv_emit_default_sample_locations()
1768 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x); in radv_emit_default_sample_locations()
1769 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x); in radv_emit_default_sample_locations()
1770 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x); in radv_emit_default_sample_locations()
1773 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2); in radv_emit_default_sample_locations()
1774 radeon_emit(cs, (uint32_t)centroid_priority_4x); in radv_emit_default_sample_locations()
1775 radeon_emit(cs, centroid_priority_4x >> 32); in radv_emit_default_sample_locations()
1776 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x); in radv_emit_default_sample_locations()
1777 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x); in radv_emit_default_sample_locations()
1778 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x); in radv_emit_default_sample_locations()
1779 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x); in radv_emit_default_sample_locations()
1782 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2); in radv_emit_default_sample_locations()
1783 radeon_emit(cs, (uint32_t)centroid_priority_8x); in radv_emit_default_sample_locations()
1784 radeon_emit(cs, centroid_priority_8x >> 32); in radv_emit_default_sample_locations()
1785 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14); in radv_emit_default_sample_locations()
1786 radeon_emit_array(cs, sample_locs_8x, 4); in radv_emit_default_sample_locations()
1787 radeon_emit_array(cs, sample_locs_8x, 4); in radv_emit_default_sample_locations()
1788 radeon_emit_array(cs, sample_locs_8x, 4); in radv_emit_default_sample_locations()
1789 radeon_emit_array(cs, sample_locs_8x, 2); in radv_emit_default_sample_locations()