1 /****************************************************************************** 2 * 3 * Copyright (C) 2009-2018 Realtek Corporation 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ******************************************************************************/ 18 19 #ifndef HARDWARE_H 20 #define HARDWARE_H 21 22 #include <stdint.h> 23 #include <stddef.h> 24 25 #if __BYTE_ORDER == __LITTLE_ENDIAN 26 #define cpu_to_le16(d) (d) 27 #define cpu_to_le32(d) (d) 28 #define le16_to_cpu(d) (d) 29 #define le32_to_cpu(d) (d) 30 #elif __BYTE_ORDER == __BIG_ENDIAN 31 #define cpu_to_le16(d) bswap_16(d) 32 #define cpu_to_le32(d) bswap_32(d) 33 #define le16_to_cpu(d) bswap_16(d) 34 #define le32_to_cpu(d) bswap_32(d) 35 #else 36 #error "Unknown byte order" 37 #endif 38 39 #define FIRMWARE_DIRECTORY "/vendor/firmware/%s" 40 #define BT_CONFIG_DIRECTORY "/vendor/firmware/%s" 41 #define PATCH_DATA_FIELD_MAX_SIZE 252 42 #define RTK_VENDOR_CONFIG_MAGIC 0x8723ab55 43 #define MAX_PATCH_SIZE_24K (1024 * 24) // 24K 44 #define MAX_PATCH_SIZE_40K (1024 * 40) // 40K 45 46 #define MAX_ORG_CONFIG_SIZE (0x100 * 14) 47 #define MAX_ALT_CONFIG_SIZE (0x100 * 2) 48 49 struct rtk_bt_vendor_config_entry 50 { 51 uint16_t offset; 52 uint8_t entry_len; 53 uint8_t entry_data[0]; 54 } __attribute__((packed)); 55 56 struct rtk_bt_vendor_config 57 { 58 uint32_t signature; 59 uint16_t data_len; 60 struct rtk_bt_vendor_config_entry entry[0]; 61 } __attribute__((packed)); 62 63 #define HCI_CMD_MAX_LEN 258 64 65 #define HCI_VERSION_MASK_10 (1 << 0) // Bluetooth Core Spec 1.0b 66 #define HCI_VERSION_MASK_11 (1 << 1) // Bluetooth Core Spec 1.1 67 #define HCI_VERSION_MASK_12 (1 << 2) // Bluetooth Core Spec 1.2 68 #define HCI_VERSION_MASK_20 (1 << 3) // Bluetooth Core Spec 2.0+EDR 69 #define HCI_VERSION_MASK_21 (1 << 4) // Bluetooth Core Spec 2.1+EDR 70 #define HCI_VERSION_MASK_30 (1 << 5) // Bluetooth Core Spec 3.0+HS 71 #define HCI_VERSION_MASK_40 (1 << 6) // Bluetooth Core Spec 4.0 72 #define HCI_VERSION_MASK_41 (1 << 7) // Bluetooth Core Spec 4.1 73 #define HCI_VERSION_MASK_42 (1 << 8) // Bluetooth Core Spec 4.2 74 #define HCI_VERSION_MASK_ALL (0xFFFFFFFF) 75 76 #define HCI_REVISION_MASK_ALL (0xFFFFFFFF) 77 78 #define LMP_SUBVERSION_NONE (0x0) 79 #define LMPSUBVERSION_8723a (0x1200) 80 81 #define CHIPTYPE_NONE (0x1F) // Chip Type's range: 0x0 ~ 0xF 82 #define CHIP_TYPE_MASK_ALL (0xFFFFFFFF) 83 84 #define PROJECT_ID_MASK_ALL (0xFFFFFFFF) // temp used for unknown project id for a new chip 85 86 #define PATCH_OPTIONAL_MATCH_FLAG_CHIPTYPE (0x1) 87 88 #define CONFIG_MAC_OFFSET_GEN_1_2 (0x3C) // MAC's OFFSET in config/efuse for realtek generation 1~2 bluetooth chip 89 #define CONFIG_MAC_OFFSET_GEN_3PLUS (0x44) // MAC's OFFSET in config/efuse for rtk generation 3+ bluetooth chip 90 #define CONFIG_MAC_OFFSET_GEN_4PLUS (0x30) // MAC's OFFSET in config/efuse for rtk generation 4+ bluetooth chip 91 92 #define HCI_EVT_CMD_CMPL_OPCODE_OFFSET (3) // opcode's offset in COMMAND Completed Event 93 #define HCI_EVT_CMD_CMPL_STATUS_OFFSET (5) // status's offset in COMMAND Completed Event 94 95 #define HCI_EVT_CMD_CMPL_OP1001_HCI_VERSION_OFFSET (6) // HCI_Version's offset in COMMAND Completed Event for OpCode 0x1001(Read Local Version Information Command) 96 #define HCI_EVT_CMD_CMPL_OP1001_HCI_REVISION_OFFSET (7) // HCI_Revision's offset in COMMAND Completed Event for OpCode 0x1001(Read Local Version Information Command) 97 #define HCI_EVT_CMD_CMPL_OP1001_LMP_SUBVERSION_OFFSET (12) // LMP Subversion's offset in COMMAND Completed Event for OpCode 0x1001(Read Local Version Information Command) 98 #define HCI_EVT_CMD_CMPL_OP0C14_LOCAL_NAME_OFFSET (6) // Local Name's offset in COMMAND Completed Event for OpCode 0x0C14(Read Local Name Command) 99 #define HCI_EVT_CMD_CMPL_OP1009_BDADDR_OFFSET (6) // BD_ADDR's offset in COMMAND Completed Event for OpCode 0x1009(Read BD_ADDR Command) 100 #define HCI_EVT_CMD_CMPL_OPFC6D_EVERSION_OFFSET (6) // eversion's offset in COMMAND Completed Event for OpCode 0xfc6d(Read eVERSION Vendor Command) 101 #define HCI_EVT_CMD_CMPL_OPFC61_CHIPTYPE_OFFSET (6) // chip type's offset in COMMAND Completed Event for OpCode 0xfc61(Read ChipType Vendor Command) 102 103 //#define UPDATE_BAUDRATE_CMD_PARAM_SIZE (6) 104 #define HCI_CMD_PREAMBLE_SIZE (3) 105 #define HCI_CMD_READ_CHIP_TYPE_SIZE (5) 106 //#define HCD_REC_PAYLOAD_LEN_BYTE (2) 107 //#define BD_ADDR_LEN (6) 108 //#define LOCAL_NAME_BUFFER_LEN (32) 109 //#define LOCAL_BDADDR_PATH_BUFFER_LEN (256) 110 111 #define H5_SYNC_REQ_SIZE (2) 112 #define H5_SYNC_RESP_SIZE (2) 113 #define H5_CONF_REQ_SIZE (3) 114 #define H5_CONF_RESP_SIZE (2) 115 116 /****************************************************************************** 117 ** Local type definitions 118 ******************************************************************************/ 119 120 /* Hardware Configuration State */ 121 enum 122 { 123 HW_CFG_H5_INIT = 1, 124 HW_CFG_READ_LOCAL_VER, 125 HW_CFG_READ_ECO_VER, // eco version 126 HW_CFG_READ_CHIP_TYPE, 127 HW_CFG_START, 128 HW_CFG_SET_UART_BAUD_HOST, // change FW baudrate 129 HW_CFG_SET_UART_BAUD_CONTROLLER, // change Host baudrate 130 HW_CFG_SET_UART_HW_FLOW_CONTROL, 131 HW_CFG_RESET_CHANNEL_CONTROLLER, 132 HW_RESET_CONTROLLER, 133 HARDWARE_INIT_COMPLETE, 134 HW_CFG_DL_FW_PATCH 135 }; 136 137 /* h/w config control block */ 138 typedef struct 139 { 140 uint32_t max_patch_size; 141 uint32_t baudrate; 142 uint16_t lmp_subversion; 143 uint16_t lmp_subversion_default; 144 uint16_t lmp_sub_current; 145 uint8_t state; /* Hardware configuration state */ 146 uint8_t eversion; 147 uint32_t project_id_mask; 148 uint8_t hci_version; 149 uint8_t hci_revision; 150 uint8_t chip_type; 151 uint8_t dl_fw_flag; 152 int fw_len; /* FW patch file len */ 153 size_t config_len; /* Config patch file len */ 154 unsigned int total_len; /* FW & config extracted buf len */ 155 uint8_t *fw_buf; /* FW patch file buf */ 156 uint8_t *config_buf; /* Config patch file buf */ 157 uint8_t *total_buf; /* FW & config extracted buf */ 158 uint8_t patch_frag_cnt; /* Patch fragment count download */ 159 uint8_t patch_frag_idx; /* Current patch fragment index */ 160 uint8_t patch_frag_len; /* Patch fragment length */ 161 uint8_t patch_frag_tail; /* Last patch fragment length */ 162 uint8_t hw_flow_cntrl; /* Uart flow control, bit7:set, bit0:enable */ 163 uint16_t vid; /* usb vendor id */ 164 uint16_t pid; /* usb product id */ 165 uint8_t heartbeat; /*heartbeat*/ 166 } bt_hw_cfg_cb_t; 167 168 /* low power mode parameters */ 169 typedef struct 170 { 171 uint8_t sleep_mode; /* 0(disable),1(UART),9(H5) */ 172 uint8_t host_stack_idle_threshold; /* Unit scale 300ms/25ms */ 173 uint8_t host_controller_idle_threshold; /* Unit scale 300ms/25ms */ 174 uint8_t bt_wake_polarity; /* 0=Active Low, 1= Active High */ 175 uint8_t host_wake_polarity; /* 0=Active Low, 1= Active High */ 176 uint8_t allow_host_sleep_during_sco; 177 uint8_t combine_sleep_mode_and_lpm; 178 uint8_t enable_uart_txd_tri_state; /* UART_TXD Tri-State */ 179 uint8_t sleep_guard_time; /* sleep guard time in 12.5ms */ 180 uint8_t wakeup_guard_time; /* wakeup guard time in 12.5ms */ 181 uint8_t txd_config; /* TXD is high in sleep state */ 182 uint8_t pulsed_host_wake; /* pulsed host wake if mode = 1 */ 183 } bt_lpm_param_t; 184 185 #define ROM_LMP_NONE 0x0000 186 #define ROM_LMP_8723a 0x1200 187 #define ROM_LMP_8723b 0x8723 188 #define ROM_LMP_8821a 0X8821 189 #define ROM_LMP_8761a 0X8761 190 #define ROM_LMP_8761b 0X8761 191 #define ROM_LMP_8703a 0x8723 192 #define ROM_LMP_8763a 0x8763 193 #define ROM_LMP_8703b 0x8703 194 #define ROM_LMP_8723c 0x8703 195 #define ROM_LMP_8822b 0x8822 196 #define ROM_LMP_8723d 0x8723 197 #define ROM_LMP_8821c 0x8821 198 #define ROM_LMP_8822c 0x8822 199 200 struct rtk_epatch_entry 201 { 202 uint16_t chip_id; 203 uint16_t patch_length; 204 uint32_t patch_offset; 205 uint32_t svn_version; 206 uint32_t coex_version; 207 } __attribute__((packed)); 208 209 struct rtk_epatch 210 { 211 uint8_t signature[8]; 212 uint32_t fw_version; 213 uint16_t number_of_patch; 214 struct rtk_epatch_entry entry[0]; 215 } __attribute__((packed)); 216 217 #endif 218