1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19 #include "hifb_vou_graphics.h"
20 #include "hi_osal.h"
21 #include "proc_ext.h"
22 #include "hi_debug.h"
23 #include "hifb_graphic_drv.h"
24
25 typedef struct {
26 hi_bool vo_enable; /* Device enable flag */
27
28 VO_INTF_TYPE_E intf_type; /* Device interface type */
29
30 hi_u32 max_width; /* Device resolution maximum width */
31 hi_u32 max_height; /* Device resolution maximum height */
32 } vo_dev_info;
33
34 #define VO_IRQ_NR 90
35 vo_dev_info g_ast_vo_dev[VO_MAX_DEV_NUM];
36
37 vo_gfxlayer_context g_hifb_gfx_layer_ctx[VO_MAX_GRAPHICS_LAYER_NUM];
38 hi_u32 g_fb_dectect_zone = 0; /* Record the DDR detection area used */
39
get_gfx_layer_ctx(hi_void)40 vo_gfxlayer_context *get_gfx_layer_ctx(hi_void)
41 {
42 return g_hifb_gfx_layer_ctx;
43 }
44
vou_get_gfx_dcmp_pixel(fb_vo_disp_pixel_format pixel_fmt,hal_disp_pixel_format * pen_pixel_fmt)45 hi_void vou_get_gfx_dcmp_pixel(fb_vo_disp_pixel_format pixel_fmt, hal_disp_pixel_format *pen_pixel_fmt)
46 {
47 switch (pixel_fmt) {
48 case FB_VO_INPUTFMT_ARGB_4444:
49 *pen_pixel_fmt = HAL_INPUTFMT_ARGB_4444;
50 break;
51 case FB_VO_INPUTFMT_ARGB_1555:
52 *pen_pixel_fmt = HAL_INPUTFMT_ARGB_1555;
53 break;
54 case FB_VO_INPUTFMT_ARGB_8888:
55 *pen_pixel_fmt = HAL_INPUTFMT_ARGB_8888;
56 break;
57 default:
58 graphics_drv_trace(HI_DBG_ERR, "pixel format(%d) is invalid!\n", pixel_fmt);
59 break;
60 }
61 }
62
vou_graphics_init_mddr_detect(hi_void)63 hi_void vou_graphics_init_mddr_detect(hi_void)
64 {
65 return;
66 }
67
vou_graphics_set_gfx_key_mode(GRAPHIC_LAYER layer,hi_u32 key_out)68 hi_bool vou_graphics_set_gfx_key_mode(GRAPHIC_LAYER layer, hi_u32 key_out)
69 {
70 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
71
72 fb_graphic_drv_get_layer_id(layer, &disp_layer);
73 return graphic_drv_set_gfx_key_mode(disp_layer, key_out);
74 }
75
vou_graphics_set_gfx_ext(GRAPHIC_LAYER layer,fb_vo_gfx_bitextend mode)76 hi_bool vou_graphics_set_gfx_ext(GRAPHIC_LAYER layer, fb_vo_gfx_bitextend mode)
77 {
78 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
79
80 fb_graphic_drv_get_layer_id(layer, &disp_layer);
81 return graphic_drv_set_gfx_ext(disp_layer, mode);
82 }
83
vou_graphics_set_gfx_palpha(GRAPHIC_LAYER layer,hi_u32 alpha_en,hi_u32 arange,hi_u8 alpha0,hi_u8 alpha1)84 hi_bool vou_graphics_set_gfx_palpha(GRAPHIC_LAYER layer, hi_u32 alpha_en, hi_u32 arange, hi_u8 alpha0,
85 hi_u8 alpha1)
86 {
87 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
88
89 fb_graphic_drv_get_layer_id(layer, &disp_layer);
90 return graphic_drv_set_gfx_palpha(disp_layer, alpha_en, arange, alpha0, alpha1);
91 }
92
vou_graphics_set_layer_galpha(GRAPHIC_LAYER layer,hi_u8 alpha0)93 hi_bool vou_graphics_set_layer_galpha(GRAPHIC_LAYER layer, hi_u8 alpha0)
94 {
95 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
96
97 fb_graphic_drv_get_layer_id(layer, &disp_layer);
98 return graphic_drv_layer_set_layer_galpha(disp_layer, alpha0);
99 }
100
vou_graphics_set_csc_en(GRAPHIC_LAYER layer,hi_bool csc_en)101 hi_bool vou_graphics_set_csc_en(GRAPHIC_LAYER layer, hi_bool csc_en)
102 {
103 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
104
105 fb_graphic_drv_get_layer_id(layer, &disp_layer);
106 return graphic_drv_layer_set_csc_en(disp_layer, csc_en);
107 }
108
vou_graphics_set_gfx_addr(GRAPHIC_LAYER layer,hi_u64 l_addr)109 hi_bool vou_graphics_set_gfx_addr(GRAPHIC_LAYER layer, hi_u64 l_addr)
110 {
111 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
112
113 fb_graphic_drv_get_layer_id(layer, &disp_layer);
114 return graphic_drv_set_layer_addr(disp_layer, l_addr);
115 }
116
vou_graphics_set_gfx_stride(GRAPHIC_LAYER layer,hi_u16 pitch)117 hi_bool vou_graphics_set_gfx_stride(GRAPHIC_LAYER layer, hi_u16 pitch)
118 {
119 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
120
121 fb_graphic_drv_get_layer_id(layer, &disp_layer);
122 return graphic_drv_set_gfx_stride(disp_layer, pitch);
123 }
124
vou_graphics_get_gfx_pre_mult(GRAPHIC_LAYER layer,hi_u32 * enable)125 hi_bool vou_graphics_get_gfx_pre_mult(GRAPHIC_LAYER layer, hi_u32 *enable)
126 {
127 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
128
129 fb_graphic_drv_get_layer_id(layer, &disp_layer);
130 return graphic_drv_get_gfx_pre_mult(disp_layer, enable);
131 }
132
vou_graphics_set_gfx_pre_mult(GRAPHIC_LAYER layer,hi_u32 enable)133 hi_bool vou_graphics_set_gfx_pre_mult(GRAPHIC_LAYER layer, hi_u32 enable)
134 {
135 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
136
137 fb_graphic_drv_get_layer_id(layer, &disp_layer);
138 return graphic_drv_set_gfx_pre_mult(disp_layer, enable);
139 }
140
vou_graphics_set_layer_data_fmt(GRAPHIC_LAYER layer,fb_vo_disp_pixel_format data_fmt)141 hi_bool vou_graphics_set_layer_data_fmt(GRAPHIC_LAYER layer, fb_vo_disp_pixel_format data_fmt)
142 {
143 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
144 hal_disp_pixel_format pix_fmt = HAL_INPUTFMT_ARGB_1555;
145
146 vou_get_gfx_dcmp_pixel(data_fmt, &pix_fmt);
147
148 fb_graphic_drv_get_layer_id(layer, &disp_layer);
149 return graphic_drv_set_layer_data_fmt(disp_layer, pix_fmt);
150 }
151
vou_graphics_set_layer_in_rect(GRAPHIC_LAYER layer,HIFB_RECT * rect)152 hi_bool vou_graphics_set_layer_in_rect(GRAPHIC_LAYER layer, HIFB_RECT *rect)
153 {
154 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
155
156 fb_graphic_drv_get_layer_id(layer, &disp_layer);
157 return graphic_drv_set_layer_in_rect(disp_layer, rect);
158 }
159
vou_graphics_set_layer_src_image_reso(GRAPHIC_LAYER layer,HIFB_RECT * rect)160 hi_bool vou_graphics_set_layer_src_image_reso(GRAPHIC_LAYER layer, HIFB_RECT *rect)
161 {
162 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
163
164 fb_graphic_drv_get_layer_id(layer, &disp_layer);
165 return graphic_drv_set_src_image_resolution(disp_layer, rect);
166 }
167
vou_graphics_set_layer_out_rect(GRAPHIC_LAYER layer,HIFB_RECT * rect)168 hi_bool vou_graphics_set_layer_out_rect(GRAPHIC_LAYER layer, HIFB_RECT *rect)
169 {
170 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
171
172 fb_graphic_drv_get_layer_id(layer, &disp_layer);
173 return graphic_drv_set_layer_out_rect(disp_layer, rect);
174 }
175
vou_graphics_set_color_key_value(GRAPHIC_LAYER layer,fb_vo_gfx_key_max vo_key_max,fb_vo_gfx_key_min vo_key_min)176 hi_bool vou_graphics_set_color_key_value(GRAPHIC_LAYER layer, fb_vo_gfx_key_max vo_key_max,
177 fb_vo_gfx_key_min vo_key_min)
178 {
179 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
180
181 hal_gfx_key_max key_max;
182 hal_gfx_key_min key_min;
183 key_max.key_max_r = vo_key_max.key_max_r;
184 key_max.key_max_g = vo_key_max.key_max_g;
185 key_max.key_max_b = vo_key_max.key_max_b;
186 key_min.key_min_r = vo_key_min.key_min_r;
187 key_min.key_min_g = vo_key_min.key_min_g;
188 key_min.key_min_b = vo_key_min.key_min_b;
189 fb_graphic_drv_get_layer_id(layer, &disp_layer);
190 return graphic_drv_set_color_key_value(disp_layer, key_max, key_min);
191 }
192
vou_graphics_set_color_key_mask(GRAPHIC_LAYER layer,fb_vo_gfx_mask vo_msk)193 hi_bool vou_graphics_set_color_key_mask(GRAPHIC_LAYER layer, fb_vo_gfx_mask vo_msk)
194 {
195 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
196
197 hal_gfx_mask msk;
198 fb_graphic_drv_get_layer_id(layer, &disp_layer);
199 msk.mask_r = vo_msk.mask_r;
200 msk.mask_g = vo_msk.mask_g;
201 msk.mask_b = vo_msk.mask_b;
202 return graphic_drv_set_color_key_mask(disp_layer, msk);
203 }
204
vou_graphics_set_gfx_key_en(GRAPHIC_LAYER layer,hi_u32 key_enable)205 hi_bool vou_graphics_set_gfx_key_en(GRAPHIC_LAYER layer, hi_u32 key_enable)
206 {
207 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
208
209 fb_graphic_drv_get_layer_id(layer, &disp_layer);
210 return graphic_drv_set_gfx_key_en(disp_layer, key_enable);
211 }
212
vou_graphics_set_reg_up(GRAPHIC_LAYER layer)213 hi_bool vou_graphics_set_reg_up(GRAPHIC_LAYER layer)
214 {
215 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
216
217 fb_graphic_drv_get_layer_id(layer, &disp_layer);
218 return graphic_drv_set_reg_up(disp_layer);
219 }
220
vou_graphics_init(hi_void)221 hi_s32 vou_graphics_init(hi_void)
222 {
223 hi_s32 ret;
224 hifb_vo_dev vo_dev;
225 hal_disp_syncinfo sync_info = { 0 };
226 hi_bool logic_ret;
227 hi_bool vo_enable = HI_FALSE;
228 VO_INTF_TYPE_E intf_type = HAL_DISP_INTF_BT1120;
229 hi_s32 i;
230
231 ret = fb_graphic_drv_init();
232
233 for (i = 0; i < VO_MAX_DEV_NUM; i++) {
234 vo_dev = i;
235 logic_ret = graphic_drv_get_dev_enable(vo_dev, &vo_enable);
236 if (logic_ret == HI_FALSE) {
237 continue;
238 } else {
239 g_ast_vo_dev[vo_dev].vo_enable = vo_enable;
240 }
241
242 logic_ret = graphic_drv_get_intf_sync(vo_dev, &sync_info);
243 if (logic_ret == HI_FALSE) {
244 continue;
245 } else {
246 g_ast_vo_dev[vo_dev].max_width = sync_info.hact;
247 /* 2 alg data */
248 g_ast_vo_dev[vo_dev].max_height = (sync_info.iop) ? sync_info.vact : sync_info.vact * 2;
249 }
250
251 logic_ret = graphic_drv_get_intf_mux_sel(vo_dev, &intf_type);
252 if (logic_ret == HI_FALSE) {
253 continue;
254 } else {
255 g_ast_vo_dev[vo_dev].intf_type = intf_type;
256 }
257 }
258
259 return ret;
260 }
261
vou_graphics_deinit(hi_void)262 hi_s32 vou_graphics_deinit(hi_void)
263 {
264 return fb_graphic_drv_exit();
265 }
266
vou_graphics_get_layer_galpha(GRAPHIC_LAYER layer,hi_u8 * alpha0)267 hi_bool vou_graphics_get_layer_galpha(GRAPHIC_LAYER layer, hi_u8 *alpha0)
268 {
269 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
270
271 fb_graphic_drv_get_layer_id(layer, &disp_layer);
272 return graphic_drv_get_layer_galpha(disp_layer, alpha0);
273 }
274
vou_graphics_get_layer_data_fmt(GRAPHIC_LAYER layer,hi_u32 * fmt)275 hi_bool vou_graphics_get_layer_data_fmt(GRAPHIC_LAYER layer, hi_u32 *fmt)
276 {
277 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
278
279 fb_graphic_drv_get_layer_id(layer, &disp_layer);
280 return graphic_drv_get_layer_data_fmt(disp_layer, fmt);
281 }
282
vou_graphics_get_gfx_addr(GRAPHIC_LAYER layer,hi_u64 * gfx_addr)283 hi_bool vou_graphics_get_gfx_addr(GRAPHIC_LAYER layer, hi_u64 *gfx_addr)
284 {
285 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
286
287 fb_graphic_drv_get_layer_id(layer, &disp_layer);
288 return graphic_drv_get_gfx_addr(disp_layer, gfx_addr);
289 }
290
vou_graphics_get_gfx_stride(GRAPHIC_LAYER layer,hi_u32 * gfx_stride)291 hi_bool vou_graphics_get_gfx_stride(GRAPHIC_LAYER layer, hi_u32 *gfx_stride)
292 {
293 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
294
295 fb_graphic_drv_get_layer_id(layer, &disp_layer);
296 return graphic_drv_get_gfx_stride(disp_layer, gfx_stride);
297 }
298
vou_graphics_get_dev_mode(hal_disp_layer layer,fb_vou_scan_mode * scan_mode,hi_bool * feild_update)299 hi_s32 vou_graphics_get_dev_mode(hal_disp_layer layer, fb_vou_scan_mode *scan_mode, hi_bool *feild_update)
300 {
301 hifb_vo_dev vo_dev;
302 hi_u32 layer_index;
303 unsigned long lock_flag;
304 vo_gfxlayer_context *vo_gfx_layer_ctx = HI_NULL;
305 hal_disp_layer gfx_layer = HAL_DISP_LAYER_BUTT;
306
307 fb_graphic_drv_get_layer_id(layer, &gfx_layer);
308 if (fb_graphic_drv_get_layer_index(gfx_layer, &layer_index) != HI_SUCCESS) {
309 graphics_drv_trace(HI_DBG_ERR, "gfx_layer(%u) is invalid!\n", (hi_u32)gfx_layer);
310 return HI_ERR_VO_GFX_INVALID_ID;
311 }
312
313 vo_gfx_layer_ctx = &g_hifb_gfx_layer_ctx[layer_index];
314
315 gfx_spin_lock_irqsave(&vo_gfx_layer_ctx->spin_lock, &lock_flag);
316 if (!vo_gfx_layer_ctx->binded) {
317 gfx_spin_unlock_irqrestore(&vo_gfx_layer_ctx->spin_lock, &lock_flag);
318 hifb_graphics_trace(HI_DBG_ERR, "graphics layer %u has not been binded!\n", layer_index);
319 return HI_ERR_VO_GFX_NOT_BIND;
320 }
321 vo_dev = vo_gfx_layer_ctx->binded_dev;
322
323 if (!g_ast_vo_dev[vo_dev].vo_enable) {
324 gfx_spin_unlock_irqrestore(&vo_gfx_layer_ctx->spin_lock, &lock_flag);
325 hifb_graphics_trace(HI_DBG_ERR, "vodev %d for graphics layer %u has been disable!\n", vo_dev, layer_index);
326 return HI_ERR_VO_DEV_NOT_ENABLE;
327 }
328 if (fb_graphic_drv_get_scan_mode(vo_dev, (hi_bool *)scan_mode) == HI_FALSE) {
329 gfx_spin_unlock_irqrestore(&vo_gfx_layer_ctx->spin_lock, &lock_flag);
330 hifb_graphics_trace(HI_DBG_ERR, "get vodev:%d scan mode failed!\n", vo_dev);
331 return HI_FAILURE;
332 }
333
334 if (graphic_drv_get_vt_thd_mode(vo_dev, feild_update) == HI_FALSE) {
335 gfx_spin_unlock_irqrestore(&vo_gfx_layer_ctx->spin_lock, &lock_flag);
336 hifb_graphics_trace(HI_DBG_ERR, "get vodev:%d scan mode failed!\n", vo_dev);
337 return HI_FAILURE;
338 }
339 gfx_spin_unlock_irqrestore(&vo_gfx_layer_ctx->spin_lock, &lock_flag);
340 return HI_SUCCESS;
341 }
342
fb_vo_graphics_init(hi_void)343 hi_s32 fb_vo_graphics_init(hi_void)
344 {
345 return fb_graphic_drv_init();
346 }
347
vo_graphics_deinit(hi_void)348 hi_s32 vo_graphics_deinit(hi_void)
349 {
350 return fb_graphic_drv_exit();
351 }
352
vou_graphics_resource_init(hi_void)353 hi_s32 vou_graphics_resource_init(hi_void)
354 {
355 hi_s32 ret;
356 ret = graphic_drv_resource_init();
357 if (ret != HI_SUCCESS) {
358 hifb_graphics_trace(HI_DBG_ERR, "graphic drv resource init failed.\n");
359 return ret;
360 }
361
362 return ret;
363 }
364
vou_graphics_resource_deinit(hi_void)365 hi_s32 vou_graphics_resource_deinit(hi_void)
366 {
367 hi_s32 ret;
368 ret = graphic_drv_resource_exit();
369 return ret;
370 }
371
vou_graphics_enable_layer(GRAPHIC_LAYER layer,hi_bool enable)372 hi_s32 vou_graphics_enable_layer(GRAPHIC_LAYER layer, hi_bool enable)
373 {
374 hal_disp_layer gfx_layer = HAL_DISP_LAYER_BUTT;
375
376 fb_graphic_drv_get_layer_id(layer, &gfx_layer);
377 if ((gfx_layer < LAYER_GFX_START) || (gfx_layer > LAYER_GFX_END)) {
378 return HI_ERR_VO_GFX_INVALID_ID;
379 }
380 return graphic_drv_enable_layer(gfx_layer, enable);
381 }
382
vou_graphics_set_callback(GRAPHIC_LAYER layer,fb_vo_int_type type,vo_fb_intcallback call_back,hi_void * arg)383 hi_s32 vou_graphics_set_callback(GRAPHIC_LAYER layer, fb_vo_int_type type, vo_fb_intcallback call_back,
384 hi_void *arg)
385 {
386 hal_disp_layer gfx_layer = HAL_DISP_LAYER_BUTT;
387
388 unsigned long lock_flag;
389 hi_u32 layer_index;
390 hi_s32 ret = HI_SUCCESS;
391 vo_gfxlayer_context *vo_gfx_layer_ctx = HI_NULL;
392
393 fb_graphic_drv_get_layer_id(layer, &gfx_layer);
394 if (fb_graphic_drv_get_layer_index(gfx_layer, &layer_index) != HI_SUCCESS) {
395 graphics_drv_trace(HI_DBG_ERR, "gfx_layer(%u) is invalid!\n", (hi_u32)gfx_layer);
396 return HI_ERR_VO_GFX_INVALID_ID;
397 }
398
399 vo_gfx_layer_ctx = &g_hifb_gfx_layer_ctx[layer_index];
400
401 gfx_spin_lock_irqsave(&vo_gfx_layer_ctx->spin_lock, &lock_flag);
402 switch (type) {
403 case HIFB_INTTYPE_VO:
404 vo_gfx_layer_ctx->vo_callback = (fb_intcallback)call_back;
405 vo_gfx_layer_ctx->vo_callback_arg = arg;
406 break;
407 case HIFB_INTTYPE_WBC:
408 vo_gfx_layer_ctx->wbc_callback = (fb_intcallback)call_back;
409 vo_gfx_layer_ctx->wbc_callback_arg = arg;
410 break;
411 default:
412 ret = HI_FAILURE;
413 break;
414 }
415 gfx_spin_unlock_irqrestore(&vo_gfx_layer_ctx->spin_lock, &lock_flag);
416
417 return ret;
418 }
419
vou_graphics_enable_dcmp(GRAPHIC_LAYER layer,hi_bool enable)420 hi_bool vou_graphics_enable_dcmp(GRAPHIC_LAYER layer, hi_bool enable)
421 {
422 hal_disp_layer gfx_layer = HAL_DISP_LAYER_BUTT;
423
424 fb_graphic_drv_get_layer_id(layer, &gfx_layer);
425 return graphic_drv_enable_dcmp(gfx_layer, enable);
426 }
427
vou_graphics_get_dcmp_enable_state(GRAPHIC_LAYER layer,hi_bool * enable)428 hi_bool vou_graphics_get_dcmp_enable_state(GRAPHIC_LAYER layer, hi_bool *enable)
429 {
430 hi_s32 ret;
431 hal_disp_layer gfx_layer = HAL_DISP_LAYER_BUTT;
432
433 ret = fb_graphic_drv_get_layer_id(layer, &gfx_layer);
434 if (ret != HI_SUCCESS) {
435 hifb_graphics_trace(HI_DBG_ERR, "graphics layer %d is illegal!\n", layer);
436 return HI_FAILURE;
437 }
438 return graphic_drv_get_dcmp_enable_state(gfx_layer, enable);
439 }
440
vou_graphics_enable_ghdr(GRAPHIC_LAYER layer,hi_bool enable)441 hi_bool vou_graphics_enable_ghdr(GRAPHIC_LAYER layer, hi_bool enable)
442 {
443 hi_unused(layer);
444 hi_unused(enable);
445 return HI_FALSE;
446 }
447
vou_graphics_enable_zme(GRAPHIC_LAYER layer,RECT_S * in_rect,RECT_S * out_rect,hi_bool enable)448 hi_bool vou_graphics_enable_zme(GRAPHIC_LAYER layer, RECT_S *in_rect, RECT_S *out_rect, hi_bool enable)
449 {
450 gf_g0_zme_cfg zme_cfg;
451 hal_disp_layer disp_layer = HAL_DISP_LAYER_BUTT;
452
453 fb_graphic_drv_get_layer_id(layer, &disp_layer);
454
455 zme_cfg.in_width = in_rect->u32Width;
456 zme_cfg.in_height = in_rect->u32Height;
457 zme_cfg.out_width = out_rect->u32Width;
458 zme_cfg.out_height = out_rect->u32Height;
459
460 return graphic_drv_enable_zme(disp_layer, &zme_cfg, enable);
461 }
462
vou_graphics_get_intf_size(GRAPHIC_LAYER layer,hi_u32 * width,hi_u32 * height)463 hi_s32 vou_graphics_get_intf_size(GRAPHIC_LAYER layer, hi_u32 *width, hi_u32 *height)
464 {
465 hifb_vo_dev vo_dev;
466 hi_u32 layer_index;
467 vo_gfxlayer_context *vo_gfx_layer_ctx = HI_NULL;
468 vo_dev_info *dev_info = HI_NULL;
469 hal_disp_layer gfx_layer = HAL_DISP_LAYER_BUTT;
470 hi_bool ret;
471 hal_disp_syncinfo sync_info = { 0 };
472
473 fb_graphic_drv_get_layer_id(layer, &gfx_layer);
474 if (fb_graphic_drv_get_layer_index(gfx_layer, &layer_index) != HI_SUCCESS) {
475 graphics_drv_trace(HI_DBG_ERR, "gfx_layer(%u) is invalid!\n", (hi_u32)gfx_layer);
476 return HI_ERR_VO_GFX_INVALID_ID;
477 }
478
479 vo_gfx_layer_ctx = &g_hifb_gfx_layer_ctx[layer_index];
480
481 if (!vo_gfx_layer_ctx->binded) {
482 hifb_graphics_trace(HI_DBG_ERR, "Graphics layer %u# has not been binded!\n", layer_index);
483 return HI_FAILURE;
484 }
485
486 vo_dev = vo_gfx_layer_ctx->binded_dev;
487 dev_info = &g_ast_vo_dev[vo_dev];
488
489 if (!dev_info->vo_enable) {
490 hifb_graphics_trace(HI_DBG_ERR, "The vo device (%d) for graphics layer %u has been disable!\n", vo_dev,
491 layer_index);
492 return HI_FAILURE;
493 }
494
495 /*
496 * Be sure to read from the register, otherwise the width and height of
497 * the hifb context will not be updated when the vo timing changes.
498 */
499 ret = graphic_drv_get_intf_sync(vo_dev, &sync_info);
500 if (ret == HI_FALSE) {
501 /* keep the old value. */
502 } else {
503 g_ast_vo_dev[vo_dev].max_width = sync_info.hact;
504 /* 2 alg data */
505 g_ast_vo_dev[vo_dev].max_height = (sync_info.iop) ? sync_info.vact : sync_info.vact * 2;
506 }
507
508 *width = dev_info->max_width;
509 *height = dev_info->max_height;
510
511 return HI_SUCCESS;
512 }
513
vou_graphics_get_intf_type(GRAPHIC_LAYER layer,VO_INTF_TYPE_E * intf_type)514 hi_s32 vou_graphics_get_intf_type(GRAPHIC_LAYER layer, VO_INTF_TYPE_E *intf_type)
515 {
516 hifb_vo_dev vo_dev;
517 hi_u32 layer_index;
518 hal_disp_layer gfx_layer = HAL_DISP_LAYER_BUTT;
519
520 fb_graphic_drv_get_layer_id(layer, &gfx_layer);
521
522 if (fb_graphic_drv_get_layer_index(gfx_layer, &layer_index) != HI_SUCCESS) {
523 graphics_drv_trace(HI_DBG_ERR, "gfx_layer(%u) is invalid!\n", (hi_u32)gfx_layer);
524 return HI_ERR_VO_GFX_INVALID_ID;
525 }
526 vo_dev = g_hifb_gfx_layer_ctx[layer_index].binded_dev;
527 *intf_type = g_ast_vo_dev[vo_dev].intf_type;
528
529 return HI_SUCCESS;
530 }
531
vou_graphics_set_csc_coef(GRAPHIC_LAYER layer)532 hi_s32 vou_graphics_set_csc_coef(GRAPHIC_LAYER layer)
533 {
534 hi_u32 layer_index;
535 hal_disp_layer gfx_layer = HAL_DISP_LAYER_BUTT;
536
537 fb_graphic_drv_get_layer_id(layer, &gfx_layer);
538
539 if (fb_graphic_drv_get_layer_index(gfx_layer, &layer_index) != HI_SUCCESS) {
540 graphics_drv_trace(HI_DBG_ERR, "gfx_layer(%u) is invalid!\n", (hi_u32)gfx_layer);
541 return HI_ERR_VO_GFX_INVALID_ID;
542 }
543
544 return fb_graphic_drv_set_csc_coef(gfx_layer, &g_hifb_gfx_layer_ctx[layer_index].gfx_csc,
545 &g_hifb_gfx_layer_ctx[layer_index].coef_param);
546 }
547
548 /* check the bind is exist or not when the first open */
vou_graphics_open_layer(hal_disp_layer gfx_layer)549 hi_s32 vou_graphics_open_layer(hal_disp_layer gfx_layer)
550 {
551 hifb_vo_dev vo_dev;
552 unsigned long lock_flag = 0;
553 hi_u32 layer_index;
554
555 if (fb_graphic_drv_get_layer_index(gfx_layer, &layer_index) != HI_SUCCESS) {
556 graphics_drv_trace(HI_DBG_ERR, "gfx_layer(%u) is invalid!\n", (hi_u32)gfx_layer);
557 return HI_ERR_VO_GFX_INVALID_ID;
558 }
559
560 gfx_spin_lock_irqsave(&g_hifb_gfx_layer_ctx[layer_index].spin_lock, &lock_flag);
561 if (!g_hifb_gfx_layer_ctx[layer_index].binded) {
562 gfx_spin_unlock_irqrestore(&g_hifb_gfx_layer_ctx[layer_index].spin_lock, &lock_flag);
563 hifb_graphics_trace(HI_DBG_ERR, "graphics layer %u has not been binded!\n", layer_index);
564 return HI_ERR_VO_GFX_NOT_BIND;
565 }
566
567 vo_dev = g_hifb_gfx_layer_ctx[layer_index].binded_dev;
568
569 if (!g_ast_vo_dev[vo_dev].vo_enable) {
570 gfx_spin_unlock_irqrestore(&g_hifb_gfx_layer_ctx[layer_index].spin_lock, &lock_flag);
571 hifb_graphics_trace(HI_DBG_ERR, "vodev %d for graphics layer %u has not been enable!\n", vo_dev, layer_index);
572 return HI_ERR_VO_DEV_NOT_ENABLE;
573 }
574 g_hifb_gfx_layer_ctx[layer_index].opened = HI_TRUE;
575 gfx_spin_unlock_irqrestore(&g_hifb_gfx_layer_ctx[layer_index].spin_lock, &lock_flag);
576 return HI_SUCCESS;
577 }
578
vou_graphics_close_layer(hal_disp_layer gfx_layer)579 hi_s32 vou_graphics_close_layer(hal_disp_layer gfx_layer)
580 {
581 unsigned long lock_flag;
582 hi_u32 layer_index;
583
584 if (fb_graphic_drv_get_layer_index(gfx_layer, &layer_index) != HI_SUCCESS) {
585 graphics_drv_trace(HI_DBG_ERR, "gfx_layer(%u) is invalid!\n", (hi_u32)gfx_layer);
586 return HI_ERR_VO_GFX_INVALID_ID;
587 }
588
589 gfx_spin_lock_irqsave(&g_hifb_gfx_layer_ctx[layer_index].spin_lock, &lock_flag);
590 g_hifb_gfx_layer_ctx[layer_index].opened = HI_FALSE;
591 gfx_spin_unlock_irqrestore(&g_hifb_gfx_layer_ctx[layer_index].spin_lock, &lock_flag);
592
593 return HI_SUCCESS;
594 }
595
fb_vou_graphics_show_proc(osal_proc_entry_t * s)596 hi_s32 fb_vou_graphics_show_proc(osal_proc_entry_t *s)
597 {
598 fb_vo_csc csc;
599 hi_s32 dev;
600 hi_s32 i;
601
602 osal_seq_printf(s, "\r\n");
603 osal_seq_printf(s, "-----GRAPHIC LAYER CSC PARAM-----------------------------\n");
604 /* 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 */
605 osal_seq_printf(s, "%s%s%s%s%s%s\n", " LAYERID", " Matrix", " Luma", " Cont",
606 " Hue", " Satu");
607 for (i = 0; i < VO_MAX_GRAPHICS_LAYER_NUM; i++) {
608 dev = g_hifb_gfx_layer_ctx[i].binded_dev;
609 if (g_ast_vo_dev[dev].vo_enable) {
610 csc = g_hifb_gfx_layer_ctx[i].gfx_csc;
611 osal_seq_printf(s, "%8u%8u%8u%8u%8u%8u\n", i, csc.csc_matrix, csc.luma, csc.contrast,
612 csc.hue, csc.satuature);
613 }
614 }
615
616 return HI_SUCCESS;
617 }
618
vou_graphics_enable_int(hi_u32 layer_index,hi_bool enable)619 hi_s32 vou_graphics_enable_int(hi_u32 layer_index, hi_bool enable)
620 {
621 vo_gfxlayer_context *vo_gfx_layer_ctx = HI_NULL;
622 vo_dev_info *vo_dev = HI_NULL;
623 hifb_vo_dev dev;
624 vo_gfx_layer_ctx = &g_hifb_gfx_layer_ctx[layer_index];
625
626 if (!vo_gfx_layer_ctx->binded) {
627 hifb_graphics_trace(HI_DBG_ERR, "graphics layer %u has not been binded!\n", layer_index);
628 return HI_ERR_VO_GFX_NOT_BIND;
629 }
630 dev = vo_gfx_layer_ctx->binded_dev;
631 vo_dev = &g_ast_vo_dev[dev];
632
633 if (vo_dev->vo_enable == HI_FALSE) {
634 hifb_graphics_trace(HI_DBG_ERR, "Open Int Error:The vo device (%d) for graphics layer %u has been disable!\n",
635 dev, layer_index);
636 return HI_FAILURE;
637 }
638
639 graphic_drv_dev_int_enable(dev, enable);
640 return HI_SUCCESS;
641 }
642
vou_graphics_clear_int(hi_u32 int_clear,hi_s32 irq)643 hi_bool vou_graphics_clear_int(hi_u32 int_clear, hi_s32 irq)
644 {
645 graphic_drv_int_clear(int_clear, irq);
646 return HI_SUCCESS;
647 }
648
vou_graphics_get_int(hi_u32 * int_staus)649 hi_bool vou_graphics_get_int(hi_u32 *int_staus)
650 {
651 *int_staus = graphic_drv_int_get_status();
652 return HI_SUCCESS;
653 }
654
vou_graphics_clear_int_status(hi_u32 int_status)655 hi_bool vou_graphics_clear_int_status(hi_u32 int_status)
656 {
657 graphic_drv_clr_int_status(int_status);
658 return HI_SUCCESS;
659 }
660
vou_graphics_get_interrupt_dev(hi_u32 int_status,hifb_vo_dev * vo_dev)661 hi_s32 vou_graphics_get_interrupt_dev(hi_u32 int_status, hifb_vo_dev *vo_dev)
662 {
663 return graphic_drv_get_interrupt_dev(int_status, vo_dev);
664 }
665