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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_1_0_sh_mask.h26 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
27 #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
28 #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L
29 #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004
30 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L
31 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014
32 #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L
33 #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018
34 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
35 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_3_0_sh_mask.h26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_sh_mask.h26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
[all …]
/kernel/linux/linux-5.10/drivers/staging/gdm724x/
Dhci_packet.h15 #define NIC_TYPE_NIC0 0x00000010
16 #define NIC_TYPE_NIC1 0x00000011
17 #define NIC_TYPE_NIC2 0x00000012
18 #define NIC_TYPE_NIC3 0x00000013
19 #define NIC_TYPE_ARP 0x00000100
20 #define NIC_TYPE_ICMPV6 0x00000200
21 #define NIC_TYPE_MASK 0x0000FFFF
22 #define NIC_TYPE_F_IPV4 0x00010000
23 #define NIC_TYPE_F_IPV6 0x00020000
24 #define NIC_TYPE_F_DHCP 0x00040000
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/kernel/linux/patches/linux-4.19/prebuilts/usr/include/asm-arm/asm/
Dptrace.h25 #define PTRACE_GETFDPIC_EXEC 0
27 #define USR26_MODE 0x00000000
28 #define FIQ26_MODE 0x00000001
29 #define IRQ26_MODE 0x00000002
30 #define SVC26_MODE 0x00000003
31 #define USR_MODE 0x00000010
32 #define SVC_MODE 0x00000013
33 #define FIQ_MODE 0x00000011
34 #define IRQ_MODE 0x00000012
35 #define MON_MODE 0x00000016
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/kernel/linux/linux-5.10/arch/riscv/include/asm/
Dftrace.h50 #define JALR_SIGN_MASK (0x00000800)
51 #define JALR_OFFSET_MASK (0x00000fff)
52 #define AUIPC_OFFSET_MASK (0xfffff000)
53 #define AUIPC_PAD (0x00001000)
55 #define JALR_BASIC (0x000080e7)
56 #define AUIPC_BASIC (0x00000097)
57 #define NOP4 (0x00000013)
61 call[0] = to_auipc_insn((unsigned int)((unsigned long)callee - \
65 } while (0)
/kernel/linux/linux-5.10/drivers/soc/atmel/
Dsoc.h35 #define AT91RM9200_CIDR_MATCH 0x09290780
37 #define AT91SAM9260_CIDR_MATCH 0x019803a0
38 #define AT91SAM9261_CIDR_MATCH 0x019703a0
39 #define AT91SAM9263_CIDR_MATCH 0x019607a0
40 #define AT91SAM9G20_CIDR_MATCH 0x019905a0
41 #define AT91SAM9RL64_CIDR_MATCH 0x019b03a0
42 #define AT91SAM9G45_CIDR_MATCH 0x019b05a0
43 #define AT91SAM9X5_CIDR_MATCH 0x019a05a0
44 #define AT91SAM9N12_CIDR_MATCH 0x019a07a0
45 #define SAM9X60_CIDR_MATCH 0x019b35a0
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Ddmacgp102.c37 nvkm_wr32(device, 0x611494 + (ctrl * 0x0010), chan->push); in gp102_disp_dmac_init()
38 nvkm_wr32(device, 0x611498 + (ctrl * 0x0010), 0x00010000); in gp102_disp_dmac_init()
39 nvkm_wr32(device, 0x61149c + (ctrl * 0x0010), 0x00000001); in gp102_disp_dmac_init()
40 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000010, 0x00000010); in gp102_disp_dmac_init()
41 nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), chan->suspend_put); in gp102_disp_dmac_init()
42 nvkm_wr32(device, 0x610490 + (ctrl * 0x0010), 0x00000013); in gp102_disp_dmac_init()
46 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x80000000)) in gp102_disp_dmac_init()
48 ) < 0) { in gp102_disp_dmac_init()
50 nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); in gp102_disp_dmac_init()
54 return 0; in gp102_disp_dmac_init()
Ddmacgv100.c31 const u32 soff = (chan->chid.ctrl - 1) * 0x04; in gv100_disp_dmac_idle()
33 u32 stat = nvkm_rd32(device, 0x610664 + soff); in gv100_disp_dmac_idle()
34 if ((stat & 0x000f0000) == 0x00040000) in gv100_disp_dmac_idle()
35 return 0; in gv100_disp_dmac_idle()
46 chan->chid.user << 25 | 0x00000040); in gv100_disp_dmac_bind()
53 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; in gv100_disp_dmac_fini()
54 const u32 coff = chan->chid.ctrl * 0x04; in gv100_disp_dmac_fini()
55 nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000000); in gv100_disp_dmac_fini()
57 nvkm_mask(device, 0x6104e0 + coff, 0x00000002, 0x00000000); in gv100_disp_dmac_fini()
58 chan->suspend_put = nvkm_rd32(device, 0x690000 + uoff); in gv100_disp_dmac_fini()
[all …]
Ddmacgf119.c35 chan->chid.user << 27 | 0x00000001); in gf119_disp_dmac_bind()
47 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00001010, 0x00001000); in gf119_disp_dmac_fini()
48 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000003, 0x00000000); in gf119_disp_dmac_fini()
50 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x001e0000)) in gf119_disp_dmac_fini()
52 ) < 0) { in gf119_disp_dmac_fini()
54 nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); in gf119_disp_dmac_fini()
57 chan->suspend_put = nvkm_rd32(device, 0x640000 + (ctrl * 0x1000)); in gf119_disp_dmac_fini()
69 nvkm_wr32(device, 0x610494 + (ctrl * 0x0010), chan->push); in gf119_disp_dmac_init()
70 nvkm_wr32(device, 0x610498 + (ctrl * 0x0010), 0x00010000); in gf119_disp_dmac_init()
71 nvkm_wr32(device, 0x61049c + (ctrl * 0x0010), 0x00000001); in gf119_disp_dmac_init()
[all …]
Ddmacnv50.c54 if (nvkm_memory_size(chan->memory) < 0x1000) in nv50_disp_dmac_new_()
58 case NVKM_MEM_TARGET_VRAM: chan->push = 0x00000001; break; in nv50_disp_dmac_new_()
59 case NVKM_MEM_TARGET_NCOH: chan->push = 0x00000002; break; in nv50_disp_dmac_new_()
60 case NVKM_MEM_TARGET_HOST: chan->push = 0x00000003; break; in nv50_disp_dmac_new_()
66 return 0; in nv50_disp_dmac_new_()
88 nvkm_mask(device, 0x610200 + (ctrl * 0x0010), 0x00001010, 0x00001000); in nv50_disp_dmac_fini()
89 nvkm_mask(device, 0x610200 + (ctrl * 0x0010), 0x00000003, 0x00000000); in nv50_disp_dmac_fini()
91 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x001e0000)) in nv50_disp_dmac_fini()
93 ) < 0) { in nv50_disp_dmac_fini()
95 nvkm_rd32(device, 0x610200 + (ctrl * 0x10))); in nv50_disp_dmac_fini()
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-apalis-emc.dtsi94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_sh_mask.h26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL
27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000
28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL
29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000
30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000
34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/
Dvega10_enum.h51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
184 NO_FORCE_REQUEST = 0x00000000,
185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187 FORCE_SHUT_DOWN_REQUEST = 0x00000003,
195 NO_FORCE_REQ = 0x00000000,
196 FORCE_LIGHT_SLEEP_REQ = 0x00000001,
204 ENABLE_MEM_PWR_CTRL = 0x00000000,
205 DISABLE_MEM_PWR_CTRL = 0x00000001,
213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/thermal/
Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_sh_mask.h26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Dbtc_dpm.c36 #define MC_CG_ARB_FREQ_F0 0x0a
37 #define MC_CG_ARB_FREQ_F1 0x0b
38 #define MC_CG_ARB_FREQ_F2 0x0c
39 #define MC_CG_ARB_FREQ_F3 0x0d
41 #define MC_CG_SEQ_DRAMCONF_S0 0x05
42 #define MC_CG_SEQ_DRAMCONF_S1 0x06
43 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
44 #define MC_CG_SEQ_YCLK_RESUME 0x0a
46 #define SMC_RAM_END 0x8000
61 0x000008f8, 0x00000010, 0xffffffff,
[all …]
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
Dlirc.h10 #define PULSE_BIT 0x01000000
11 #define PULSE_MASK 0x00FFFFFF
12 #define LIRC_MODE2_SPACE 0x00000000
13 #define LIRC_MODE2_PULSE 0x01000000
14 #define LIRC_MODE2_FREQUENCY 0x02000000
15 #define LIRC_MODE2_TIMEOUT 0x03000000
16 #define LIRC_VALUE_MASK 0x00FFFFFF
17 #define LIRC_MODE2_MASK 0xFF000000
33 #define LIRC_MODE_RAW 0x00000001
34 #define LIRC_MODE_PULSE 0x00000002
[all …]
/kernel/linux/patches/linux-5.10/prebuilts/usr/include/asm-arm/asm/
Dptrace.h38 #define PTRACE_GETFDPIC_EXEC 0
40 #define USR26_MODE 0x00000000
41 #define FIQ26_MODE 0x00000001
42 #define IRQ26_MODE 0x00000002
43 #define SVC26_MODE 0x00000003
44 #define USR_MODE 0x00000010
45 #define SVC_MODE 0x00000013
46 #define FIQ_MODE 0x00000011
47 #define IRQ_MODE 0x00000012
48 #define MON_MODE 0x00000016
[all …]
/kernel/linux/linux-5.10/arch/arm/include/uapi/asm/
Dptrace.h37 #define PTRACE_GETFDPIC_EXEC 0
44 #define USR26_MODE 0x00000000
45 #define FIQ26_MODE 0x00000001
46 #define IRQ26_MODE 0x00000002
47 #define SVC26_MODE 0x00000003
50 * Use 0 here to get code right that creates a userspace
53 #define USR_MODE 0x00000000
54 #define SVC_MODE 0x00000000
56 #define USR_MODE 0x00000010
57 #define SVC_MODE 0x00000013
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/top/
Dgk104.c35 for (i = 0; i < 64; i++) { in gk104_top_oneinit()
39 type = ~0; in gk104_top_oneinit()
40 inst = 0; in gk104_top_oneinit()
43 data = nvkm_rd32(device, 0x022700 + (i * 0x04)); in gk104_top_oneinit()
45 switch (data & 0x00000003) { in gk104_top_oneinit()
46 case 0x00000000: /* NOT_VALID */ in gk104_top_oneinit()
48 case 0x00000001: /* DATA */ in gk104_top_oneinit()
49 inst = (data & 0x3c000000) >> 26; in gk104_top_oneinit()
50 info->addr = (data & 0x00fff000); in gk104_top_oneinit()
51 if (data & 0x00000004) in gk104_top_oneinit()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_6_1_default.h26 #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000
29 #define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000
30 #define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000
31 #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000
32 #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000
34 #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000
[all …]

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