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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dgk104.c36 { 0x100d10, 1, 0x0000c244 },
37 { 0x100d30, 1, 0x0000c242 },
38 { 0x100d3c, 1, 0x00000242 },
39 { 0x100d48, 1, 0x00000242 },
40 { 0x100d1c, 1, 0x00000042 },
46 { 0x100c98, 1, 0x00000242 },
52 { 0x10f000, 1, 0x00000042 },
53 { 0x17e030, 1, 0x00000044 },
54 { 0x17e040, 1, 0x00000044 },
60 { 0x17ea60, 4, 0x00000044 },
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/hdmi/
Dhdmi.xml.h50 HDCP_KEYS_STATE_NO_KEYS = 0,
61 DDC_WRITE = 0,
66 ACR_NONE = 0,
72 #define REG_HDMI_CTRL 0x00000000
73 #define HDMI_CTRL_ENABLE 0x00000001
74 #define HDMI_CTRL_HDMI 0x00000002
75 #define HDMI_CTRL_ENCRYPTED 0x00000004
77 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
78 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
80 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
/kernel/linux/linux-5.10/drivers/staging/media/rkisp1/
Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI BIT(0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dp/
Ddp_reg.h10 #define REG_DP_HW_VERSION (0x00000000)
12 #define REG_DP_SW_RESET (0x00000010)
13 #define DP_SW_RESET (0x00000001)
15 #define REG_DP_PHY_CTRL (0x00000014)
16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
17 #define DP_PHY_CTRL_SW_RESET (0x00000004)
19 #define REG_DP_CLK_CTRL (0x00000018)
20 #define REG_DP_CLK_ACTIVE (0x0000001C)
21 #define REG_DP_INTR_STATUS (0x00000020)
22 #define REG_DP_INTR_STATUS2 (0x00000024)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/include/nvhw/class/
Dcl006c.h27 #define NV06C_PUT (0x00000040)
29 #define NV06C_GET (0x00000044)
37 #define NV06C_OPCODE_METHOD (0x00000000)
38 #define NV06C_OPCODE_NONINC_METHOD (0x00000002)
41 #define NV06C_DATA 31:0
44 #define NV06C_OPCODE_JUMP (0x00000001)
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/
Dar9330_1p2_initvals.h45 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
46 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
47 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
48 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
49 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
50 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
51 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
52 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
53 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
54 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
[all …]
Dar9330_1p1_initvals.h27 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
28 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
29 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
30 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
31 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
32 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
33 {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
34 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
35 {0x00009e04, 0x00202020, 0x00202020, 0x00202020, 0x00202020},
36 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
[all …]
Dar9485_initvals.h31 {0x00009e00, 0x037216a0},
32 {0x00009e04, 0x00182020},
33 {0x00009e18, 0x00000000},
34 {0x00009e20, 0x000003a8},
35 {0x00009e2c, 0x00004121},
36 {0x00009e44, 0x02282324},
37 {0x0000a000, 0x00060005},
38 {0x0000a004, 0x00810080},
39 {0x0000a008, 0x00830082},
40 {0x0000a00c, 0x00850084},
[all …]
Dar9462_2p1_initvals.h63 {0x00000008, 0x00000000},
64 {0x00000030, 0x000e0085},
65 {0x00000034, 0x00000005},
66 {0x00000040, 0x00000000},
67 {0x00000044, 0x00000000},
68 {0x00000048, 0x00000008},
69 {0x0000004c, 0x00000010},
70 {0x00000050, 0x00000000},
71 {0x00001040, 0x002ffc0f},
72 {0x00001044, 0x002ffc0f},
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/tegra/
Dfalcon.h11 #define FALCON_UCLASS_METHOD_OFFSET 0x00000040
13 #define FALCON_UCLASS_METHOD_DATA 0x00000044
15 #define FALCON_IRQMSET 0x00001010
21 #define FALCON_IRQMSET_EXT(v) (((v) & 0xff) << 8)
23 #define FALCON_IRQDEST 0x0000101c
28 #define FALCON_IRQDEST_EXT(v) (((v) & 0xff) << 8)
30 #define FALCON_ITFEN 0x00001048
31 #define FALCON_ITFEN_CTXEN (1 << 0)
34 #define FALCON_IDLESTATE 0x0000104c
36 #define FALCON_CPUCTL 0x00001100
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h50 NON_BURST_SYNCH_PULSE = 0,
56 VID_DST_FORMAT_RGB565 = 0,
63 SWAP_RGB = 0,
72 TRIGGER_NONE = 0,
81 CMD_DST_FORMAT_RGB111 = 0,
90 LANE_SWAP_0123 = 0,
100 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
101 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
102 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
103 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/thermal/
Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/kernel/linux/linux-5.10/drivers/crypto/amcc/
Dcrypto4xx_reg_def.h15 #define CRYPTO4XX_DESCRIPTOR 0x00000000
16 #define CRYPTO4XX_CTRL_STAT 0x00000000
17 #define CRYPTO4XX_SOURCE 0x00000004
18 #define CRYPTO4XX_DEST 0x00000008
19 #define CRYPTO4XX_SA 0x0000000C
20 #define CRYPTO4XX_SA_LENGTH 0x00000010
21 #define CRYPTO4XX_LENGTH 0x00000014
23 #define CRYPTO4XX_PE_DMA_CFG 0x00000040
24 #define CRYPTO4XX_PE_DMA_STAT 0x00000044
25 #define CRYPTO4XX_PDR_BASE 0x00000048
[all …]
/kernel/linux/linux-5.10/include/linux/mmc/
Dsh_mmcif.h33 u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
38 #define MMCIF_CE_CMD_SET 0x00000000
39 #define MMCIF_CE_ARG 0x00000008
40 #define MMCIF_CE_ARG_CMD12 0x0000000C
41 #define MMCIF_CE_CMD_CTRL 0x00000010
42 #define MMCIF_CE_BLOCK_SET 0x00000014
43 #define MMCIF_CE_CLK_CTRL 0x00000018
44 #define MMCIF_CE_BUF_ACC 0x0000001C
45 #define MMCIF_CE_RESP3 0x00000020
46 #define MMCIF_CE_RESP2 0x00000024
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv50.c42 if (ret == 0) { in nv50_mpeg_cclass_bind()
44 nvkm_wo32(*pgpuobj, 0x70, 0x00801ec1); in nv50_mpeg_cclass_bind()
45 nvkm_wo32(*pgpuobj, 0x7c, 0x0000037c); in nv50_mpeg_cclass_bind()
65 u32 stat = nvkm_rd32(device, 0x00b100); in nv50_mpeg_intr()
66 u32 type = nvkm_rd32(device, 0x00b230); in nv50_mpeg_intr()
67 u32 mthd = nvkm_rd32(device, 0x00b234); in nv50_mpeg_intr()
68 u32 data = nvkm_rd32(device, 0x00b238); in nv50_mpeg_intr()
71 if (stat & 0x01000000) { in nv50_mpeg_intr()
73 if (type == 0x00000020 && mthd == 0x0000) { in nv50_mpeg_intr()
74 nvkm_wr32(device, 0x00b308, 0x00000100); in nv50_mpeg_intr()
[all …]
/kernel/linux/linux-5.10/include/linux/
Datmel-ssc.h33 #define SSC_CR 0x00000000
37 #define SSC_CR_RXEN_OFFSET 0
46 #define SSC_CMR 0x00000004
48 #define SSC_CMR_DIV_OFFSET 0
51 #define SSC_RCMR 0x00000010
59 #define SSC_RCMR_CKS_OFFSET 0
70 #define SSC_RFMR 0x00000014
72 #define SSC_RFMR_DATLEN_OFFSET 0
93 #define SSC_TCMR 0x00000018
101 #define SSC_TCMR_CKS_OFFSET 0
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/sti/bdisp/
Dbdisp-reg.h8 /* 0 - General */
87 #define BLT_CTL 0x0A00
88 #define BLT_ITS 0x0A04
89 #define BLT_STA1 0x0A08
90 #define BLT_AQ1_CTL 0x0A60
91 #define BLT_AQ1_IP 0x0A64
92 #define BLT_AQ1_LNA 0x0A68
93 #define BLT_AQ1_STA 0x0A6C
94 #define BLT_ITM0 0x0AD0
96 #define BLT_PLUGS1_OP2 0x0B04
[all …]
/kernel/linux/linux-5.10/arch/m68k/fpsp040/
Dutil.S41 EXT_PINF: .long 0x7fff0000,0x00000000,0x00000000,0x00000000
43 EXT_PLRG: .long 0x7ffe0000,0xffffffff,0xffffffff,0x00000000
45 SGL_PLRG: .long 0x407e0000,0xffffff00,0x00000000,0x00000000
47 DBL_PLRG: .long 0x43fe0000,0xffffffff,0xfffff800,0x00000000
88 | This entry point used by x_ovfl. (opclass 0 and 2)
107 andiw #0x00000060,%d0 |clear all bits except 6 and 5
108 cmpil #0x00000040,%d0
110 cmpil #0x00000060,%d0
113 andil #0x7f,%d0 |clear all except operation
114 cmpil #0x33,%d0
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/toshiba/
Dspider_net.h57 #define SPIDER_NET_GHIINT0STS 0x00000000
58 #define SPIDER_NET_GHIINT1STS 0x00000004
59 #define SPIDER_NET_GHIINT2STS 0x00000008
60 #define SPIDER_NET_GHIINT0MSK 0x00000010
61 #define SPIDER_NET_GHIINT1MSK 0x00000014
62 #define SPIDER_NET_GHIINT2MSK 0x00000018
64 #define SPIDER_NET_GRESUMINTNUM 0x00000020
65 #define SPIDER_NET_GREINTNUM 0x00000024
67 #define SPIDER_NET_GFFRMNUM 0x00000028
68 #define SPIDER_NET_GFAFRMNUM 0x0000002c
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/edp/
Dedp.xml.h50 EDP_6BIT = 0,
58 EDP_RGB = 0,
63 #define REG_EDP_MAINLINK_CTRL 0x00000004
64 #define EDP_MAINLINK_CTRL_ENABLE 0x00000001
65 #define EDP_MAINLINK_CTRL_RESET 0x00000002
67 #define REG_EDP_STATE_CTRL 0x00000008
68 #define EDP_STATE_CTRL_TRAIN_PATTERN_1 0x00000001
69 #define EDP_STATE_CTRL_TRAIN_PATTERN_2 0x00000002
70 #define EDP_STATE_CTRL_TRAIN_PATTERN_3 0x00000004
71 #define EDP_STATE_CTRL_SYMBOL_ERR_RATE_MEAS 0x00000008
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
Dgf100.fuc3.h3 /* 0x0000: ctx_object */
4 0x00000000,
5 /* 0x0004: ctx_query_address_high */
6 0x00000000,
7 /* 0x0008: ctx_query_address_low */
8 0x00000000,
9 /* 0x000c: ctx_query_counter */
10 0x00000000,
11 /* 0x0010: ctx_src_address_high */
12 0x00000000,
[all …]
/kernel/linux/linux-5.10/arch/m68k/include/asm/
Dm528xsim.h24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
33 #define MCFINTC_IRLR 0x18 /* */
34 #define MCFINTC_IACKL 0x19 /* */
[all …]
/kernel/linux/linux-5.10/drivers/message/fusion/lsi/
Dmpi.h33 * 01-25-01 01.01.04 Changed MPI_VERSION_MINOR from 0x00 to 0x01.
44 * Changed MPI_VERSION_MINOR from 0x01 to 0x02.
99 #define MPI_VERSION_MAJOR (0x01)
100 #define MPI_VERSION_MINOR (0x05)
101 #define MPI_VERSION_MAJOR_MASK (0xFF00)
103 #define MPI_VERSION_MINOR_MASK (0x00FF)
104 #define MPI_VERSION_MINOR_SHIFT (0)
108 #define MPI_VERSION_01_00 (0x0100)
109 #define MPI_VERSION_01_01 (0x0101)
110 #define MPI_VERSION_01_02 (0x0102)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dsdma_v5_0.c55 #define SDMA1_REG_OFFSET 0x600
56 #define SDMA0_HYP_DEC_REG_START 0x5880
57 #define SDMA0_HYP_DEC_REG_END 0x5893
58 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
66 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
67 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac1000.h14 #define GMAC_CONTROL 0x00000000 /* Configuration */
15 #define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */
16 #define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */
17 #define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */
18 #define GMAC_MII_ADDR 0x00000010 /* MII Address */
19 #define GMAC_MII_DATA 0x00000014 /* MII Data */
20 #define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */
21 #define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */
22 #define GMAC_DEBUG 0x00000024 /* GMAC debug register */
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
[all …]

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