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/kernel/linux/linux-5.10/include/uapi/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
42 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
[all …]
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
45 #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
46 #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
57 /* Media-dependent registers. */
58 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
59 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
60 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
61 * Lanes B-D are numbered 134-136. */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb/
Dmv88e1xxx.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 #define MII_GBCR 9 /* 1000Base-T control register */
19 #define MII_GBSR 10 /* 1000Base-T status register */
21 /* 1000Base-T control register fields */
28 /* 1000Base-T status register fields */
72 #define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE) argument
73 #define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE) argument
81 #define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT) argument
82 #define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT) argument
108 #define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN) argument
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/ti/
Dnetcp_sgmii.c1 // SPDX-License-Identifier: GPL-2.0
7 * Sandeep Paulraj <s-paulraj@ti.com>
8 * Wingman Kwok <w-kwok2@ti.com>
22 #define SGMII23_OFFSET(x) ((x - 2) * 0x100) argument
23 #define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : (SGMII23_OFFSET(x))) argument
26 #define SGMII_SRESET_REG(x) (SGMII_OFFSET(x) + 0x004) argument
27 #define SGMII_CTL_REG(x) (SGMII_OFFSET(x) + 0x010) argument
28 #define SGMII_STATUS_REG(x) (SGMII_OFFSET(x) + 0x014) argument
29 #define SGMII_MRADV_REG(x) (SGMII_OFFSET(x) + 0x018) argument
31 static void sgmii_write_reg(void __iomem *base, int reg, u32 val) in sgmii_write_reg() argument
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Dsfp-bus.c1 // SPDX-License-Identifier: GPL-2.0-only
20 * struct sfp_bus - internal representation of a sfp bus
50 /* Ubiquiti U-Fiber Instant module claims that support all transceiver in sfp_quirk_ubnt_uf_instant()
52 * modes and set only one mode which module supports: 1000baseX_Full. in sfp_quirk_ubnt_uf_instant()
55 phylink_set(modes, 1000baseX_Full); in sfp_quirk_ubnt_uf_instant()
60 // Alcatel Lucent G-010S-P can operate at 2500base-X, but
66 // Alcatel Lucent G-010S-A can operate at 2500base-X, but
72 // Huawei MA5671A can operate at 2500base-X, but report 1.2GBd
79 .part = "UF-INSTANT",
111 vs = sfp_strlen(id->base.vendor_name, ARRAY_SIZE(id->base.vendor_name)); in sfp_lookup_quirk()
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
Di915_utils.h37 #define FDO_BUG_URL "https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs"
42 #define WARN_ON(x) ({ \
43 bool __i915_warn_cond = (x); \
46 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
48 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")") argument
52 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")") argument
54 #define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \ argument
55 __stringify(x), (long)(x))
79 #define i915_inject_probe_failure(i915) i915_inject_probe_error((i915), -ENODEV)
105 start__ >= max__ || size__ > max__ - start__; \
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/kernel/linux/linux-5.10/drivers/cpufreq/
Darmada-37xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
26 #include "cpufreq-dt.h"
66 #define ARMADA_37XX_AVS_VSET(x) (0x1C + 4 * (x)) argument
75 #define MIN_VOLT_MV 1000
109 /* {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, */
110 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
111 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
112 {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
132 static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base, in armada37xx_cpufreq_dvfs_setup() argument
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dvf610-zii-scu4-aib.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 // Copyright (C) 2016-2018 Zodiac Inflight Innovations
5 /dts-v1/;
10 compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610";
13 stdout-path = &uart0;
21 gpio-leds {
22 compatible = "gpio-leds";
23 pinctrl-0 = <&pinctrl_leds_debug>;
24 pinctrl-names = "default";
29 linux,default-trigger = "heartbeat";
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/atheros/atlx/
Datlx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* atlx_hw.h -- common hardware definitions for Attansic network drivers
4 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
5 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
6 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
10 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
26 #define SPEED_1000 1000
149 /* IRQ Anti-Lost Timer Initial Value Register */
228 /* MAC Half-Duplex Control Register */
246 /* Wake-On-Lan control register */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/arm/display/komeda/
Dkomeda_crtc.c1 // SPDX-License-Identifier: GPL-2.0
29 for_each_new_connector_in_state(crtc_st->state, conn, conn_st, i) { in komeda_crtc_get_color_config()
30 if (conn_st->crtc != crtc_st->crtc) in komeda_crtc_get_color_config()
33 conn_bpc = conn->display_info.bpc ? conn->display_info.bpc : 8; in komeda_crtc_get_color_config()
34 conn_color_formats &= conn->display_info.color_formats; in komeda_crtc_get_color_config()
52 if (!kcrtc_st->base.active) { in komeda_crtc_update_clock_ratio()
53 kcrtc_st->clock_ratio = 0; in komeda_crtc_update_clock_ratio()
57 pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL; in komeda_crtc_update_clock_ratio()
60 kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk); in komeda_crtc_update_clock_ratio()
64 * komeda_crtc_atomic_check - build display output data flow
[all …]
/kernel/linux/linux-5.10/drivers/pwm/
Dpwm-hibvt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #define PWM_CFG0_ADDR(x) (((x) * 0x20) + 0x0) argument
19 #define PWM_CFG1_ADDR(x) (((x) * 0x20) + 0x4) argument
20 #define PWM_CFG2_ADDR(x) (((x) * 0x20) + 0x8) argument
21 #define PWM_CTRL_ADDR(x) (((x) * 0x20) + 0xC) argument
38 void __iomem *base; member
71 static void hibvt_pwm_set_bits(void __iomem *base, u32 offset, in hibvt_pwm_set_bits() argument
74 void __iomem *address = base + offset; in hibvt_pwm_set_bits()
87 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
95 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
[all …]
/kernel/linux/linux-5.10/drivers/ide/
Dqd65xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1996-2001 Linus Torvalds & author (see below)
7 * Version 0.03 Cleaned auto-tune, added probe
20 * Samuel Thibault <samuel.thibault@ens-lyon.org>
40 * I/O ports are 0x30-0x31 (and 0x32-0x33 for qd6580)
41 * or 0xb0-0xb1 (and 0xb2-0xb3 for qd6580)
42 * -- qd6500 is a single IDE interface
43 * -- qd6580 is a dual IDE interface
51 * base: Timer1
54 * base+0x01: Config (R/O)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Drs690.c42 for (i = 0; i < rdev->usec_timeout; i++) { in rs690_mc_wait_for_idle()
49 return -1; in rs690_mc_wait_for_idle()
74 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, in rs690_pm_info()
76 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); in rs690_pm_info()
82 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); in rs690_pm_info()
83 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); in rs690_pm_info()
84 if (le16_to_cpu(info->info.usK8MemoryClock)) in rs690_pm_info()
85 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); in rs690_pm_info()
86 else if (rdev->clock.default_mclk) { in rs690_pm_info()
87 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); in rs690_pm_info()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
Dauxgm200.c24 #define gm200_i2c_aux(p) container_of((p), struct gm200_i2c_aux, base)
28 struct nvkm_i2c_aux base; member
35 struct nvkm_device *device = aux->base.pad->i2c->subdev.device; in gm200_i2c_aux_fini()
36 nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00710000, 0x00000000); in gm200_i2c_aux_fini()
42 struct nvkm_device *device = aux->base.pad->i2c->subdev.device; in gm200_i2c_aux_init()
49 timeout = 1000; in gm200_i2c_aux_init()
51 ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50)); in gm200_i2c_aux_init()
53 if (!timeout--) { in gm200_i2c_aux_init()
54 AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl); in gm200_i2c_aux_init()
55 return -EBUSY; in gm200_i2c_aux_init()
[all …]
Dauxg94.c24 #define g94_i2c_aux(p) container_of((p), struct g94_i2c_aux, base)
28 struct nvkm_i2c_aux base; member
35 struct nvkm_device *device = aux->base.pad->i2c->subdev.device; in g94_i2c_aux_fini()
36 nvkm_mask(device, 0x00e4e4 + (aux->ch * 0x50), 0x00310000, 0x00000000); in g94_i2c_aux_fini()
42 struct nvkm_device *device = aux->base.pad->i2c->subdev.device; in g94_i2c_aux_init()
49 timeout = 1000; in g94_i2c_aux_init()
51 ctrl = nvkm_rd32(device, 0x00e4e4 + (aux->ch * 0x50)); in g94_i2c_aux_init()
53 if (!timeout--) { in g94_i2c_aux_init()
54 AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl); in g94_i2c_aux_init()
55 return -EBUSY; in g94_i2c_aux_init()
[all …]
/kernel/linux/linux-5.10/drivers/i2c/busses/
Di2c-mt7621.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/i2c/busses/i2c-mt7621.c
9 * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
47 #define SM0CTL1_PGLEN(x) ((((x) - 1) << 8) & SM0CTL1_PGLEN_MASK) argument
57 #define TIMEOUT_MS 1000
60 void __iomem *base; member
74 ret = readl_relaxed_poll_timeout(i2c->base + REG_SM0CTL1_REG, in mtk_i2c_wait_idle()
76 10, TIMEOUT_MS * 1000); in mtk_i2c_wait_idle()
78 dev_dbg(i2c->dev, "idle err(%d)\n", ret); in mtk_i2c_wait_idle()
87 ret = device_reset(i2c->adap.dev.parent); in mtk_i2c_reset()
[all …]
Di2c-highlander.c1 // SPDX-License-Identifier: GPL-2.0
42 void __iomem *base; member
52 static int iic_timeout = 1000, iic_read_delay;
56 iowrite16(ioread16(dev->base + SMCR) | SMCR_IEIC, dev->base + SMCR); in highlander_i2c_irq_enable()
61 iowrite16(ioread16(dev->base + SMCR) & ~SMCR_IEIC, dev->base + SMCR); in highlander_i2c_irq_disable()
66 iowrite16(ioread16(dev->base + SMCR) | SMCR_START, dev->base + SMCR); in highlander_i2c_start()
71 iowrite16(ioread16(dev->base + SMCR) | SMCR_IRIC, dev->base + SMCR); in highlander_i2c_done()
78 smmr = ioread16(dev->base + SMMR); in highlander_i2c_setup()
86 iowrite16(smmr, dev->base + SMMR); in highlander_i2c_setup()
91 for (; len > 1; len -= 2) { in smbus_write_data()
[all …]
/kernel/linux/linux-5.10/Documentation/admin-guide/pm/
Dintel-speed-select.rst1 .. SPDX-License-Identifier: GPL-2.0
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
49 The top-level help describes arguments and features. Notice that there is a
[all …]
/kernel/linux/linux-5.10/drivers/scsi/pcmcia/
Dnsp_cs.c3 NinjaSCSI-3 / NinjaSCSI-32Bi PCMCIA SCSI host adapter card driver
21 I-O DATA PCSC-F (Workbit NinjaSCSI-3)
22 "WBT", "NinjaSCSI-3", "R1.0"
23 I-O DATA CBSC-II (Workbit NinjaSCSI-32Bi in 16bit mode)
57 MODULE_DESCRIPTION("WorkBit NinjaSCSI-3 / NinjaSCSI-32Bi(16bit) PCMCIA SCSI host adapter module");
78 .name = "WorkBit NinjaSCSI-3/32Bi(16bit)",
87 .dma_boundary = PAGE_SIZE - 1,
90 static nsp_hw_data nsp_data_base; /* attach <-> detect glue */
165 printk("nsp_cs-debug: 0x%x %s (%d): %s\n", mask, func, line, buf); in nsp_cs_dmessage()
174 * You must be set SCpnt->result before call this function.
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/pll/
Ddsi_pll_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 * DSI PLL 14nm - clock diagram (eg: DSI0):
18 * +----+ | +----+
19 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
20 * +----+ | +----+
22 * | +----+ |
23 * o---| /2 |--o--|\
24 * | +----+ | \ +----+
25 * | | |--| n2 |-- dsi0pll
[all …]
/kernel/linux/linux-5.10/drivers/s390/net/
Dqeth_ethtool.c1 // SPDX-License-Identifier: GPL-2.0
90 struct qeth_card *card = dev->ml_priv; in qeth_get_sset_count()
95 card->qdio.no_out_queues * TXQ_STATS_LEN; in qeth_get_sset_count()
97 return -EINVAL; in qeth_get_sset_count()
104 struct qeth_card *card = dev->ml_priv; in qeth_get_ethtool_stats()
107 qeth_add_stat_data(&data, &card->stats, card_stats, CARD_STATS_LEN); in qeth_get_ethtool_stats()
108 for (i = 0; i < card->qdio.no_out_queues; i++) in qeth_get_ethtool_stats()
109 qeth_add_stat_data(&data, &card->qdio.out_qs[i]->stats, in qeth_get_ethtool_stats()
117 WRITE_ONCE(queue->coalesce_usecs, coal->tx_coalesce_usecs); in __qeth_set_coalesce()
118 WRITE_ONCE(queue->max_coalesced_frames, coal->tx_max_coalesced_frames); in __qeth_set_coalesce()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/oki-semi/pch_gbe/
Dpch_gbe_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
12 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
14 /* PHY 1000 MII Register/Bit Definitions */
21 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
25 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */
26 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */
34 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
41 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
61 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
Dselftest_rps.c1 // SPDX-License-Identifier: MIT
22 #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */
33 return -1; in cmp_u64()
45 return -1; in cmp_u32()
64 #define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x) in create_spin_counter() argument
68 u32 *base, *cs; in create_spin_counter() local
72 obj = i915_gem_object_create_internal(vm->i915, 64 << 10); in create_spin_counter()
76 end = obj->base.size / sizeof(u32) - 1; in create_spin_counter()
90 base = i915_gem_object_pin_map(obj, I915_MAP_WC); in create_spin_counter()
91 if (IS_ERR(base)) { in create_spin_counter()
[all …]
/kernel/linux/linux-5.10/arch/mips/cavium-octeon/executive/
Dcvmx-helper-sgmii.c7 * Copyright (C) 2003-2018 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
35 #include <asm/octeon/cvmx-config.h>
37 #include <asm/octeon/cvmx-helper.h>
38 #include <asm/octeon/cvmx-helper-board.h>
40 #include <asm/octeon/cvmx-gmxx-defs.h>
41 #include <asm/octeon/cvmx-pcsx-defs.h>
42 #include <asm/octeon/cvmx-pcsxx-defs.h>
54 const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000; in __cvmx_helper_sgmii_hardware_init_one_time()
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