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/kernel/linux/linux-5.10/Documentation/fb/
Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
16 # 12 chars 2 lines
18 # 2 chars 10 lines
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
39 # Scan Frequency 37.500 kHz 75.00 Hz
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
60 # Scan Frequency 43.269 kHz 85.00 Hz
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/kernel/linux/linux-5.10/include/sound/
Dasoundef.h19 #define IEC958_AES0_PRO_EMPHASIS (7<<2) /* mask - emphasis */
20 #define IEC958_AES0_PRO_EMPHASIS_NOTID (0<<2) /* emphasis not indicated */
21 #define IEC958_AES0_PRO_EMPHASIS_NONE (1<<2) /* none emphasis */
22 #define IEC958_AES0_PRO_EMPHASIS_5015 (3<<2) /* 50/15us emphasis */
23 #define IEC958_AES0_PRO_EMPHASIS_CCITT (7<<2) /* CCITT J.17 emphasis */
27 #define IEC958_AES0_PRO_FS_44100 (1<<6) /* 44.1kHz */
28 #define IEC958_AES0_PRO_FS_48000 (2<<6) /* 48kHz */
29 #define IEC958_AES0_PRO_FS_32000 (3<<6) /* 32kHz */
30 #define IEC958_AES0_CON_NOT_COPYRIGHT (1<<2) /* 0 = copyright, 1 = not copyright */
37 #define IEC958_AES1_PRO_MODE_STEREOPHONIC (2<<0) /* stereophonic - ch A is left */
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Demu10k1.h178 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
179 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
294 /* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */
310 #define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop …
311 #define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop …
317 /* 0x00000000 2-channel output. */
323 * bit 2: Lock P16V playback memory cache.
327 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
386 #define Z2 0x04 /* Filter delay memory 2 register */
414 #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
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Ddesignware_i2s.h16 * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
27 #define DW_I2S_SLAVE (1 << 2)
36 #define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2)
59 #define TWO_CHANNEL_SUPPORT 2 /* up to 2.0 */
/kernel/linux/linux-5.10/sound/ppc/
Dawacs.h60 #define MASK_ADDR2 (0x2 << 12) /* Expanded Data Mode Address 2 */
94 #define MASK_RECALIBRATE (0x1 << 2) /* Recalibrate */
112 #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */
113 #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */
114 #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */
115 #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
116 #define SAMPLERATE_16000 (0x4 << 3) /* 16 or 14.7 kHz */
117 #define SAMPLERATE_12000 (0x5 << 3) /* 12 or 11.025 kHz */
118 #define SAMPLERATE_9600 (0x6 << 3) /* 9.6 or 8.82 kHz */
119 #define SAMPLERATE_8000 (0x7 << 3) /* 8 or 7.35 kHz */
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/include/
Dgrph_object_ctrl_defs.h45 PANEL_8BIT_COLOR = 2,
122 uint32_t GREY_LEVEL:2;
128 uint32_t pixel_clk; /* in KHz */
160 uint32_t crystal_frequency; /* in KHz */
161 uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */
162 uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */
163 uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */
164 uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */
172 uint32_t default_display_engine_pll_frequency; /* in KHz */
173 uint32_t external_clock_source_frequency_for_dp; /* in KHz */
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dti,j721e-cpb-ivi-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
21 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
22 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
23 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
28 Clocking setup for 48KHz family:
35 Clocking setup for 44.1KHz family:
74 - description: Parent for CPB_McASP auxclk (for 48KHz)
75 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
77 - description: Parent for CPB_SCKI clock (for 48KHz)
78 - description: Parent for CPB_SCKI clock (for 44.1KHz)
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Dti,j721e-cpb-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
16 In order to support 48KHz and 44.1KHz family of sampling rates the parent
17 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
18 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
22 48KHz family:
26 44.1KHz family:
31 48KHz family:
84 - description: Parent for CPB_McASP auxclk (for 48KHz)
85 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
87 - description: Parent for CPB_SCKI clock (for 48KHz)
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/kernel/linux/linux-5.10/drivers/video/fbdev/core/
Dmodedb.c38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
39 { NULL, 70, 640, 400, 39721, 40, 24, 39, 9, 96, 2, 0,
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
43 { NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, 0,
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
47 { NULL, 56, 800, 600, 27777, 128, 24, 22, 1, 72, 2, 0,
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
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/kernel/linux/linux-5.10/Documentation/sound/cards/
Daudiophile-usb.rst31 The device has 4 audio interfaces, and 2 MIDI ports:
35 - This port supports 2 pairs of line-level audio inputs (1/4" TS and RCA)
48 * sample rate from 8kHz to 96kHz
57 * 16-bit/48kHz ==> 4 channels in + 4 channels out
61 * 24-bit/48kHz ==> 4 channels in + 2 channels out,
62 or 2 channels in + 4 channels out
66 * 24-bit/96kHz ==> 2 channels in _or_ 2 channels out (half duplex only)
129 * hw:1,2 is Do in AC3/DTS passthrough mode
135 One exception is the hw:1,2 port which was reported to be Little Endian
137 This has been fixed in kernel 2.6.23 and above and now the hw:1,2 interface
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/kernel/linux/linux-5.10/sound/pci/ca0106/
Dca0106.h34 * playback periods_min=2, periods_max=8
120 #define HCFG_PLAYBACK_ATTENUATION 0x00006000 /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12…
124 #define HCFG_8_CHANNEL_PLAY 0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/
125 #define HCFG_8_CHANNEL_CAPTURE 0x00000100 /* 1 = 8 channels, 0 = 2 channels per substream.*/
137 /* Here pins 0,1,2,3,4,,6 are output. 5,7 are input */
144 * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit.
203 * Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
208 * The jack has 4 poles. I will call 1 - Tip, 2 - Next to 1, 3 - Next to 2, 4 - Next to 3
209 * For Analogue: 1 -> Center Speaker, 2 -> Sub Woofer, 3 -> Ground, 4 -> Ground
210 * For Digital: 1 -> Front SPDIF, 2 -> Rear SPDIF, 3 -> Center/Subwoofer SPDIF, 4 -> Ground.
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/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
Dmxl5xx_defs.h13 * version 2, as published by the Free Software Foundation.
39 MXL_HYDRA_DEV_SET_OVERWRITE_DEF_CMD = 2,
132 #define MXL_HYDRA_I2C_HDR_SIZE (2 * sizeof(u8)) /* PLID + LEN(0xFF) */
137 #define MXL_HYDRA_SKU_ID_585 2
146 #define MXL_HYDRA_REG_WRITE_LEN (MXL_HYDRA_I2C_HDR_SIZE + (2 * MXL_HYDRA_REG_SIZE_IN_BYTES))
195 cmd_buff[2] = size; \
400 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
402 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
403 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
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/kernel/linux/linux-5.10/include/linux/
Dclocksource.h144 * mult/2^shift = ns/cyc in clocksource_freq2mult()
145 * mult = ns/cyc * 2^shift in clocksource_freq2mult()
146 * mult = from/freq * 2^shift in clocksource_freq2mult()
147 * mult = from * 2^shift / freq in clocksource_freq2mult()
152 tmp += freq/2; /* round for do_div */ in clocksource_freq2mult()
159 * clocksource_khz2mult - calculates mult from khz and shift
160 * @khz: Clocksource frequency in KHz
163 * Helper functions that converts a khz counter frequency to a timsource
166 static inline u32 clocksource_khz2mult(u32 khz, u32 shift_constant) in clocksource_khz2mult() argument
168 return clocksource_freq2mult(khz, shift_constant, NSEC_PER_MSEC); in clocksource_khz2mult()
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/kernel/linux/linux-5.10/drivers/cpufreq/
Dpowernow-k6.c26 static unsigned int busfreq; /* FSB, in 10 kHz */
36 MODULE_PARM_DESC(bus_frequency, "Bus frequency in kHz");
51 static const u8 index_to_register[8] = { 6, 3, 1, 0, 2, 7, 5, 4 };
52 static const u8 register_to_index[8] = { 3, 2, 4, 1, 7, 6, 0, 5 };
157 unsigned khz; in powernow_k6_cpu_init() local
163 khz = cpu_khz; in powernow_k6_cpu_init()
165 if (khz >= usual_frequency_table[i].freq - FREQ_RANGE && in powernow_k6_cpu_init()
166 khz <= usual_frequency_table[i].freq + FREQ_RANGE) { in powernow_k6_cpu_init()
167 khz = usual_frequency_table[i].freq; in powernow_k6_cpu_init()
184 khz); in powernow_k6_cpu_init()
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Dtegra194-cpufreq.c21 #define KHZ 1000 macro
24 #define US_DELAY_MIN 2
25 #define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ)
87 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); in map_ndiv_to_freq()
99 * It will take = 2 ^ 32 / 408 MHz to overflow ref clk counter in tegra_read_counters()
105 * It will take = 2 ^ 32 / 2000 MHz to overflow core clk counter in tegra_read_counters()
130 * - Return Kcycles/second, freq in KHz
137 * in KHz = (delta cycles * 408 * 10^3) / delta ref_clk_counter
140 * Returns freq in KHz on success, 0 if cpu is offline
180 return (rate_mhz * KHZ); /* in KHz */ in tegra194_get_speed_common()
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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Datombios.h60 #define ATOM_EXT_DAC 2
64 #define ATOM_CRTC3 2
75 #define ATOM_DCPLL 2
76 #define ATOM_PPLL0 2
86 #define ENCODER_REFCLK_SRC_DCPLL 2
95 #define ATOM_SCALER_EXPANSION 2
100 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
101 #define ATOM_LCD_BLON (ATOM_ENABLE+2)
122 #define ATOM_TV_NTSCJ 2
132 #define ATOM_DAC1_CV 2
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/
Datombios.h59 #define ATOM_EXT_DAC 2
63 #define ATOM_CRTC3 2
78 #define ATOM_DCPLL 2
79 #define ATOM_PPLL0 2
103 #define ENCODER_REFCLK_SRC_DCPLL 2
109 #define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode
114 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
115 #define ATOM_LCD_BLON (ATOM_ENABLE+2)
131 #define ATOM_TV_NTSCJ 2
141 #define ATOM_DAC1_CV 2
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgt215.c100 sdiv = ((sctl & 0x003f0000) >> 16) + 2; in read_clk()
101 return (sclk * 2) / sdiv; in read_clk()
171 case 2: in gt215_clk_read()
187 gt215_clk_info(struct nvkm_clk *base, int idx, u32 khz, in gt215_clk_info() argument
196 switch (khz) { in gt215_clk_info()
199 return khz; in gt215_clk_info()
202 return khz; in gt215_clk_info()
205 return khz; in gt215_clk_info()
208 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info()
209 oclk = (sclk * 2) / sdiv; in gt215_clk_info()
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Dnv40.c47 u32 ref = 27000, khz = 0; in read_pll_1() local
50 khz = ref * N / M; in read_pll_1()
52 return khz >> P; in read_pll_1()
66 u32 ref = 27000, khz = 0; in read_pll_2() local
69 khz = ref * N1 / M1; in read_pll_2()
72 khz = khz * N2 / M2; in read_pll_2()
74 khz = 0; in read_pll_2()
78 return khz >> P; in read_pll_2()
87 case 2: in read_clk()
124 nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz, in nv40_clk_calc_pll() argument
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/kernel/linux/linux-5.10/drivers/media/tuners/
Dtda9887.c276 "- 12.5 kHz", in dump_read_message()
277 "- 37.5 kHz", in dump_read_message()
278 "- 62.5 kHz", in dump_read_message()
279 "- 87.5 kHz", in dump_read_message()
280 "-112.5 kHz", in dump_read_message()
281 "-137.5 kHz", in dump_read_message()
282 "-162.5 kHz", in dump_read_message()
283 "-187.5 kHz [min]", in dump_read_message()
284 "+187.5 kHz [max]", in dump_read_message()
285 "+162.5 kHz", in dump_read_message()
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Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
30 0f 2c ?
41 1a d0 set frequency: 125 kHz scale, n*125 kHz
57 2a 13 ?
58 2b 01 ?
59 2c ea ?
60 2d 00 ?
61 2e 00 ? not used?
62 2f 00 ? not used?
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/kernel/linux/linux-5.10/arch/arm/plat-omap/
DKconfig25 bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2"
31 version 2 of the SmartReflex IP.
72 timer provides more intra-tick resolution than the 32KHz timer,
76 bool "Use 32KHz timer"
80 Select this option if you want to enable the OMAP 32KHz timer.
82 support for no tick during idle. The 32KHz timer provides less
83 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
/kernel/linux/linux-5.10/Documentation/hwmon/
Dlm85.rst92 The LM85 uses the 2-wire interface compatible with the SMBUS 2.0
108 transistor like the 2N3904.
133 for 3-wire and 2-wire mode. For this reason, the 2-wire fan modes are not
153 driven by a 22.5 kHz clock. This is a global mode, not per-PWM output,
154 which means that setting any PWM frequency above 11.3 kHz will switch
155 all 3 PWM outputs to a 22.5 kHz frequency. Conversely, setting any PWM
156 frequency below 11.3 kHz will switch all 3 PWM outputs to a frequency
179 The LM96000 supports additional high frequency PWM modes (22.5 kHz, 24 kHz,
180 25.7 kHz, 27.7 kHz and 30 kHz), which can be configured on a per-PWM basis.
213 sensors and therefore three zones (# 1, 2 and 3). Each zone has the following
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/kernel/linux/linux-5.10/sound/soc/codecs/
Dak4613.c25 #define PW_MGMT2 0x01 /* Power Management 2 */
28 #define CTRL2 0x04 /* Control 2 */
51 #define PMADC BIT(2)
70 #define DFS_MASK (3 << 2)
71 #define DFS_NORMAL_SPEED (0 << 2)
72 #define DFS_DOUBLE_SPEED (1 << 2)
73 #define DFS_QUAD_SPEED (2 << 2)
144 /* [0] - [2] are not supported */
197 SND_SOC_DAPM_DAC("DAC3", NULL, PW_MGMT3, 2, 0),
280 * Normal: [32kHz, 48kHz] : 256fs,384fs or 512fs in ak4613_hw_constraints()
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/kernel/linux/linux-5.10/sound/pci/emu10k1/
Dp16v.h8 * Output fixed at S32_LE, 2 channel to hw:0,0
15 * Use 2 channel output streams instead of 8 channel.
57 * Audigy 2 Chip: CA0102-IAT
60 * DAC: CS4382-K (8-channel, 24bit, 192Khz)
99 * 2 = Capture output 2.
101 * [3:2] Capture input 1 channel select. 0 = Capture output 0.
103 * 2 = Capture output 2.
105 * [5:4] Capture input 2 channel select. 0 = Capture output 0.
107 * 2 = Capture output 2.
111 * 2 = Capture output 2.
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