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/kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/
Dia_css_env.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * CSS-API host-code by the environment in which the CSS-API code runs.
52 /** Store an 8 bit value into an address in the CSS HW address space.
53 The address must be an 8 bit aligned address. */
55 /** Store a 16 bit value into an address in the CSS HW address space.
56 The address must be a 16 bit aligned address. */
58 /** Store a 32 bit value into an address in the CSS HW address space.
59 The address must be a 32 bit aligned address. */
61 /** Load an 8 bit value from an address in the CSS HW address
62 space. The address must be an 8 bit aligned address. */
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/kernel/linux/linux-5.10/arch/sparc/include/asm/
Dhypervisor.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * -----------------------------------------------
23 * -----------------------------------------------
25 * The second type are "hyper-fast traps" which encode the function
27 * numbers > 0x80. The register usage for hyper-fast traps is as
30 * -----------------------------------------------
36 * -----------------------------------------------
44 * defined below. So, for example, if a hyper-fast trap takes
49 * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits
63 #define HV_ENORADDR 2 /* Invalid real address */
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/kernel/linux/linux-5.10/arch/arm/mm/
Dtlb-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/tlb-v7.S
5 * Copyright (C) 1997-2002 Russell King
14 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
22 * Invalidate a range of TLB entries in the specified address space.
24 * - start - start address (may not be aligned)
25 * - end - end address (exclusive, may not be aligned)
26 * - vma - vma_struct describing address range
29 * - the "Invalidate single entry" instruction will invalidate
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Dtlb-v6.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/tlb-v6.S
5 * Copyright (C) 1997-2002 Russell King
12 #include <asm/asm-offsets.h>
16 #include "proc-macros.S"
23 * Invalidate a range of TLB entries in the specified address space.
25 * - start - start address (may not be aligned)
26 * - end - end address (exclusive, may not be aligned)
27 * - vma - vma_struct describing address range
30 * - the "Invalidate single entry" instruction will invalidate
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Dcache-v4wt.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v4wt.S
5 * Copyright (C) 1997-2002 Russell king
15 #include "proc-macros.S"
55 * Invalidate all cache entries in a particular address
78 * address space.
80 * - start - start address (inclusive, page aligned)
81 * - end - end address (exclusive, page aligned)
82 * - flags - vma_area_struct flags describing address space
101 * region described by start. If you have non-snooping
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/kernel/linux/linux-5.10/arch/alpha/lib/
Dev6-memset.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memset.S
8 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
13 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
15 * E - either cluster
16 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
48 * undertake a major re-write to interleave the constant materialization
49 * with other parts of the fall-through code. This is important, even
58 addq $18,$16,$6 # E : max address to write to
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/kernel/linux/linux-5.10/arch/xtensa/lib/
Dchecksum.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 * This function assumes 2- or 4-byte alignment. Other alignments will fail!
32 /* ONES_ADD converts twos-complement math to ones-complement. */
44 * is aligned on either a 2-byte or 4-byte boundary.
48 bnez a5, 8f /* branch if 2-byte aligned */
49 /* Fall-through on common case, 4-byte alignment */
51 srli a5, a3, 5 /* 32-byte chunks */
57 add a5, a5, a2 /* a5 = end of last 32-byte chunk */
81 extui a5, a3, 2, 3 /* remaining 4-byte chunks */
87 add a5, a5, a2 /* a5 = end of last 4-byte chunk */
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Dmemcopy.S2 * arch/xtensa/lib/hal/memcopy.S -- Core HAL library functions
9 * Copyright (C) 2002 - 2012 Tensilica Inc.
24 * 32-bit load and store instructions (as required for these
34 * If source is aligned,
39 * This code tries to use fall-through branches for the common
40 * case of aligned source and destination and multiple
44 * a0/ return address
71 add a7, a3, a4 # a7 = end address for source
89 .Ldst1mod2: # dst is only byte aligned
95 addi a4, a4, -1
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Dstrncpy_user.S8 * Returns: -EFAULT if exception before terminator, N if the entire
36 # a0/ return address
61 bbsi.l a3, 0, .Lsrc1mod2 # if only 8-bit aligned
62 bbsi.l a3, 1, .Lsrc2mod4 # if only 16-bit aligned
63 .Lsrcaligned: # return here when src is word-aligned
69 .Lsrc1mod2: # src address is odd
75 addi a4, a4, -1 # decrement len
77 bbci.l a3, 1, .Lsrcaligned # if src is now word-aligned
79 .Lsrc2mod4: # src address is 2 mod 4
81 /* 1-cycle interlock */
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/kernel/linux/linux-5.10/sound/soc/fsl/
Dfsl_dma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mpc8610-pcm.h - ALSA PCM interface for the Freescale MPC8610 SoC
15 __be32 clndar; /* Current link descriptor address register */
17 __be32 sar; /* Source address register */
19 __be32 dar; /* Destination address register */
21 __be32 enlndar; /* Next link descriptor extended address reg */
22 __be32 nlndar; /* Next link descriptor address register */
25 __be32 clsdar; /* Current list descriptor address register */
26 __be32 enlsdar; /* Next list descriptor extended address reg */
27 __be32 nlsdar; /* Next list descriptor address register */
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/kernel/linux/linux-5.10/arch/riscv/lib/
Duaccess.S2 #include <asm-generic/export.h>
23 /* Use word-oriented copy only if low-order bits match */
24 andi t0, a0, SZREG-1
25 andi t1, a1, SZREG-1
28 addi t0, a1, SZREG-1
29 andi t1, a3, ~(SZREG-1)
30 andi t0, t0, ~(SZREG-1)
32 * a3: terminal address of source region
33 * t0: lowest XLEN-aligned address in source
34 * t1: highest XLEN-aligned address in source
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/kernel/liteos_m/arch/risc-v/nuclei/gcc/nmsis/Core/Include/
Dcore_feature_base.h4 * SPDX-License-Identifier: Apache-2.0
10 * www.apache.org/licenses/LICENSE-2.0
47 /** \brief Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V */
69 …rv_csr_t b:1; /*!< bit: 1 Tentatively reserved for Bit-Manipulation…
71 …rv_csr_t d:1; /*!< bit: 3 Double-precision floating-point extension…
73 …rv_csr_t f:1; /*!< bit: 5 Single-precision floating-point extension…
79 … /*!< bit: 11 Tentatively reserved for Decimal Floating-Point extension */
81 rv_csr_t n:1; /*!< bit: 13 User-level interrupts supported */
83 …rv_csr_t p:1; /*!< bit: 15 Tentatively reserved for Packed-SIMD exte…
84 …rv_csr_t q:1; /*!< bit: 16 Quad-precision floating-point extension …
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Dcore_feature_fpu.h4 * SPDX-License-Identifier: Apache-2.0
10 * www.apache.org/licenses/LICENSE-2.0
39 * \brief Functions that related to the RISC-V FPU (F and D extension).
42 * Nuclei provided floating point unit by RISC-V F and D extension.
43 * * `F extension` adds single-precision floating-point computational
44 * instructions compliant with the IEEE 754-2008 arithmetic standard, __RISCV_FLEN = 32.
45 * The F extension adds 32 floating-point registers, f0-f31, each 32 bits wide,
46 * and a floating-point control and status register fcsr, which contains the
47 * operating mode and exception status of the floating-point unit.
48 * * `D extension` adds double-precision floating-point computational instructions
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/kernel/linux/linux-5.10/include/uapi/linux/
Dvhost_types.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 /* Userspace interface for in-kernel virtio accelerators. */
26 int fd; /* Pass -1 to unbind from file. */
35 /* Whether log address is valid. If set enables logging. */
40 /* Used structure address. Must be 32 bit aligned */
42 /* Available structure address. Must be 16 bit aligned */
46 * address. Address must be 32 bit aligned. */
104 /* All region addresses and sizes must be 4K aligned. */
116 * Used by QEMU userspace to ensure a consistent vhost-scsi ABI.
118 * ABI Rev 0: July 2012 version starting point for v3.6-rc merge candidate +
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/kernel/linux/linux-5.10/Documentation/sparc/oradax/
Ddax-hv-api.txt3 Publication date 2017-09-25 08:21
5 Extracted via "pdftotext -f 547 -l 572 -layout sun4v_20170925.pdf"
16 live-migration and other system management activities.
20 …high speed processoring of database-centric operations. The coprocessors may support one or more of
28 …e Completion Area and, unless execution order is specifically restricted through the use of serial-
45 …device node in the guest MD (Section 8.24.17, “Database Analytics Accelerators (DAX) virtual-device
51 36.1.1.1. "ORCL,sun4v-dax" Device Compatibility
54 • No-op/Sync
81 36.1.1.2. "ORCL,sun4v-dax-fc" Device Compatibility
82 … "ORCL,sun4v-dax-fc" is compatible with the "ORCL,sun4v-dax" interface, and includes additional CCB
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/kernel/linux/linux-5.10/arch/s390/include/asm/
Dqdio.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 #define QDIO_MAX_BUFFERS_MASK (QDIO_MAX_BUFFERS_PER_Q - 1)
28 * struct qdesfmt0 - queue descriptor, format 0
29 * @sliba: absolute address of storage list information block
30 * @sla: absolute address of storage list
31 * @slsba: absolute address of storage list state block
52 * struct qdr - queue description record (QDR)
59 * @qiba: absolute address of queue information block
90 * struct qib - queue information block (QIB)
95 * @isliba: absolute address of first input SLIB
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/kernel/linux/linux-5.10/include/linux/
Detherdevice.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
68 * is_link_local_ether_addr - Determine if given Ethernet address is link-local
69 * @addr: Pointer to a six-byte array containing the Ethernet address
71 * Return true if address is link local reserved addr (01:80:c2:00:00:0X) per
74 * Please note: addr must be aligned to u16.
91 * is_zero_ether_addr - Determine if give Ethernet address is all zeros.
92 * @addr: Pointer to a six-byte array containing the Ethernet address
94 * Return true if the address is all zeroes.
96 * Please note: addr must be aligned to u16.
110 * is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dpsp_gfx_if.h46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
57 /*-----------------------------------------------------------------------------
64 * SRBM-to-PSP mailbox registers (total 8 registers).
109 …hy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligne…
110 …uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binar…
112 …_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned…
113 …uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
135 … buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned…
136 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */
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/kernel/linux/linux-5.10/arch/mips/include/asm/
Dmaar.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 * platform_maar_init() - perform platform-level MAAR configuration
18 * MAAR pairs as required, from 0 up to the maximum of num_pairs-1, and returns
28 * write_maar_pair() - write to a pair of MAARs
30 * @lower: The lowest address that the MAAR pair will affect. Must be
31 * aligned to a 2^16 byte boundary.
32 * @upper: The highest address that the MAAR pair will affect. Must be
33 * aligned to one byte before a 2^16 byte boundary.
52 * Write the upper address & attributes (both MIPS_MAAR_VL and in write_maar_pair()
65 /* Write the lower address & attributes */ in write_maar_pair()
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/kernel/linux/linux-5.10/Documentation/core-api/
Dunaligned-memory-access.rst23 from an address that is not evenly divisible by N (i.e. addr % N != 0).
24 For example, reading 4 bytes of data from address 0x10004 is fine, but
25 reading 4 bytes of data from address 0x10005 would be an unaligned memory
32 which will compile to multiple-byte memory access instructions, namely when
40 When accessing N bytes of memory, the base memory address must be evenly
59 - Some architectures are able to perform unaligned memory accesses
61 - Some architectures raise processor exceptions when unaligned accesses
64 - Some architectures raise processor exceptions when unaligned accesses
67 - Some architectures are not capable of unaligned memory access, but will
94 starting at address 0x10000. With a basic level of understanding, it would
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/kernel/linux/linux-5.10/sound/pci/trident/
Dtrident_memory.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Trident 4DWave-NX memory page allocation (TLB area)
20 * aligned pages in others
23 do { (trident)->tlb.entries[page] = cpu_to_le32((addr) & ~(SNDRV_TRIDENT_PAGE_SIZE-1)); \
24 (trident)->tlb.shadow_entries[page] = (ptr); } while (0)
26 (void*)((trident)->tlb.shadow_entries[page])
28 (dma_addr_t)le32_to_cpu((trident->tlb.entries[page]) & ~(SNDRV_TRIDENT_PAGE_SIZE - 1))
33 #define MAX_ALIGN_PAGES SNDRV_TRIDENT_MAX_PAGES /* maxmium aligned pages */
37 …nt,page) __set_tlb_bus(trident, page, (unsigned long)trident->tlb.silent_page.area, trident->tlb.s…
38 /* get aligned page from offset address */
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/kernel/linux/linux-5.10/arch/x86/platform/intel-quark/
Dimr.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * imr.c -- Intel Isolated Memory Region driver
6 * Copyright(c) 2015 Bryan O'Donoghue <pure.logic@nexus-software.ie>
10 * When a device behind a masked port performs an access - snooped or
22 * See quark-x1000-datasheet.pdf for register definitions.
23 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/quark-x1000-datasheet.pdf
28 #include <asm-generic/sections.h>
50 * See quark-x1000-datasheet.pdf sections 12.7.4.5 and 12.7.4.6 for
56 * 23:2 1 KiB aligned lo address
61 * 23:2 1 KiB aligned hi address
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/kernel/linux/linux-5.10/tools/testing/selftests/rcutorture/formal/srcu-cbmc/include/linux/
Dtypes.h1 /* SPDX-License-Identifier: GPL-2.0 */
49 /* this is a special 64bit data type that is 8-byte aligned */
50 #define aligned_u64 __u64 __attribute__((aligned(8)))
51 #define aligned_be64 __be64 __attribute__((aligned(8)))
52 #define aligned_le64 __le64 __attribute__((aligned(8)))
70 * A dma_addr_t can hold any valid DMA address, i.e., any address returned
73 * If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32
75 * but drivers do memory-mapped I/O to ioremapped kernel virtual addresses,
121 * struct callback_head - callback structure for use with RCU and task_work
125 * The struct is aligned to size of pointer. On most architectures it happens
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/kernel/linux/linux-5.10/arch/mips/include/asm/octeon/
Dcvmx-fau.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
119 * Builds a store I/O address for writing to the FAU
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
126 * - Step by 8 for 64 bit access.
127 * Returns Address to store for atomic update
137 * Builds a I/O address for accessing the FAU
141 * - 0 = Don't wait
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/kernel/liteos_a/kernel/include/
Dlos_memory.h2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
69 * The start address of exc interaction dynamic memory pool address, when the exc
76 * The start address of system dynamic memory pool address.
90 * @param pool [IN] Starting address of memory.
150 * <li>The parameter input must be four byte-aligned.</li>
154 * @param pool [IN] Starting address of memory.
180 * @param pool [IN] Starting address of memory.
204 * <li>The size of the input parameter size must be four byte-aligned.</li>
211 …* @retval #VOID* The memory is successfully allocated with the starting address of the all…
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