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/kernel/liteos_m/arch/arm/
DKconfig4 # ARM has 32-bit(Aarch32) and 64-bit(Aarch64) implementations
10 32-bit ARM architecture implementations, Except the M-profile.
11 It is not limited to ARMv7-A but also ARMv7-R, ARMv8-A 32-bit and etc.
27 default "armv7-m" if ARCH_ARM_V7M
28 default "armv8-m" if ARCH_ARM_V8M
48 …onal extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
49 …VFPv3U is a variant of VFPv3 that supports the trapping of floating-point exceptions to support co…
54 …onal extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
55 …VFPv4U is a variant of VFPv4 that supports the trapping of floating-point exceptions to support co…
56 …VFPv4 and VFPv4U add both the Half-precision Extension and the fused multiply-add instructions to …
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/kernel/liteos_m/
Darch_spec.md3 ├── arch --- Code of the kernel instruction …
4 │   ├── arm --- ARM32 architecture
5 │   │   ├── arm9 --- ARM9 architecture
6 │   │   │ └── gcc --- Implementation of the GCC toolc…
7 │   │   ├── cortex-m3 --- Cortex-m3 architecture
8 │   │   │ └── keil --- Implementation of the keil tool…
9 │   │   ├── cortex-m33 --- Cortex-m33 architecture
10 │   │   │ │── gcc --- Implementation of the GCC toolc…
11 │   │   │ │ │── NTZ --- Cortex-m33 Non-TrustZone archit…
12 │   │   │ │ └── TZ --- Cortex-m33 TrustZone architectu…
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DREADME.md1 # LiteOS-M Kernel<a name="EN-US_TOPIC_0000001096757661"></a>
3 - [Introduction](#section11660541593)
4 - [Directory Structure](#section161941989596)
5 - [Constraints](#section119744591305)
6 - [Usage](#section3732185231214)
7 - [Contribution](#section1371123476307)
8 - [Repositories Involved](#section1371113476307)
12 …-M is a lightweight operating system kernel designed for the Internet of Things (IoT) field. It fe…
13 **Figure1** shows the architecture of the LiteOS-M kernel.
15 **Figure 1** Architecture of the OpenHarmony LiteOS-M kernel<a name="fig0865152210223"></a>
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DREADME_zh.md1 # LiteOS-M内核<a name="ZH-CN_TOPIC_0000001096757661"></a>
3 - [简介](#section11660541593)
4 - [目录](#section161941989596)
5 - [约束](#section119744591305)
6 - [使用说明](#section3732185231214)
7 - [贡献](#section1371123476307)
8 - [相关仓](#section1371113476307)
12 OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系统内核，具有小体积、低功耗、高性能的特点，其代码结构简单，主要包括内核最小功能集、内核抽象层、可选组件以及工程目录…
14 **图 1** OpenHarmony LiteOS-M核内核架构图<a name="fig0865152210223"></a>
15 ![](figures/OpenHarmony-LiteOS-M核内核架构图.png "OpenHarmony-LiteOS-M核内核架构图")
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Darch_spec_zh.md3 ├── arch --- 内核指令架构层代码
4 │   ├── arm --- ARM32架构
5 │   │   ├── arm9 --- arm9架构
6 │   │   │ └── gcc --- gcc 编译工具链实现
7 │   │   ├── cortex-m3 --- Cortex-m3架构
8 │   │   │ └── keil --- Keil编译工具链实现
9 │   │   ├── cortex-m33 --- Cortex-m33架构
10 │   │   │ │── gcc --- GCC编译工具链实现
11 │   │   │ │ │── NTZ --- Cortex-m33非TrustZone架构实现
12 │   │   │ │ └── TZ --- Cortex-m33 TrustZone架构实现
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/remoteproc/
Dwkup_m3_rproc.txt1 TI Wakeup M3 Remoteproc Driver
4 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
5 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
10 Wkup M3 Device Node:
12 A wkup_m3 device node is used to represent the Wakeup M3 processor instance
17 --------------------
18 - compatible: Should be one of,
19 "ti,am3352-wkup-m3" for AM33xx SoCs
20 "ti,am4372-wkup-m3" for AM43xx SoCs
21 - reg: Should contain the address ranges for the two internal
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Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/ti/
Dwkup_m3_ipc.txt1 Wakeup M3 IPC Driver
4 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
5 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
7 C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
12 Wkup M3 Device Node:
18 --------------------
19 - compatible: Should be,
20 "ti,am3352-wkup-m3-ipc" for AM33xx SoCs
21 "ti,am4372-wkup-m3-ipc" for AM43xx SoCs
22 - reg: Contains the IPC register address space to communicate
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/kernel/linux/linux-5.10/arch/arm/mm/
Dproc-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7m.S
8 * This is the "shell" of the ARMv7-M processor support.
14 #include "proc-macros.S"
31 * - loc - location to jump to for soft reset
104 * This should be able to cover all ARMv7-M cores.
140 ldmia sp, {r0-r3, r12}
144 @ Special-purpose control register
150 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
152 teq r8, #0 @ re-evalutae condition
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/kernel/liteos_m/arch/arm/cortex-m3/keil/
Dlos_arch_interrupt.h2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M3 platform is [OS_USER_HWI_MIN,…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be…
164 * The value range of the interrupt priority applicable for a Cortex-M3 platform is [0,15].
185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be…
203 * Interrupt Priority-Level Registers.
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/kernel/liteos_m/arch/
DBUILD.gn1 # Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
2 # Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
38 if ("$board_cpu" == "arm9" || "$board_cpu" == "cortex-m3" ||
39 "$board_cpu" == "cortex-m4" || "$board_cpu" == "cortex-m7" ||
40 "$board_cpu" == "cortex-m33" || "$board_cpu" == "cortex-m55") {
47 modules += [ "risc-v" ]
/kernel/linux/linux-5.10/drivers/soc/ti/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # 64-bit ARM SoCs from TI
36 Packets are queued/de-queued by writing/reading descriptor address
58 c-states on AM335x. Also required for rtc and ddr in self-refresh low
62 tristate "TI AMx3 Wkup-M3 IPC Driver"
66 TI AM33XX and AM43XX have a Cortex M3, the Wakeup M3, to handle
68 to communicate and use the Wakeup M3 for PM features like suspend
105 tristate "TI PRU-ICSS Subsystem Platform drivers"
109 TI PRU-ICSS Subsystem platform specific support.
/kernel/linux/linux-5.10/arch/arm/mach-vexpress/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
24 This option enables support for systems using Cortex processor based
28 - CoreTile Express A5x2 (V2P-CA5s)
29 - CoreTile Express A9x4 (V2P-CA9)
30 - CoreTile Express A15x2 (V2P-CA15)
31 - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
33 - Versatile Express RTSMs (Models)
42 bool "Enable A5 and A9 only errata work-arounds"
49 based on Cortex-A5 and Cortex-A9 processors. In order to
68 between the dual cluster test-chip and the M3 microcontroller that
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/
Dxgene-slimpro-mailbox.txt1 The APM X-Gene SLIMpro mailbox is used to communicate messages between
2 the ARM64 processors and the Cortex M3 (dubbed SLIMpro). It uses a simple
10 - compatible: Should be as "apm,xgene-slimpro-mbox".
12 - reg: Contains the mailbox register address range.
14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
18 - #mbox-cells: only one to specify the mailbox channel number.
24 compatible = "apm,xgene-slimpro-mbox";
26 #mbox-cells = <1>;
/kernel/linux/linux-5.10/drivers/remoteproc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
30 Say y here to support iMX's remote processors (Cortex M4
41 This can be either built-in or a loadable module.
61 Say y here to support OMAP's remote processors (dual M3
67 use-cases to run on your platform (multimedia codecs are
86 tristate "AMx3xx Wakeup M3 remoteproc support"
89 Say y here to support Wakeup M3 remote processor on TI AM33xx
92 Required for Suspend-to-RAM on AM33xx and AM43xx SoCs. Also needed
98 tristate "DA8xx/OMAP-L13x remoteproc support"
102 Say y here to support DA8xx/OMAP-L13x remote processors via the
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
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/kernel/linux/linux-5.10/Documentation/staging/
Dremoteproc.rst10 of operating system, whether it's Linux or any other flavor of real-time OS.
12 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.
13 In a typical configuration, the dual cortex-A9 is running Linux in a SMP
14 configuration, and each of the other three cores (two M3 cores and a DSP)
22 platform-specific remoteproc drivers only need to provide a few low-level
24 (for more information about the virtio-based rpmsg bus and its drivers,
117 name of this remote processor, platform-specific ops handlers,
153 This is called by the platform-specific rproc implementation, whenever
179 Returns 0 on success and -EINVAL if @rproc isn't valid.
189 non-remoteproc driver. This function can be called from atomic/interrupt
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Drpmsg.rst17 flavor of real-time OS.
19 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.
20 Typically, the dual cortex-A9 is running Linux in a SMP configuration,
21 and each of the other three cores (two M3 cores and a DSP) is running
25 hardware accelerators, and therefore are often used to offload CPU-intensive
28 These remote processors could also be used to control latency-sensitive
34 hardware accessible only by the remote processor, reserving kernel-controlled
37 Rpmsg is a virtio-based messaging bus that allows kernel drivers to communicate
60 a unique rpmsg local address (a 32-bit integer). This way when inbound messages
83 -ERESTARTSYS is returned.
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/kernel/linux/linux-5.10/arch/arm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
131 The ARM series is a line of low-power-consumption RISC chip designs
133 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
134 manufactured, but legacy ARM-based PC hardware remains popular in
244 Patch phys-to-virt and virt-to-phys translation functions at
248 This can only be used with non-XIP MMU kernels where the base
294 bool "MMU-based Paged Memory Management Support"
297 Select if you want MMU-based virtualised addressing space
336 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
349 bool "EBSA-110"
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/kernel/linux/linux-5.10/Documentation/locking/
Dhwspinlock.rst12 For example, OMAP4 has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP,
14 is usually running Linux and the slave processors, the M3 and the DSP,
17 A generic hwspinlock framework allows platform-independent drivers to use
22 This is necessary, for example, for Inter-processor communications:
23 on OMAP4, cpu-intensive multimedia tasks are offloaded by the host to the
24 remote M3 and/or C64x+ slave processors (by an IPC subsystem called Syslink).
26 To achieve fast message-based communications, a minimal kernel support
35 A common hwspinlock interface makes it possible to have generic, platform-
67 Retrieve the global lock id for an OF phandle-based specific lock.
72 The function returns a lock id number on success, -EPROBE_DEFER if
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/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-nvic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/irq/irq-nvic.c
9 * ARMv7-M CPUs (Cortex-M3/M4)
36 #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
85 return -ENOMEM; in nvic_of_init()
97 return -ENOMEM; in nvic_of_init()
113 gc->reg_base = nvic_base + 4 * i; in nvic_of_init()
114 gc->chip_types[0].regs.enable = NVIC_ISER; in nvic_of_init()
115 gc->chip_types[0].regs.disable = NVIC_ICER; in nvic_of_init()
116 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in nvic_of_init()
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/kernel/uniproton/src/arch/cpu/armv7-m/common/
Dos_cpu_armv7_m_external.h2 * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved.
9 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12 * Create: 2009-12-22
33 #define OS_MX_VECTOR_CNT (OS_MX_SYS_VECTOR_CNT + OS_MX_IRQ_VECTOR_CNT) /* 系统向量16个 + 60(M3)/82(M4)个中…
38 /* 为了保持对外接口统一（硬件中断号），mx的hwinum=irqnum=真实中断号-16(内部已处理, 见OsInterrupt) */
137 return ((struct TagHwContext *)addr)->pc; in OsTskGetInstrAddr()
143 #include "../cortex-m4/prt_cpu_m4_external.h"
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dam4372.dtsi4 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/clock/am4.h>
18 interrupt-parent = <&wakeupgen>;
19 #address-cells = <1>;
20 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
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Dam33xx.dtsi4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/am33xx.h>
14 #include <dt-bindings/clock/am3.h>
18 interrupt-parent = <&intc>;
19 #address-cells = <1>;
20 #size-cells = <1>;
33 d-can0 = &dcan0;
34 d-can1 = &dcan1;
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/kernel/linux/linux-5.10/drivers/mailbox/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
51 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
77 This driver provides support for inter-processor communication
161 providing an interface for invoking the inter-process communication
174 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
177 An implementation of the APM X-Gene Interprocessor Communication
178 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
179 It is used to send short messages between ARM64-bit cores and
181 want to use the APM X-Gene SLIMpro IPCM support.
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