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/kernel/linux/linux-5.10/Documentation/riscv/
Dpatch-acceptance.rst1 .. SPDX-License-Identifier: GPL-2.0
7 --------
8 The RISC-V instruction set architecture is developed in the open:
9 in-progress drafts are available for all to review and to experiment
11 during the development process - sometimes in ways that are
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
14 of churn, and the Linux development process prefers well-reviewed and
16 principles to the RISC-V-related code that will be accepted for
20 -------------------------
23 "Frozen" or "Ratified" by the RISC-V Foundation. (Developers may, of
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Dboot-image-header.rst2 Boot image header in RISC-V Linux
8 This document only describes the boot image header details for RISC-V Linux.
13 The following 64-byte header is present in decompressed Linux kernel image::
28 ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common
34 - This header can also be reused to support EFI stub for RISC-V in future. EFI
40 - version field indicate header version number
50 - The "magic" field is deprecated as of version 0.2. In a future
55 - In current header, the flags field has only one field.
61 - Image size is mandatory for boot loader to load kernel image. Booting will
Dpmu.rst2 Supporting PMUs on RISC-V platforms
8 ------------
10 As of this writing, perf_event-related features mentioned in The RISC-V ISA
23 Counters are just free-running all the time in our case.
33 hardware-extension for M-S-U model machines to write counters directly.
44 -----------------
47 various methods according to perf's internal convention and PMU-specific
53 the minimal and already-implemented logic can be leveraged, or invent his/her
63 -----------------------
72 into bitmap, so that HW-related control registers or counters can directly be
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/kernel/linux/linux-5.10/Documentation/translations/it_IT/riscv/
Dpatch-acceptance.rst1 .. include:: ../disclaimer-ita.rst
3 :Original: :doc:`../../../riscv/patch-acceptance`
10 ------------
12 L'insieme di istruzioni RISC-V sono sviluppate in modo aperto: le
15 dei nuovi moduli o estensioni possono cambiare in fase di sviluppo - a
18 supporto RISC-V nel kernel Linux. I manutentori Linux non amano
22 relativo all'architettura RISC-V che verrà accettato per l'inclusione
26 -------------------------------------------------------------------------
29 RISC-V li classifica come "Frozen" o "Retified". (Ovviamente, gli
33 In aggiunta, la specifica RISC-V permette agli implementatori di
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
28 - #interrupt-cells : should be <1>. The interrupt sources are defined by the
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Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
12 (PLIC) high-level specification in the RISC-V Privileged Architecture
17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
20 Each interrupt can be enabled on per-context basis. Any context can claim
28 While the PLIC supports both edge-triggered and level-triggered interrupts,
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/kernel/linux/linux-5.10/arch/riscv/kernel/
Dperf_callchain.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd. */
23 (unsigned long *)(fp - sizeof(struct stackframe)); in user_backtrace()
53 * $ perf record -e cpu-clock --call-graph fp ./program
54 * $ perf report --call-graph
56 * On RISC-V platform, the program being sampled and the C library
57 * need to be compiled with -fno-omit-frame-pointer, otherwise
66 /* RISC-V does not support perf in guest mode. */ in perf_callchain_user()
67 if (guest_cbs && guest_cbs->is_in_guest()) in perf_callchain_user()
70 fp = regs->s0; in perf_callchain_user()
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Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
12 * Returns the hart ID of the given device tree node, or -ENODEV if the node
13 * isn't an enabled and valid RISC-V hart node.
22 return -ENODEV; in riscv_of_processor_hartid()
27 return -ENODEV; in riscv_of_processor_hartid()
32 return -ENODEV; in riscv_of_processor_hartid()
37 return -ENODEV; in riscv_of_processor_hartid()
39 if (isa[0] != 'r' || isa[1] != 'v') { in riscv_of_processor_hartid()
41 return -ENODEV; in riscv_of_processor_hartid()
51 * RISC-V core (HART) node and extract the cpuid from it.
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Dsys_riscv.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <asm-generic/mman-common.h>
19 return -EINVAL; in riscv_sys_mmap()
23 return -EINVAL; in riscv_sys_mmap()
26 offset >> (PAGE_SHIFT - page_shift_offset)); in riscv_sys_mmap()
50 * Allows the instruction cache to be flushed from userspace. Despite RISC-V
55 * thread->hart mappings), so we've defined a RISC-V specific system call to
68 return -EINVAL; in SYSCALL_DEFINE3()
70 flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL); in SYSCALL_DEFINE3()
/kernel/linux/linux-5.10/drivers/media/pci/cx88/
Dcx88-alsa.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include "cx88-reg.h"
22 #include <linux/dma-mapping.h>
37 chip->core->name, ##arg); \
41 * Data type declarations - Can be moded to a header file later
46 struct cx88_riscmem risc; member
81 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
116 struct cx88_audio_buffer *buf = chip->buf; in _cx88_start_audio_dma()
117 struct cx88_core *core = chip->core; in _cx88_start_audio_dma()
120 /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */ in _cx88_start_audio_dma()
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Dcx88-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * (c) 2005-2006 Mauro Carvalho Chehab <mchehab@kernel.org>
9 * - Multituner support
10 * - video_ioctl2 conversion
11 * - PAL/M fixes
29 #include <media/v4l2-common.h>
30 #include <media/v4l2-ioctl.h>
36 /* ------------------------------------------------------------------ */
64 #define NO_SYNC_LINE (-1U)
91 offset -= sg_dma_len(sg); in cx88_risc_field()
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/kernel/linux/linux-5.10/arch/riscv/include/asm/
Dpci.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <linux/dma-mapping.h>
18 /* RISC-V shim does not initialize PCI bus */
26 /* no legacy IRQ on risc-v */ in pci_get_legacy_ide_irq()
27 return -ENODEV; in pci_get_legacy_ide_irq()
/kernel/liteos_m/
DREADME.md1 # LiteOS-M Kernel<a name="EN-US_TOPIC_0000001096757661"></a>
3 - [Introduction](#section11660541593)
4 - [Directory Structure](#section161941989596)
5 - [Constraints](#section119744591305)
6 - [Usage](#section3732185231214)
7 - [Contribution](#section1371123476307)
8 - [Repositories Involved](#section1371113476307)
12 …-M is a lightweight operating system kernel designed for the Internet of Things (IoT) field. It fe…
13 **Figure1** shows the architecture of the LiteOS-M kernel.
15 **Figure 1** Architecture of the OpenHarmony LiteOS-M kernel<a name="fig0865152210223"></a>
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DREADME_zh.md1 # LiteOS-M内核<a name="ZH-CN_TOPIC_0000001096757661"></a>
3 - [简介](#section11660541593)
4 - [目录](#section161941989596)
5 - [约束](#section119744591305)
6 - [使用说明](#section3732185231214)
7 - [贡献](#section1371123476307)
8 - [相关仓](#section1371113476307)
12 OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系统内核，具有小体积、低功耗、高性能的特点，其代码结构简单，主要包括内核最小功能集、内核抽象层、可选组件以及工程目录…
14 **图 1** OpenHarmony LiteOS-M核内核架构图<a name="fig0865152210223"></a>
15 ![](figures/OpenHarmony-LiteOS-M核内核架构图.png "OpenHarmony-LiteOS-M核内核架构图")
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Darch_spec.md3 ├── arch --- Code of the kernel instruction …
4 │   ├── arm --- ARM32 architecture
5 │   │   ├── arm9 --- ARM9 architecture
6 │   │   │ └── gcc --- Implementation of the GCC toolc…
7 │   │   ├── cortex-m3 --- Cortex-m3 architecture
8 │   │   │ └── keil --- Implementation of the keil tool…
9 │   │   ├── cortex-m33 --- Cortex-m33 architecture
10 │   │   │ │── gcc --- Implementation of the GCC toolc…
11 │   │   │ │ │── NTZ --- Cortex-m33 Non-TrustZone archit…
12 │   │   │ │ └── TZ --- Cortex-m33 TrustZone architectu…
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/kernel/linux/linux-5.10/drivers/media/pci/cx23885/
Dcx23885-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include "altera-ci.h"
25 #include "cx23888-ir.h"
26 #include "cx23885-ir.h"
27 #include "cx23885-av.h"
28 #include "cx23885-input.h"
38 * encountered is "mpeg risc op code error". Only Ryzen platforms employ
45 …PARM_DESC(dma_reset_workaround, "periodic RiSC dma engine reset; 0-force disable, 1-driver detect …
51 static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
63 #define NO_SYNC_LINE (-1U)
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/kernel/linux/linux-5.10/tools/arch/riscv/include/uapi/asm/
Dunistd.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
23 #include <asm-generic/unistd.h>
26 * Allows the instruction cache to be flushed from userspace. Despite RISC-V
31 * thread->hart mappings), so we've defined a RISC-V specific system call to
/kernel/linux/linux-5.10/arch/riscv/include/uapi/asm/
Dunistd.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
25 #include <asm-generic/unistd.h>
28 * Allows the instruction cache to be flushed from userspace. Despite RISC-V
33 * thread->hart mappings), so we've defined a RISC-V specific system call to
/kernel/linux/linux-5.10/drivers/clocksource/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
165 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
188 32-bit free running decrementing counters.
242 bool "Integrator-AP timer driver" if COMPILE_TEST
245 Enables support for the Integrator-AP timer.
278 available on many OMAP-like platforms.
287 It has a 64-bit counter with update rate up to 1000MHz.
288 This counter is accessed via couple of 32-bit memory-mapped registers.
307 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
311 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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/kernel/linux/linux-5.10/drivers/irqchip/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
216 bool "J-Core integrated AIC" if COMPILE_TEST
220 Support for the J-Core integrated AIC.
231 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
234 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
239 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
274 tristate "TS-4800 IRQ controller"
279 Support for the TS-4800 FPGA IRQ controller
443 bool "C-SKY Multi Processor Interrupt Controller"
446 Say yes here to enable C-SKY SMP interrupt controller driver used
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/kernel/linux/linux-5.10/drivers/firmware/efi/libstub/
Driscv-stub.c1 // SPDX-License-Identifier: GPL-2.0
15 * RISC-V requires the kernel image to placed 2 MB aligned base for 64 bit and
42 prop = fdt_getprop((void *)fdt, chosen_node, "boot-hartid", &len); in get_boot_hartid_from_fdt()
53 efi_err("/chosen/boot-hartid missing or invalid!\n"); in check_platform_features()
62 unsigned long stext_offset = _start_kernel - _start; in efi_enter_kernel()
86 kernel_size = _edata - _start; in handle_kernel_image()
88 *image_size = kernel_size + (_end - _edata); in handle_kernel_image()
91 * RISC-V kernel maps PAGE_OFFSET virtual address to the same physical in handle_kernel_image()
/kernel/linux/linux-5.10/drivers/tty/hvc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
8 It will automatically be selected if one of the back-end console drivers
51 This driver provides a Hypervisor console (HVC) back-end to access
91 bool "RISC-V SBI console support"
95 This enables support for console output via RISC-V SBI calls, which
/kernel/linux/linux-5.10/include/uapi/linux/
Delf-em.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define EM_MIPS 8 /* MIPS R3000 (officially, big-endian only) */
18 #define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */
19 #define EM_MIPS_RS4_BE 10 /* MIPS R4000 big-endian */
28 #define EM_SPARCV9 43 /* SPARC v9 64-bit */
30 #define EM_IA_64 50 /* HP/Intel IA-64 */
31 #define EM_X86_64 62 /* AMD x86-64 */
33 #define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */
36 #define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */
40 #define EM_UNICORE 110 /* UniCore-32 */
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