| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/supply/ |
| D | max17040_battery.txt | 5 - compatible : "maxim,max17040", "maxim,max17041", "maxim,max17043",
7 "maxim,max17058", "maxim,max17059" or "maxim,max77836-battery"
8 - reg: i2c slave address
11 - maxim,alert-low-soc-level : The alert threshold that sets the state of
12 charge level (%) where an interrupt is
16 - maxim,double-soc : Certain devices return double the capacity.
19 SOC == State of Charge == Capacity.
20 - maxim,rcomp : A value to compensate readings for various
25 - interrupts : Interrupt line see Documentation/devicetree/
26 bindings/interrupt-controller/interrupts.txt
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| D | da9150-fg.txt | 1 Dialog Semiconductor DA9150 Fuel-Gauge Power Supply bindings
4 - compatible: "dlg,da9150-fuel-gauge" for DA9150 Fuel-Gauge Power Supply
7 - dlg,update-interval: Interval time (milliseconds) between battery level checks.
8 - dlg,warn-soc-level: Battery discharge level (%) where warning event raised.
9 [1 - 100]
10 - dlg,crit-soc-level: Battery discharge level (%) where critical event raised.
11 This value should be lower than the warning level.
12 [1 - 100]
17 fuel-gauge {
18 compatible = "dlg,da9150-fuel-gauge";
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| /kernel/linux/linux-5.10/drivers/power/supply/ |
| D | da9150-fg.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DA9150 Fuel-Gauge Driver
84 int soc; member
99 da9150_read_qif(fg->da9150, read_addr, size, buf); in da9150_fg_read_attr()
121 da9150_write_qif(fg->da9150, write_addr, size, buf); in da9150_fg_write_attr()
130 mutex_lock(&fg->io_lock); in da9150_fg_read_sync_start()
150 dev_err(fg->dev, "Failed to perform QIF read sync!\n"); in da9150_fg_read_sync_start()
159 mutex_unlock(&fg->io_lock); in da9150_fg_read_sync_end()
181 mutex_lock(&fg->io_lock); in da9150_fg_write_attr_sync()
196 dev_err(fg->dev, "Timeout waiting for existing QIF sync!\n"); in da9150_fg_write_attr_sync()
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| D | max17040_battery.c | 1 // SPDX-License-Identifier: GPL-2.0
4 // fuel-gauge systems for lithium-ion (Li+) batteries
149 int soc; member
162 return regmap_write(chip->regmap, MAX17040_CMD, chip->data.reset_val); in max17040_reset()
165 static int max17040_set_low_soc_alert(struct max17040_chip *chip, u32 level) in max17040_set_low_soc_alert() argument
167 level = 32 - level * (chip->quirk_double_soc ? 2 : 1); in max17040_set_low_soc_alert()
168 return regmap_update_bits(chip->regmap, MAX17040_CONFIG, in max17040_set_low_soc_alert()
169 MAX17040_ATHD_MASK, level); in max17040_set_low_soc_alert()
174 return regmap_update_bits(chip->regmap, MAX17040_CONFIG, in max17040_set_soc_alert()
180 u16 mask = chip->data.rcomp_bytes == 2 ? in max17040_set_rcomp()
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | cm_common.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 * cm_ll_data: function pointers to SoC-specific implementations of
41 * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
43 * @cm2: CM2 base virtual address (if present on the booted SoC)
54 * cm_split_idlest_reg - split CM_IDLEST reg addr into its components
61 * via the @prcm_inst and @idlest_reg_id. Returns -EINVAL upon error,
69 if (!cm_ll_data->split_idlest_reg) { in cm_split_idlest_reg()
70 WARN_ONCE(1, "cm: %s: no low-level function defined\n", in cm_split_idlest_reg()
72 return -EINVAL; in cm_split_idlest_reg()
75 ret = cm_ll_data->split_idlest_reg(idlest_reg, prcm_inst, in cm_split_idlest_reg()
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| D | prm_common.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Tero Kristo <t-kristo@ti.com>
24 #include <linux/clk-provider.h>
27 #include "soc.h"
45 * actual amount of memory needed for the SoC
70 * prm_ll_data: function pointers to SoC-specific implementations of
86 for (i = 0; i < prcm_irq_setup->nr_regs; i++) { in omap_prcm_events_filter_priority()
88 events[i] & prcm_irq_setup->priority_mask[i]; in omap_prcm_events_filter_priority()
99 * done by the SoC specific individual handlers.
107 int nr_irq = prcm_irq_setup->nr_regs * 32; in omap_prcm_irq_handler()
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| D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap2/clock.c
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
21 #include <linux/clk-provider.h>
29 #include "soc.h"
35 #include "cm-regbits-24xx.h"
36 #include "cm-regbits-34xx.h"
41 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | sprd,pinctrl.txt | 8 pad driving level, system control select and so on ("domain pad
9 driving level": One pin can output 3.0v or 1.8v, depending on the
13 have several systems (AP/CP/CM4) on one SoC.).
16 of them, so we can not make every Spreadtrum-special configuration
32 Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
35 - input-enable
36 - input-disable
37 - output-high
38 - output-low
39 - bias-pull-up
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| /kernel/linux/linux-5.10/drivers/thermal/tegra/ |
| D | soctherm.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
34 #include <dt-bindings/thermal/tegra124-soctherm.h>
197 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
200 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
203 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
205 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
206 * level vector
212 #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1) argument
229 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
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| /kernel/linux/linux-5.10/Documentation/driver-api/firmware/ |
| D | other_interfaces.rst | 5 --------------
7 .. kernel-doc:: drivers/firmware/dmi_scan.c
11 --------------
13 .. kernel-doc:: drivers/firmware/edd.c
16 Intel Stratix10 SoC Service Layer
17 ---------------------------------
18 Some features of the Intel Stratix10 SoC require a level of privilege
21 at Exception Level 1 (EL1), access to the features requires
22 Exception Level 3 (EL3).
24 The Intel Stratix10 SoC service layer provides an in kernel API for
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpc5121-psc.txt | 4 ----------------
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
16 Supported <soc>s: mpc5121, mpc5125
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
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| D | mpc5200.txt | 2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
18 chip? For the MPC5200; the answer is easy. Most of the SoC devices
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,llcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Last Level Cache Controller
10 - Rishabh Bhatnagar <rishabhb@codeaurora.org>
11 - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
14 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
16 SoC, the idea is to minimize the local caches at the clients and migrate to
24 - qcom,sc7180-llcc
25 - qcom,sdm845-llcc
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| D | qcom,idle-state.txt | 3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
6 The idle states supported by the QCOM SoC are defined as -
41 back into Elevation Level (EL) which trampolines the control back to the
44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
48 itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
49 modes. In a hierarchical power domain SoC, this means L2 and other caches can
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
53 of this low power mode would be considered high even though at a cpu level,
55 with the Resource power manager (RPM) processor in the SoC to indicate a
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | t104xsi-pre.dtsi | 2 * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2013-2014 Freescale Semiconductor Inc.
35 /dts-v1/;
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
45 ccsr = &soc;
71 #address-cells = <1>;
72 #size-cells = <0>;
78 next-level-cache = <&L2_1>;
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| D | p4080si-pre.dtsi | 2 * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 ccsr = &soc;
91 #address-cells = <1>;
92 #size-cells = <0>;
98 next-level-cache = <&L2_0>;
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| D | p2041si-pre.dtsi | 2 * P2041 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 ccsr = &soc;
86 #address-cells = <1>;
87 #size-cells = <0>;
93 next-level-cache = <&L2_0>;
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| D | p3041si-pre.dtsi | 2 * P3041 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 ccsr = &soc;
87 #address-cells = <1>;
88 #size-cells = <0>;
94 next-level-cache = <&L2_0>;
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| D | p5040si-pre.dtsi | 2 * P5040 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 ccsr = &soc;
99 #address-cells = <1>;
100 #size-cells = <0>;
106 next-level-cache = <&L2_0>;
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| D | t102xsi-pre.dtsi | 2 * T1024/T1023 Silicon/SoC Device Tree Source (pre include)
35 /dts-v1/;
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
45 ccsr = &soc;
71 #address-cells = <1>;
72 #size-cells = <0>;
78 next-level-cache = <&L2_1>;
79 #cooling-cells = <2>;
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| D | b4860si-pre.dtsi | 2 * B4860 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
46 ccsr = &soc;
72 #address-cells = <1>;
73 #size-cells = <0>;
79 next-level-cache = <&L2_1>;
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
22 Choose this option for open-source NVIDIA support.
37 bool "Nouveau (NVIDIA) SoC GPUs"
41 Support for Nouveau platform driver, used for SoC GPUs as found
45 int "Maximum debug level"
50 Selects the maximum debug level to compile support for.
52 0 - fatal
53 1 - error
54 2 - warning
55 3 - info
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | qcom,qusb2-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Manu Gautam <mgautam@codeaurora.org>
19 - items:
20 - enum:
21 - qcom,ipq8074-qusb2-phy
22 - qcom,msm8996-qusb2-phy
23 - qcom,msm8998-qusb2-phy
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx6q.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
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| /kernel/linux/linux-5.10/Documentation/devicetree/ |
| D | usage-model.rst | 1 .. SPDX-License-Identifier: GPL-2.0
44 ----------
56 In 2005, when PowerPC Linux began a major cleanup and to merge 32-bit
57 and 64-bit support, the decision was made to require DT support on all
61 blob without requiring a real Open Firmware implementation. U-Boot,
66 existing non-DT aware firmware.
71 out of mainline (nios) have some level of DT support.
74 -------------
78 2.1 High Level View
79 -------------------
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