| /kernel/linux/linux-5.10/arch/arm/include/asm/hardware/ |
| D | cp14.h | 45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0)
46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
50 #define RCP14_DBGECR() MRC14(0, c0, c9, 0)
51 #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0)
52 #define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0)
53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2)
54 #define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2)
[all …]
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| /kernel/liteos_a/arch/arm/arm/include/ |
| D | arm.h | 42 __asm__ volatile("mrc p15, 0, %0, c1,c0,0" : "=r"(val)); in OsArmReadSctlr()
48 __asm__ volatile("mcr p15, 0, %0, c1,c0,0" ::"r"(val)); in OsArmWriteSctlr()
55 __asm__ volatile("mrc p15, 0, %0, c1,c0,1" : "=r"(val)); in OsArmReadActlr()
61 __asm__ volatile("mcr p15, 0, %0, c1,c0,1" ::"r"(val)); in OsArmWriteActlr()
68 __asm__ volatile("mrc p15, 0, %0, c1,c0,2" : "=r"(val)); in OsArmReadCpacr()
74 __asm__ volatile("mcr p15, 0, %0, c1,c0,2" ::"r"(val)); in OsArmWriteCpacr()
81 __asm__ volatile("mrc p15, 0, %0, c2,c0,0" : "=r"(val)); in OsArmReadTtbr()
87 __asm__ volatile("mcr p15, 0, %0, c2,c0,0" ::"r"(val)); in OsArmWriteTtbr()
94 __asm__ volatile("mrc p15, 0, %0, c2,c0,0" : "=r"(val)); in OsArmReadTtbr0()
100 __asm__ volatile("mcr p15, 0, %0, c2,c0,0" ::"r"(val)); in OsArmWriteTtbr0()
[all …]
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| D | los_hw_cpu.h | 90 * Identification registers (c0)
92 #define MIDR CP15_REG(c0, 0, c0, 0) /* Main ID Register */
93 #define MPIDR CP15_REG(c0, 0, c0, 5) /* Multiprocessor Affinity Register */
94 #define CCSIDR CP15_REG(c0, 1, c0, 0) /* Cache Size ID Registers */
95 #define CLIDR CP15_REG(c0, 1, c0, 1) /* Cache Level ID Register */
96 #define VPIDR CP15_REG(c0, 4, c0, 0) /* Virtualization Processor ID Register */
97 #define VMPIDR CP15_REG(c0, 4, c0, 5) /* Virtualization Multiprocessor ID Register …
102 #define SCTLR CP15_REG(c1, 0, c0, 0) /* System Control Register */
103 #define ACTLR CP15_REG(c1, 0, c0, 1) /* Auxiliary Control Register */
104 #define CPACR CP15_REG(c1, 0, c0, 2) /* Coprocessor Access Control Register */
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/ |
| D | g98.fuc0s | 514 cxsin $c0
515 cxsout $c0
525 cxsin $c0
526 cenc $c0 $c0
527 cxsout $c0
533 cxsin $c0
534 cdec $c0 $c0
535 cxsout $c0
540 cxsin $c0
541 cxor $c6 $c0
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | proc-v7.S | 32 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
35 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
58 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
134 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
135 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
138 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
142 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
144 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
146 mrc p15, 0, r8, c1, c0, 0 @ Control register
[all …]
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| D | proc-v6.S | 39 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
42 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
59 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
76 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
104 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
106 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
111 mcr p15, 0, r1, c13, c0, 1 @ set context ID
139 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
141 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
[all …]
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| D | proc-sa1100.S | 42 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
78 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
147 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
148 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
175 mrc p15, 0, r4, c3, c0, 0 @ domain ID
176 mrc p15, 0, r5, c13, c0, 0 @ PID
177 mrc p15, 0, r6, c1, c0, 0 @ control reg
[all …]
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| D | proc-arm740.S | 37 mrc p15, 0, r0, c1, c0, 0
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
71 mcr p15, 0, r0, c6, c0 @ set area 0, default
97 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
103 mcr p15, 0, r0, c3, c0
107 mcr p15, 0, r0, c5, c0 @ all read/write access
[all …]
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| D | proc-xsc3.S | 56 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
89 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
92 mcr p15, 0, r0, c1, c0, 0 @ disable caches
109 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
137 mcr p14, 0, r0, c7, c0, 0 @ go to idle
366 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
416 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
418 mrc p15, 0, r6, c13, c0, 0 @ PID
[all …]
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| D | proc-mohawk.S | 41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
68 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
321 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
345 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
347 mrc p15, 0, r6, c13, c0, 0 @ PID
348 mrc p15, 0, r7, c3, c0, 0 @ domain ID
349 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
[all …]
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| /kernel/linux/linux-5.10/arch/arm/include/debug/ |
| D | icedcc.S | 16 mcr p14, 0, \rd, c0, c5, 0
21 mrc p14, 0, \rx, c0, c1, 0
34 mrc p14, 0, \rx, c0, c1, 0
43 mcr p14, 0, \rd, c8, c0, 0
48 mrc p14, 0, \rx, c14, c0, 0
61 mrc p14, 0, \rx, c14, c0, 0
70 mcr p14, 0, \rd, c1, c0, 0
75 mrc p14, 0, \rx, c0, c0, 0
89 mrc p14, 0, \rx, c0, c0, 0
|
| /kernel/linux/linux-5.10/arch/arm/kernel/ |
| D | hyp-stub.S | 114 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
124 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
131 mrc p15, 0, r7, c1, c0, 0 @ SCTLR
135 mcr p15, 0, r7, c1, c0, 0 @ SCTLR
137 mrc p15, 0, r7, c0, c0, 0 @ MIDR
138 mcr p15, 4, r7, c0, c0, 0 @ VPIDR
140 mrc p15, 0, r7, c0, c0, 5 @ MPIDR
141 mcr p15, 4, r7, c0, c0, 5 @ VMPIDR
145 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
164 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/tidss/ |
| D | tidss_scale_coefs.c | 19 .c0 = { 192, 192, 192, 190, 188, 186, 184, 182, 180, },
25 .c0 = { 200, 202, 204, 202, 200, 196, 192, 188, 184, },
31 .c0 = { 216, 216, 216, 214, 212, 208, 204, 198, 192, },
37 .c0 = { 232, 232, 232, 226, 220, 218, 216, 208, 200, },
43 .c0 = { 264, 262, 260, 254, 248, 242, 236, 226, 216, },
49 .c0 = { 288, 286, 284, 280, 276, 266, 256, 244, 232, },
55 .c0 = { 312, 308, 304, 298, 292, 282, 272, 258, 244, },
61 .c0 = { 336, 332, 328, 320, 312, 300, 288, 272, 256, },
67 .c0 = { 368, 364, 360, 350, 340, 326, 312, 292, 272, },
73 .c0 = { 400, 398, 396, 384, 372, 354, 336, 312, 288, },
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-sunxi/ |
| D | headsmp.S | 25 mrc p15, 0, r1, c0, c0, 0
37 mrc p15, 1, r1, c15, c0, 4
39 mcr p15, 1, r1, c15, c0, 4
42 mrc p15, 1, r1, c15, c0, 0
47 mcr p15, 1, r1, c15, c0, 0
50 mrc p15, 1, r1, c9, c0, 2
53 mcr p15, 1, r1, c9, c0, 2
|
| /kernel/linux/linux-5.10/arch/arm/mach-spear/ |
| D | hotplug.c | 28 " mrc p15, 0, %0, c1, c0, 1\n" in cpu_enter_lowpower()
30 " mcr p15, 0, %0, c1, c0, 1\n" in cpu_enter_lowpower()
31 " mrc p15, 0, %0, c1, c0, 0\n" in cpu_enter_lowpower()
33 " mcr p15, 0, %0, c1, c0, 0\n" in cpu_enter_lowpower()
43 asm volatile("mrc p15, 0, %0, c1, c0, 0\n" in cpu_leave_lowpower()
45 " mcr p15, 0, %0, c1, c0, 0\n" in cpu_leave_lowpower()
46 " mrc p15, 0, %0, c1, c0, 1\n" in cpu_leave_lowpower()
48 " mcr p15, 0, %0, c1, c0, 1\n" in cpu_leave_lowpower()
|
| /kernel/linux/linux-5.10/arch/arm/include/asm/ |
| D | tls.h | 14 mrc p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
15 mcr p15, 0, \tp, c13, c0, 3 @ set TLS register
16 mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register
26 mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
27 mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
28 mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register
82 asm("mcr p15, 0, %0, c13, c0, 3" in set_tls()
105 __asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg)); in get_tpuser()
116 asm("mcr p15, 0, %0, c13, c0, 2" in set_tpuser()
|
| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | sleep44xx.S | 88 mrc p15, 0, r0, c1, c0, 0
90 mcr p15, 0, r0, c1, c0, 0
108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
128 mrcne p15, 0, r0, c1, c0, 1
130 mcrne p15, 0, r0, c1, c0, 1
146 mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
189 mrc p15, 0, r0, c1, c0, 0
192 mcreq p15, 0, r0, c1, c0, 0
201 mrc p15, 0, r0, c1, c0, 1
[all …]
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| D | omap-headsmp.S | 46 mrc p15, 0, r4, c0, c0, 5
64 mrc p15, 0, r4, c0, c0, 5
86 mrc p15, 0, r4, c0, c0, 5
103 mrc p15, 0, r4, c0, c0, 5
|
| /kernel/linux/linux-5.10/arch/arm/plat-versatile/ |
| D | hotplug.c | 30 " mrc p15, 0, %0, c1, c0, 1\n" in versatile_immitation_enter_lowpower()
32 " mcr p15, 0, %0, c1, c0, 1\n" in versatile_immitation_enter_lowpower()
33 " mrc p15, 0, %0, c1, c0, 0\n" in versatile_immitation_enter_lowpower()
35 " mcr p15, 0, %0, c1, c0, 0\n" in versatile_immitation_enter_lowpower()
46 "mrc p15, 0, %0, c1, c0, 0\n" in versatile_immitation_leave_lowpower()
48 " mcr p15, 0, %0, c1, c0, 0\n" in versatile_immitation_leave_lowpower()
49 " mrc p15, 0, %0, c1, c0, 1\n" in versatile_immitation_leave_lowpower()
51 " mcr p15, 0, %0, c1, c0, 1\n" in versatile_immitation_leave_lowpower()
|
| /kernel/liteos_a/arch/arm/arm/src/startup/ |
| D | reset_vector_mp.S | 121 mcr p15, 0, r0, c13, c0, 4
123 mrc p15, 0, r0, c1, c0, 0
127 mcr p15, 0, r0, c1, c0, 0
137 MCR p15, 0, r0, c1, c0, 2
148 mrc p15, 0, r12, c0, c0, 5 /* r12: get cpuid */
227 mrc p15, 0, r12, c0, c0, 5
238 MCR p15, 0, r0, c12, c0, 0
271 mcr p15, 0, r12, c2, c0, 2 /* Initialize the c2 register */
274 mcr p15, 0, r12, c2, c0, 0 /* Set attributes and set temp page table */
277 … mcr p15, 0, r12, c3, c0, 0 /* Set DACR with 0b0111, client and manager domian */
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/compressed/ |
| D | head.S | 32 mcr p14, 0, \ch, c0, c5, 0
38 mcr p14, 0, \ch, c8, c0, 0
44 mcr p14, 0, \ch, c1, c0, 0
139 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
143 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
484 mrc p15, 0, r1, c0, c1, 1 @ read ID_PFR1 register
756 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
795 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
796 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
797 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-tegra/ |
| D | sleep.h | 70 mrc p15, 0, \rd, c0, c0, 5
82 mrc p15, 0, \tmp1, c0, c0, 0
90 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
92 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
96 mrceq p15, 0, \tmp1, c0, c0, 5
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| D | sleep.S | 38 mrc p15, 0, r2, c1, c0, 0
41 mcrne p15, 0, r2, c1, c0, 0
63 mrc p15, 0, r0, c0, c0, 5
68 mrc p15, 0x1, r0, c9, c0, 2
73 mcrne p15, 0x1, r0, c9, c0, 2
114 mrc p15, 0, r3, c1, c0, 0
118 mcr p15, 0, r3, c1, c0, 0
|
| /kernel/linux/linux-5.10/Documentation/admin-guide/media/ |
| D | dvb-usb-gp8psk-cardlist.rst | 16 - 09c0:0200, 09c0:0201
18 - 09c0:0202
20 - 09c0:0203
22 - 09c0:0206
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | stih407-clock.dtsi | 98 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
105 clock-output-names = "clk-s-c0-fs0-ch0",
106 "clk-s-c0-fs0-ch1",
107 "clk-s-c0-fs0-ch2",
108 "clk-s-c0-fs0-ch3";
109 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
116 clk_s_c0_pll0: clk-s-c0-pll0 {
122 clock-output-names = "clk-s-c0-pll0-odf-0";
123 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
126 clk_s_c0_pll1: clk-s-c0-pll1 {
[all …]
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