| /kernel/linux/linux-5.10/arch/arm64/boot/dts/amazon/ |
| D | alpine-v3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/ |
| D | k3-am654.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
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| D | k3-j7200.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/k3.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
16 interrupt-parent = <&gic500>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <1>;
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| D | k3-j721e.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/k3.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
16 interrupt-parent = <&gic500>;
17 #address-cells = <2>;
18 #size-cells = <2>;
39 #address-cells = <1>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/ |
| D | armada-ap806-quad.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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| D | armada-ap807-quad.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap807.dtsi"
12 compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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| D | armada-ap806-dual.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/ |
| D | juno-r2.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
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| D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-lx2160a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
24 #address-cells = <1>;
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| /kernel/linux/linux-5.10/arch/x86/kernel/cpu/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
35 short size; member
40 /* All the cache descriptor types we care about (no TLB or
41 trace cache entries) */
45 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
46 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
48 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
49 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/socionext/ |
| D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | iss4xx-mpic.dts | 15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <100000000>; // 100Mhz :-)
39 timebase-frequency = <100000000>;
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| /kernel/linux/linux-5.10/arch/mips/kernel/ |
| D | bmips_5xxx_init.S | 7 * Copyright (C) 2011-2012 by Broadcom Corporation
28 #define cacheop(kva, size, linesize, op) \ argument
30 addu t1, kva, size ; \
34 addiu t1, t1, -1 ; \
36 9: cache op, 0(t0) ; \
80 /* ZSC L2 Cache Register Access Register Definitions */
111 * Returns: v0 = i cache size, v1 = I cache line size
112 * Description: compute the I-cache size and I-cache line size
129 * the instruction cache:
131 * vi) 0x5 - 0x7: Reserved.
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | mpc8641si-pre.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
8 /dts-v1/;
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&mpic>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
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| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | cache-v6.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v6.S
15 #include "proc-macros.S"
25 * Flush the whole I-cache.
27 * ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
32 * r0 - set to 0
33 * r1 - corrupted
40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
41 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
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| D | cache-v7m.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v7m.S
5 * Based on linux/arch/arm/mm/cache-v7.S
19 #include "proc-macros.S"
21 /* Generic V7M read/write macros for memory mapped cache operations */
48 * dcisw: Invalidate data cache by set/way
55 * dccisw: Clean and invalidate data cache by set/way
62 * dccimvac: Clean and invalidate data cache line by MVA to PoC.
71 * dcimvac: Invalidate data cache line by MVA to PoC
80 * dccmvau: Clean data cache line by MVA to PoU
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| D | proc-xscale.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-xscale.S
25 #include <asm/pgtable-hwdef.h>
28 #include "proc-macros.S"
31 * This is the maximum size of an area which will be flushed. If the area
32 * is larger than this, then we flush the whole cache
37 * the cache line size of the I and D cache
42 * the size of the data cache
47 * Virtual address used to allocate the cache when flushed
56 * Without this the XScale core exhibits cache eviction problems and no one
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| D | proc-xsc3.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-xsc3.S
15 * - ARMv6 Supersections
16 * - Low Locality Reference pages (replaces mini-cache)
17 * - 36-bit addressing
18 * - L2 cache
19 * - Cache coherency if chipset supports it
29 #include <asm/pgtable-hwdef.h>
32 #include "proc-macros.S"
35 * This is the maximum size of an area which will be flushed. If the
[all …]
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| D | cache-v7.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v7.S
15 #include <asm/hardware/cache-b15-rac.h>
17 #include "proc-macros.S"
31 * of cache lines with uninitialized data and uninitialized tags to get
36 * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs
42 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR
44 mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR
51 and r3, r1, r0, lsr #3 @ NumWays - 1
59 1: sub r2, r2, #1 @ NumSets--
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| /kernel/linux/linux-5.10/arch/arm64/mm/ |
| D | cache.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Cache maintenance
15 #include <asm/asm-uaccess.h>
24 * - start - virtual start address of region
25 * - end - virtual end address of region
37 * - start - virtual start address of region
38 * - end - virtual end address of region
67 mov x0, #-EFAULT
75 * Ensure that the I cache is invalid within specified region.
77 * - start - virtual start address of region
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
8 - compatible : Should include one of the following:
9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
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| /kernel/linux/linux-5.10/arch/arc/mm/ |
| D | cache.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARC Cache Management
5 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
6 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
12 #include <linux/cache.h>
44 if (!(p)->line_len) \ in arc_cache_mumbojumbo()
45 n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \ in arc_cache_mumbojumbo()
47 n += scnprintf(buf + n, len - n, \ in arc_cache_mumbojumbo()
48 str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \ in arc_cache_mumbojumbo()
49 (p)->sz_k, (p)->assoc, (p)->line_len, \ in arc_cache_mumbojumbo()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 11 - compatible: Compatible property value should be "altr,nios2-1.0".
12 - reg: Contains CPU index.
13 - interrupt-controller: Specifies that the node is an interrupt controller
14 - #interrupt-cells: Specifies the number of cells needed to encode an
16 - clock-frequency: Contains the clock frequency for CPU, in Hz.
17 - dcache-line-size: Contains data cache line size.
18 - icache-line-size: Contains instruction line size.
19 - dcache-size: Contains data cache size.
20 - icache-size: Contains instruction cache size.
21 - altr,pid-num-bits: Specifies the number of bits to use to represent the process
[all …]
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